2 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
4 * Based on sun4i_backend.c, which is:
5 * Copyright (C) 2015 Free Electrons
6 * Copyright (C) 2015 NextThing Co
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_fb_cma_helper.h>
19 #include <drm/drm_gem_cma_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/component.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/of_device.h>
25 #include <linux/of_graph.h>
26 #include <linux/reset.h>
28 #include "sun4i_drv.h"
29 #include "sun8i_mixer.h"
30 #include "sun8i_ui_layer.h"
31 #include "sun8i_vi_layer.h"
32 #include "sunxi_engine.h"
34 static const struct de2_fmt_info de2_formats
[] = {
36 .drm_fmt
= DRM_FORMAT_ARGB8888
,
37 .de2_fmt
= SUN8I_MIXER_FBFMT_ARGB8888
,
39 .csc
= SUN8I_CSC_MODE_OFF
,
42 .drm_fmt
= DRM_FORMAT_ABGR8888
,
43 .de2_fmt
= SUN8I_MIXER_FBFMT_ABGR8888
,
45 .csc
= SUN8I_CSC_MODE_OFF
,
48 .drm_fmt
= DRM_FORMAT_RGBA8888
,
49 .de2_fmt
= SUN8I_MIXER_FBFMT_RGBA8888
,
51 .csc
= SUN8I_CSC_MODE_OFF
,
54 .drm_fmt
= DRM_FORMAT_BGRA8888
,
55 .de2_fmt
= SUN8I_MIXER_FBFMT_BGRA8888
,
57 .csc
= SUN8I_CSC_MODE_OFF
,
60 .drm_fmt
= DRM_FORMAT_XRGB8888
,
61 .de2_fmt
= SUN8I_MIXER_FBFMT_XRGB8888
,
63 .csc
= SUN8I_CSC_MODE_OFF
,
66 .drm_fmt
= DRM_FORMAT_XBGR8888
,
67 .de2_fmt
= SUN8I_MIXER_FBFMT_XBGR8888
,
69 .csc
= SUN8I_CSC_MODE_OFF
,
72 .drm_fmt
= DRM_FORMAT_RGBX8888
,
73 .de2_fmt
= SUN8I_MIXER_FBFMT_RGBX8888
,
75 .csc
= SUN8I_CSC_MODE_OFF
,
78 .drm_fmt
= DRM_FORMAT_BGRX8888
,
79 .de2_fmt
= SUN8I_MIXER_FBFMT_BGRX8888
,
81 .csc
= SUN8I_CSC_MODE_OFF
,
84 .drm_fmt
= DRM_FORMAT_RGB888
,
85 .de2_fmt
= SUN8I_MIXER_FBFMT_RGB888
,
87 .csc
= SUN8I_CSC_MODE_OFF
,
90 .drm_fmt
= DRM_FORMAT_BGR888
,
91 .de2_fmt
= SUN8I_MIXER_FBFMT_BGR888
,
93 .csc
= SUN8I_CSC_MODE_OFF
,
96 .drm_fmt
= DRM_FORMAT_RGB565
,
97 .de2_fmt
= SUN8I_MIXER_FBFMT_RGB565
,
99 .csc
= SUN8I_CSC_MODE_OFF
,
102 .drm_fmt
= DRM_FORMAT_BGR565
,
103 .de2_fmt
= SUN8I_MIXER_FBFMT_BGR565
,
105 .csc
= SUN8I_CSC_MODE_OFF
,
108 .drm_fmt
= DRM_FORMAT_ARGB4444
,
109 .de2_fmt
= SUN8I_MIXER_FBFMT_ARGB4444
,
111 .csc
= SUN8I_CSC_MODE_OFF
,
114 .drm_fmt
= DRM_FORMAT_ABGR4444
,
115 .de2_fmt
= SUN8I_MIXER_FBFMT_ABGR4444
,
117 .csc
= SUN8I_CSC_MODE_OFF
,
120 .drm_fmt
= DRM_FORMAT_RGBA4444
,
121 .de2_fmt
= SUN8I_MIXER_FBFMT_RGBA4444
,
123 .csc
= SUN8I_CSC_MODE_OFF
,
126 .drm_fmt
= DRM_FORMAT_BGRA4444
,
127 .de2_fmt
= SUN8I_MIXER_FBFMT_BGRA4444
,
129 .csc
= SUN8I_CSC_MODE_OFF
,
132 .drm_fmt
= DRM_FORMAT_ARGB1555
,
133 .de2_fmt
= SUN8I_MIXER_FBFMT_ARGB1555
,
135 .csc
= SUN8I_CSC_MODE_OFF
,
138 .drm_fmt
= DRM_FORMAT_ABGR1555
,
139 .de2_fmt
= SUN8I_MIXER_FBFMT_ABGR1555
,
141 .csc
= SUN8I_CSC_MODE_OFF
,
144 .drm_fmt
= DRM_FORMAT_RGBA5551
,
145 .de2_fmt
= SUN8I_MIXER_FBFMT_RGBA5551
,
147 .csc
= SUN8I_CSC_MODE_OFF
,
150 .drm_fmt
= DRM_FORMAT_BGRA5551
,
151 .de2_fmt
= SUN8I_MIXER_FBFMT_BGRA5551
,
153 .csc
= SUN8I_CSC_MODE_OFF
,
156 .drm_fmt
= DRM_FORMAT_UYVY
,
157 .de2_fmt
= SUN8I_MIXER_FBFMT_UYVY
,
159 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
162 .drm_fmt
= DRM_FORMAT_VYUY
,
163 .de2_fmt
= SUN8I_MIXER_FBFMT_VYUY
,
165 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
168 .drm_fmt
= DRM_FORMAT_YUYV
,
169 .de2_fmt
= SUN8I_MIXER_FBFMT_YUYV
,
171 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
174 .drm_fmt
= DRM_FORMAT_YVYU
,
175 .de2_fmt
= SUN8I_MIXER_FBFMT_YVYU
,
177 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
180 .drm_fmt
= DRM_FORMAT_NV16
,
181 .de2_fmt
= SUN8I_MIXER_FBFMT_NV16
,
183 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
186 .drm_fmt
= DRM_FORMAT_NV61
,
187 .de2_fmt
= SUN8I_MIXER_FBFMT_NV61
,
189 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
192 .drm_fmt
= DRM_FORMAT_NV12
,
193 .de2_fmt
= SUN8I_MIXER_FBFMT_NV12
,
195 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
198 .drm_fmt
= DRM_FORMAT_NV21
,
199 .de2_fmt
= SUN8I_MIXER_FBFMT_NV21
,
201 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
204 .drm_fmt
= DRM_FORMAT_YUV444
,
205 .de2_fmt
= SUN8I_MIXER_FBFMT_RGB888
,
207 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
210 .drm_fmt
= DRM_FORMAT_YUV422
,
211 .de2_fmt
= SUN8I_MIXER_FBFMT_YUV422
,
213 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
216 .drm_fmt
= DRM_FORMAT_YUV420
,
217 .de2_fmt
= SUN8I_MIXER_FBFMT_YUV420
,
219 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
222 .drm_fmt
= DRM_FORMAT_YUV411
,
223 .de2_fmt
= SUN8I_MIXER_FBFMT_YUV411
,
225 .csc
= SUN8I_CSC_MODE_YUV2RGB
,
228 .drm_fmt
= DRM_FORMAT_YVU444
,
229 .de2_fmt
= SUN8I_MIXER_FBFMT_RGB888
,
231 .csc
= SUN8I_CSC_MODE_YVU2RGB
,
234 .drm_fmt
= DRM_FORMAT_YVU422
,
235 .de2_fmt
= SUN8I_MIXER_FBFMT_YUV422
,
237 .csc
= SUN8I_CSC_MODE_YVU2RGB
,
240 .drm_fmt
= DRM_FORMAT_YVU420
,
241 .de2_fmt
= SUN8I_MIXER_FBFMT_YUV420
,
243 .csc
= SUN8I_CSC_MODE_YVU2RGB
,
246 .drm_fmt
= DRM_FORMAT_YVU411
,
247 .de2_fmt
= SUN8I_MIXER_FBFMT_YUV411
,
249 .csc
= SUN8I_CSC_MODE_YVU2RGB
,
253 const struct de2_fmt_info
*sun8i_mixer_format_info(u32 format
)
257 for (i
= 0; i
< ARRAY_SIZE(de2_formats
); ++i
)
258 if (de2_formats
[i
].drm_fmt
== format
)
259 return &de2_formats
[i
];
264 static void sun8i_mixer_commit(struct sunxi_engine
*engine
)
266 DRM_DEBUG_DRIVER("Committing changes\n");
268 regmap_write(engine
->regs
, SUN8I_MIXER_GLOBAL_DBUFF
,
269 SUN8I_MIXER_GLOBAL_DBUFF_ENABLE
);
272 static struct drm_plane
**sun8i_layers_init(struct drm_device
*drm
,
273 struct sunxi_engine
*engine
)
275 struct drm_plane
**planes
;
276 struct sun8i_mixer
*mixer
= engine_to_sun8i_mixer(engine
);
279 planes
= devm_kcalloc(drm
->dev
,
280 mixer
->cfg
->vi_num
+ mixer
->cfg
->ui_num
+ 1,
281 sizeof(*planes
), GFP_KERNEL
);
283 return ERR_PTR(-ENOMEM
);
285 for (i
= 0; i
< mixer
->cfg
->vi_num
; i
++) {
286 struct sun8i_vi_layer
*layer
;
288 layer
= sun8i_vi_layer_init_one(drm
, mixer
, i
);
291 "Couldn't initialize overlay plane\n");
292 return ERR_CAST(layer
);
295 planes
[i
] = &layer
->plane
;
298 for (i
= 0; i
< mixer
->cfg
->ui_num
; i
++) {
299 struct sun8i_ui_layer
*layer
;
301 layer
= sun8i_ui_layer_init_one(drm
, mixer
, i
);
303 dev_err(drm
->dev
, "Couldn't initialize %s plane\n",
304 i
? "overlay" : "primary");
305 return ERR_CAST(layer
);
308 planes
[mixer
->cfg
->vi_num
+ i
] = &layer
->plane
;
314 static const struct sunxi_engine_ops sun8i_engine_ops
= {
315 .commit
= sun8i_mixer_commit
,
316 .layers_init
= sun8i_layers_init
,
319 static struct regmap_config sun8i_mixer_regmap_config
= {
323 .max_register
= 0xbfffc, /* guessed */
326 static int sun8i_mixer_of_get_id(struct device_node
*node
)
328 struct device_node
*port
, *ep
;
331 /* output is port 1 */
332 port
= of_graph_get_port_by_id(node
, 1);
336 /* try to find downstream endpoint */
337 for_each_available_child_of_node(port
, ep
) {
338 struct device_node
*remote
;
341 remote
= of_graph_get_remote_endpoint(ep
);
345 ret
= of_property_read_u32(remote
, "reg", ®
);
362 static int sun8i_mixer_bind(struct device
*dev
, struct device
*master
,
365 struct platform_device
*pdev
= to_platform_device(dev
);
366 struct drm_device
*drm
= data
;
367 struct sun4i_drv
*drv
= drm
->dev_private
;
368 struct sun8i_mixer
*mixer
;
369 struct resource
*res
;
376 * The mixer uses single 32-bit register to store memory
377 * addresses, so that it cannot deal with 64-bit memory
379 * Restrict the DMA mask so that the mixer won't be
380 * allocated some memory that is too high.
382 ret
= dma_set_mask(dev
, DMA_BIT_MASK(32));
384 dev_err(dev
, "Cannot do 32-bit DMA.\n");
388 mixer
= devm_kzalloc(dev
, sizeof(*mixer
), GFP_KERNEL
);
391 dev_set_drvdata(dev
, mixer
);
392 mixer
->engine
.ops
= &sun8i_engine_ops
;
393 mixer
->engine
.node
= dev
->of_node
;
396 * While this function can fail, we shouldn't do anything
397 * if this happens. Some early DE2 DT entries don't provide
398 * mixer id but work nevertheless because matching between
399 * TCON and mixer is done by comparing node pointers (old
400 * way) instead comparing ids. If this function fails and
401 * id is needed, it will fail during id matching anyway.
403 mixer
->engine
.id
= sun8i_mixer_of_get_id(dev
->of_node
);
405 mixer
->cfg
= of_device_get_match_data(dev
);
409 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
410 regs
= devm_ioremap_resource(dev
, res
);
412 return PTR_ERR(regs
);
414 mixer
->engine
.regs
= devm_regmap_init_mmio(dev
, regs
,
415 &sun8i_mixer_regmap_config
);
416 if (IS_ERR(mixer
->engine
.regs
)) {
417 dev_err(dev
, "Couldn't create the mixer regmap\n");
418 return PTR_ERR(mixer
->engine
.regs
);
421 mixer
->reset
= devm_reset_control_get(dev
, NULL
);
422 if (IS_ERR(mixer
->reset
)) {
423 dev_err(dev
, "Couldn't get our reset line\n");
424 return PTR_ERR(mixer
->reset
);
427 ret
= reset_control_deassert(mixer
->reset
);
429 dev_err(dev
, "Couldn't deassert our reset line\n");
433 mixer
->bus_clk
= devm_clk_get(dev
, "bus");
434 if (IS_ERR(mixer
->bus_clk
)) {
435 dev_err(dev
, "Couldn't get the mixer bus clock\n");
436 ret
= PTR_ERR(mixer
->bus_clk
);
437 goto err_assert_reset
;
439 clk_prepare_enable(mixer
->bus_clk
);
441 mixer
->mod_clk
= devm_clk_get(dev
, "mod");
442 if (IS_ERR(mixer
->mod_clk
)) {
443 dev_err(dev
, "Couldn't get the mixer module clock\n");
444 ret
= PTR_ERR(mixer
->mod_clk
);
445 goto err_disable_bus_clk
;
449 * It seems that we need to enforce that rate for whatever
450 * reason for the mixer to be functional. Make sure it's the
453 if (mixer
->cfg
->mod_rate
)
454 clk_set_rate(mixer
->mod_clk
, mixer
->cfg
->mod_rate
);
456 clk_prepare_enable(mixer
->mod_clk
);
458 list_add_tail(&mixer
->engine
.list
, &drv
->engine_list
);
460 base
= sun8i_blender_base(mixer
);
462 /* Reset registers and disable unused sub-engines */
463 if (mixer
->cfg
->is_de3
) {
464 for (i
= 0; i
< DE3_MIXER_UNIT_SIZE
; i
+= 4)
465 regmap_write(mixer
->engine
.regs
, i
, 0);
467 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_FCE_EN
, 0);
468 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_PEAK_EN
, 0);
469 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_LCTI_EN
, 0);
470 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_BLS_EN
, 0);
471 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_FCC_EN
, 0);
472 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_DNS_EN
, 0);
473 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_DRC_EN
, 0);
474 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_FMT_EN
, 0);
475 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_CDC0_EN
, 0);
476 regmap_write(mixer
->engine
.regs
, SUN50I_MIXER_CDC1_EN
, 0);
478 for (i
= 0; i
< DE2_MIXER_UNIT_SIZE
; i
+= 4)
479 regmap_write(mixer
->engine
.regs
, i
, 0);
481 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_FCE_EN
, 0);
482 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_BWS_EN
, 0);
483 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_LTI_EN
, 0);
484 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_PEAK_EN
, 0);
485 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_ASE_EN
, 0);
486 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_FCC_EN
, 0);
487 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_DCSC_EN
, 0);
490 /* Enable the mixer */
491 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_GLOBAL_CTL
,
492 SUN8I_MIXER_GLOBAL_CTL_RT_EN
);
494 /* Set background color to black */
495 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_BLEND_BKCOLOR(base
),
496 SUN8I_MIXER_BLEND_COLOR_BLACK
);
499 * Set fill color of bottom plane to black. Generally not needed
500 * except when VI plane is at bottom (zpos = 0) and enabled.
502 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_BLEND_PIPE_CTL(base
),
503 SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
504 regmap_write(mixer
->engine
.regs
, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base
, 0),
505 SUN8I_MIXER_BLEND_COLOR_BLACK
);
507 plane_cnt
= mixer
->cfg
->vi_num
+ mixer
->cfg
->ui_num
;
508 for (i
= 0; i
< plane_cnt
; i
++)
509 regmap_write(mixer
->engine
.regs
,
510 SUN8I_MIXER_BLEND_MODE(base
, i
),
511 SUN8I_MIXER_BLEND_MODE_DEF
);
513 regmap_update_bits(mixer
->engine
.regs
, SUN8I_MIXER_BLEND_PIPE_CTL(base
),
514 SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK
, 0);
519 clk_disable_unprepare(mixer
->bus_clk
);
521 reset_control_assert(mixer
->reset
);
525 static void sun8i_mixer_unbind(struct device
*dev
, struct device
*master
,
528 struct sun8i_mixer
*mixer
= dev_get_drvdata(dev
);
530 list_del(&mixer
->engine
.list
);
532 clk_disable_unprepare(mixer
->mod_clk
);
533 clk_disable_unprepare(mixer
->bus_clk
);
534 reset_control_assert(mixer
->reset
);
537 static const struct component_ops sun8i_mixer_ops
= {
538 .bind
= sun8i_mixer_bind
,
539 .unbind
= sun8i_mixer_unbind
,
542 static int sun8i_mixer_probe(struct platform_device
*pdev
)
544 return component_add(&pdev
->dev
, &sun8i_mixer_ops
);
547 static int sun8i_mixer_remove(struct platform_device
*pdev
)
549 component_del(&pdev
->dev
, &sun8i_mixer_ops
);
554 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg
= {
561 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg
= {
568 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg
= {
570 .mod_rate
= 432000000,
576 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg
= {
578 .mod_rate
= 297000000,
584 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg
= {
586 .mod_rate
= 297000000,
592 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg
= {
597 .mod_rate
= 150000000,
600 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg
= {
602 .mod_rate
= 297000000,
608 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg
= {
610 .mod_rate
= 297000000,
616 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg
= {
619 .mod_rate
= 600000000,
625 static const struct of_device_id sun8i_mixer_of_table
[] = {
627 .compatible
= "allwinner,sun8i-a83t-de2-mixer-0",
628 .data
= &sun8i_a83t_mixer0_cfg
,
631 .compatible
= "allwinner,sun8i-a83t-de2-mixer-1",
632 .data
= &sun8i_a83t_mixer1_cfg
,
635 .compatible
= "allwinner,sun8i-h3-de2-mixer-0",
636 .data
= &sun8i_h3_mixer0_cfg
,
639 .compatible
= "allwinner,sun8i-r40-de2-mixer-0",
640 .data
= &sun8i_r40_mixer0_cfg
,
643 .compatible
= "allwinner,sun8i-r40-de2-mixer-1",
644 .data
= &sun8i_r40_mixer1_cfg
,
647 .compatible
= "allwinner,sun8i-v3s-de2-mixer",
648 .data
= &sun8i_v3s_mixer_cfg
,
651 .compatible
= "allwinner,sun50i-a64-de2-mixer-0",
652 .data
= &sun50i_a64_mixer0_cfg
,
655 .compatible
= "allwinner,sun50i-a64-de2-mixer-1",
656 .data
= &sun50i_a64_mixer1_cfg
,
659 .compatible
= "allwinner,sun50i-h6-de3-mixer-0",
660 .data
= &sun50i_h6_mixer0_cfg
,
664 MODULE_DEVICE_TABLE(of
, sun8i_mixer_of_table
);
666 static struct platform_driver sun8i_mixer_platform_driver
= {
667 .probe
= sun8i_mixer_probe
,
668 .remove
= sun8i_mixer_remove
,
670 .name
= "sun8i-mixer",
671 .of_match_table
= sun8i_mixer_of_table
,
674 module_platform_driver(sun8i_mixer_platform_driver
);
676 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
677 MODULE_DESCRIPTION("Allwinner DE2 Mixer driver");
678 MODULE_LICENSE("GPL");