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[thirdparty/linux.git] / drivers / gpu / drm / tegra / dc.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/iommu.h>
13 #include <linux/of_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/reset.h>
16
17 #include <soc/tegra/pmc.h>
18
19 #include "dc.h"
20 #include "drm.h"
21 #include "gem.h"
22 #include "hub.h"
23 #include "plane.h"
24
25 #include <drm/drm_atomic.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_plane_helper.h>
28
29 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats)
30 {
31 stats->frames = 0;
32 stats->vblank = 0;
33 stats->underflow = 0;
34 stats->overflow = 0;
35 }
36
37 /* Reads the active copy of a register. */
38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset)
39 {
40 u32 value;
41
42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
43 value = tegra_dc_readl(dc, offset);
44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
45
46 return value;
47 }
48
49 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane,
50 unsigned int offset)
51 {
52 if (offset >= 0x500 && offset <= 0x638) {
53 offset = 0x000 + (offset - 0x500);
54 return plane->offset + offset;
55 }
56
57 if (offset >= 0x700 && offset <= 0x719) {
58 offset = 0x180 + (offset - 0x700);
59 return plane->offset + offset;
60 }
61
62 if (offset >= 0x800 && offset <= 0x839) {
63 offset = 0x1c0 + (offset - 0x800);
64 return plane->offset + offset;
65 }
66
67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset);
68
69 return plane->offset + offset;
70 }
71
72 static inline u32 tegra_plane_readl(struct tegra_plane *plane,
73 unsigned int offset)
74 {
75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset));
76 }
77
78 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value,
79 unsigned int offset)
80 {
81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset));
82 }
83
84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev)
85 {
86 struct device_node *np = dc->dev->of_node;
87 struct of_phandle_iterator it;
88 int err;
89
90 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0)
91 if (it.node == dev->of_node)
92 return true;
93
94 return false;
95 }
96
97 /*
98 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
99 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy.
100 * Latching happens mmediately if the display controller is in STOP mode or
101 * on the next frame boundary otherwise.
102 *
103 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
104 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits
105 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched
106 * into the ACTIVE copy, either immediately if the display controller is in
107 * STOP mode, or at the next frame boundary otherwise.
108 */
109 void tegra_dc_commit(struct tegra_dc *dc)
110 {
111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
113 }
114
115 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
116 unsigned int bpp)
117 {
118 fixed20_12 outf = dfixed_init(out);
119 fixed20_12 inf = dfixed_init(in);
120 u32 dda_inc;
121 int max;
122
123 if (v)
124 max = 15;
125 else {
126 switch (bpp) {
127 case 2:
128 max = 8;
129 break;
130
131 default:
132 WARN_ON_ONCE(1);
133 /* fallthrough */
134 case 4:
135 max = 4;
136 break;
137 }
138 }
139
140 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
141 inf.full -= dfixed_const(1);
142
143 dda_inc = dfixed_div(inf, outf);
144 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
145
146 return dda_inc;
147 }
148
149 static inline u32 compute_initial_dda(unsigned int in)
150 {
151 fixed20_12 inf = dfixed_init(in);
152 return dfixed_frac(inf);
153 }
154
155 static void tegra_dc_setup_window(struct tegra_plane *plane,
156 const struct tegra_dc_window *window)
157 {
158 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
159 struct tegra_dc *dc = plane->dc;
160 bool yuv, planar;
161 u32 value;
162
163 /*
164 * For YUV planar modes, the number of bytes per pixel takes into
165 * account only the luma component and therefore is 1.
166 */
167 yuv = tegra_plane_format_is_yuv(window->format, &planar);
168 if (!yuv)
169 bpp = window->bits_per_pixel / 8;
170 else
171 bpp = planar ? 1 : 2;
172
173 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH);
174 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP);
175
176 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
177 tegra_plane_writel(plane, value, DC_WIN_POSITION);
178
179 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
180 tegra_plane_writel(plane, value, DC_WIN_SIZE);
181
182 h_offset = window->src.x * bpp;
183 v_offset = window->src.y;
184 h_size = window->src.w * bpp;
185 v_size = window->src.h;
186
187 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
188 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE);
189
190 /*
191 * For DDA computations the number of bytes per pixel for YUV planar
192 * modes needs to take into account all Y, U and V components.
193 */
194 if (yuv && planar)
195 bpp = 2;
196
197 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
198 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
199
200 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
201 tegra_plane_writel(plane, value, DC_WIN_DDA_INC);
202
203 h_dda = compute_initial_dda(window->src.x);
204 v_dda = compute_initial_dda(window->src.y);
205
206 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA);
207 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA);
208
209 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE);
210 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE);
211
212 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR);
213
214 if (yuv && planar) {
215 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U);
216 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V);
217 value = window->stride[1] << 16 | window->stride[0];
218 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE);
219 } else {
220 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE);
221 }
222
223 if (window->bottom_up)
224 v_offset += window->src.h - 1;
225
226 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET);
227 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET);
228
229 if (dc->soc->supports_block_linear) {
230 unsigned long height = window->tiling.value;
231
232 switch (window->tiling.mode) {
233 case TEGRA_BO_TILING_MODE_PITCH:
234 value = DC_WINBUF_SURFACE_KIND_PITCH;
235 break;
236
237 case TEGRA_BO_TILING_MODE_TILED:
238 value = DC_WINBUF_SURFACE_KIND_TILED;
239 break;
240
241 case TEGRA_BO_TILING_MODE_BLOCK:
242 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
243 DC_WINBUF_SURFACE_KIND_BLOCK;
244 break;
245 }
246
247 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND);
248 } else {
249 switch (window->tiling.mode) {
250 case TEGRA_BO_TILING_MODE_PITCH:
251 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
252 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
253 break;
254
255 case TEGRA_BO_TILING_MODE_TILED:
256 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
257 DC_WIN_BUFFER_ADDR_MODE_TILE;
258 break;
259
260 case TEGRA_BO_TILING_MODE_BLOCK:
261 /*
262 * No need to handle this here because ->atomic_check
263 * will already have filtered it out.
264 */
265 break;
266 }
267
268 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE);
269 }
270
271 value = WIN_ENABLE;
272
273 if (yuv) {
274 /* setup default colorspace conversion coefficients */
275 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF);
276 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB);
277 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR);
278 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR);
279 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG);
280 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG);
281 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB);
282 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB);
283
284 value |= CSC_ENABLE;
285 } else if (window->bits_per_pixel < 24) {
286 value |= COLOR_EXPAND;
287 }
288
289 if (window->bottom_up)
290 value |= V_DIRECTION;
291
292 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS);
293
294 /*
295 * Disable blending and assume Window A is the bottom-most window,
296 * Window C is the top-most window and Window B is in the middle.
297 */
298 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_NOKEY);
299 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_1WIN);
300
301 switch (plane->index) {
302 case 0:
303 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_X);
304 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y);
305 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY);
306 break;
307
308 case 1:
309 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X);
310 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_2WIN_Y);
311 tegra_plane_writel(plane, 0x000000, DC_WIN_BLEND_3WIN_XY);
312 break;
313
314 case 2:
315 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_X);
316 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_2WIN_Y);
317 tegra_plane_writel(plane, 0xffff00, DC_WIN_BLEND_3WIN_XY);
318 break;
319 }
320 }
321
322 static const u32 tegra20_primary_formats[] = {
323 DRM_FORMAT_ARGB4444,
324 DRM_FORMAT_ARGB1555,
325 DRM_FORMAT_RGB565,
326 DRM_FORMAT_RGBA5551,
327 DRM_FORMAT_ABGR8888,
328 DRM_FORMAT_ARGB8888,
329 };
330
331 static const u32 tegra114_primary_formats[] = {
332 DRM_FORMAT_ARGB4444,
333 DRM_FORMAT_ARGB1555,
334 DRM_FORMAT_RGB565,
335 DRM_FORMAT_RGBA5551,
336 DRM_FORMAT_ABGR8888,
337 DRM_FORMAT_ARGB8888,
338 /* new on Tegra114 */
339 DRM_FORMAT_ABGR4444,
340 DRM_FORMAT_ABGR1555,
341 DRM_FORMAT_BGRA5551,
342 DRM_FORMAT_XRGB1555,
343 DRM_FORMAT_RGBX5551,
344 DRM_FORMAT_XBGR1555,
345 DRM_FORMAT_BGRX5551,
346 DRM_FORMAT_BGR565,
347 DRM_FORMAT_BGRA8888,
348 DRM_FORMAT_RGBA8888,
349 DRM_FORMAT_XRGB8888,
350 DRM_FORMAT_XBGR8888,
351 };
352
353 static const u32 tegra124_primary_formats[] = {
354 DRM_FORMAT_ARGB4444,
355 DRM_FORMAT_ARGB1555,
356 DRM_FORMAT_RGB565,
357 DRM_FORMAT_RGBA5551,
358 DRM_FORMAT_ABGR8888,
359 DRM_FORMAT_ARGB8888,
360 /* new on Tegra114 */
361 DRM_FORMAT_ABGR4444,
362 DRM_FORMAT_ABGR1555,
363 DRM_FORMAT_BGRA5551,
364 DRM_FORMAT_XRGB1555,
365 DRM_FORMAT_RGBX5551,
366 DRM_FORMAT_XBGR1555,
367 DRM_FORMAT_BGRX5551,
368 DRM_FORMAT_BGR565,
369 DRM_FORMAT_BGRA8888,
370 DRM_FORMAT_RGBA8888,
371 DRM_FORMAT_XRGB8888,
372 DRM_FORMAT_XBGR8888,
373 /* new on Tegra124 */
374 DRM_FORMAT_RGBX8888,
375 DRM_FORMAT_BGRX8888,
376 };
377
378 static int tegra_plane_atomic_check(struct drm_plane *plane,
379 struct drm_plane_state *state)
380 {
381 struct tegra_plane_state *plane_state = to_tegra_plane_state(state);
382 struct tegra_bo_tiling *tiling = &plane_state->tiling;
383 struct tegra_plane *tegra = to_tegra_plane(plane);
384 struct tegra_dc *dc = to_tegra_dc(state->crtc);
385 int err;
386
387 /* no need for further checks if the plane is being disabled */
388 if (!state->crtc)
389 return 0;
390
391 err = tegra_plane_format(state->fb->format->format,
392 &plane_state->format,
393 &plane_state->swap);
394 if (err < 0)
395 return err;
396
397 err = tegra_fb_get_tiling(state->fb, tiling);
398 if (err < 0)
399 return err;
400
401 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK &&
402 !dc->soc->supports_block_linear) {
403 DRM_ERROR("hardware doesn't support block linear mode\n");
404 return -EINVAL;
405 }
406
407 /*
408 * Tegra doesn't support different strides for U and V planes so we
409 * error out if the user tries to display a framebuffer with such a
410 * configuration.
411 */
412 if (state->fb->format->num_planes > 2) {
413 if (state->fb->pitches[2] != state->fb->pitches[1]) {
414 DRM_ERROR("unsupported UV-plane configuration\n");
415 return -EINVAL;
416 }
417 }
418
419 err = tegra_plane_state_add(tegra, state);
420 if (err < 0)
421 return err;
422
423 return 0;
424 }
425
426 static void tegra_plane_atomic_disable(struct drm_plane *plane,
427 struct drm_plane_state *old_state)
428 {
429 struct tegra_plane *p = to_tegra_plane(plane);
430 u32 value;
431
432 /* rien ne va plus */
433 if (!old_state || !old_state->crtc)
434 return;
435
436 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS);
437 value &= ~WIN_ENABLE;
438 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS);
439 }
440
441 static void tegra_plane_atomic_update(struct drm_plane *plane,
442 struct drm_plane_state *old_state)
443 {
444 struct tegra_plane_state *state = to_tegra_plane_state(plane->state);
445 struct drm_framebuffer *fb = plane->state->fb;
446 struct tegra_plane *p = to_tegra_plane(plane);
447 struct tegra_dc_window window;
448 unsigned int i;
449
450 /* rien ne va plus */
451 if (!plane->state->crtc || !plane->state->fb)
452 return;
453
454 if (!plane->state->visible)
455 return tegra_plane_atomic_disable(plane, old_state);
456
457 memset(&window, 0, sizeof(window));
458 window.src.x = plane->state->src.x1 >> 16;
459 window.src.y = plane->state->src.y1 >> 16;
460 window.src.w = drm_rect_width(&plane->state->src) >> 16;
461 window.src.h = drm_rect_height(&plane->state->src) >> 16;
462 window.dst.x = plane->state->dst.x1;
463 window.dst.y = plane->state->dst.y1;
464 window.dst.w = drm_rect_width(&plane->state->dst);
465 window.dst.h = drm_rect_height(&plane->state->dst);
466 window.bits_per_pixel = fb->format->cpp[0] * 8;
467 window.bottom_up = tegra_fb_is_bottom_up(fb);
468
469 /* copy from state */
470 window.tiling = state->tiling;
471 window.format = state->format;
472 window.swap = state->swap;
473
474 for (i = 0; i < fb->format->num_planes; i++) {
475 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
476
477 window.base[i] = bo->paddr + fb->offsets[i];
478
479 /*
480 * Tegra uses a shared stride for UV planes. Framebuffers are
481 * already checked for this in the tegra_plane_atomic_check()
482 * function, so it's safe to ignore the V-plane pitch here.
483 */
484 if (i < 2)
485 window.stride[i] = fb->pitches[i];
486 }
487
488 tegra_dc_setup_window(p, &window);
489 }
490
491 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = {
492 .atomic_check = tegra_plane_atomic_check,
493 .atomic_disable = tegra_plane_atomic_disable,
494 .atomic_update = tegra_plane_atomic_update,
495 };
496
497 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm,
498 struct tegra_dc *dc)
499 {
500 /*
501 * Ideally this would use drm_crtc_mask(), but that would require the
502 * CRTC to already be in the mode_config's list of CRTCs. However, it
503 * will only be added to that list in the drm_crtc_init_with_planes()
504 * (in tegra_dc_init()), which in turn requires registration of these
505 * planes. So we have ourselves a nice little chicken and egg problem
506 * here.
507 *
508 * We work around this by manually creating the mask from the number
509 * of CRTCs that have been registered, and should therefore always be
510 * the same as drm_crtc_index() after registration.
511 */
512 unsigned long possible_crtcs = 1 << drm->mode_config.num_crtc;
513 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY;
514 struct tegra_plane *plane;
515 unsigned int num_formats;
516 const u32 *formats;
517 int err;
518
519 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
520 if (!plane)
521 return ERR_PTR(-ENOMEM);
522
523 /* Always use window A as primary window */
524 plane->offset = 0xa00;
525 plane->index = 0;
526 plane->depth = 255;
527 plane->dc = dc;
528
529 num_formats = dc->soc->num_primary_formats;
530 formats = dc->soc->primary_formats;
531
532 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs,
533 &tegra_plane_funcs, formats,
534 num_formats, NULL, type, NULL);
535 if (err < 0) {
536 kfree(plane);
537 return ERR_PTR(err);
538 }
539
540 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
541
542 return &plane->base;
543 }
544
545 static const u32 tegra_cursor_plane_formats[] = {
546 DRM_FORMAT_RGBA8888,
547 };
548
549 static int tegra_cursor_atomic_check(struct drm_plane *plane,
550 struct drm_plane_state *state)
551 {
552 struct tegra_plane *tegra = to_tegra_plane(plane);
553 int err;
554
555 /* no need for further checks if the plane is being disabled */
556 if (!state->crtc)
557 return 0;
558
559 /* scaling not supported for cursor */
560 if ((state->src_w >> 16 != state->crtc_w) ||
561 (state->src_h >> 16 != state->crtc_h))
562 return -EINVAL;
563
564 /* only square cursors supported */
565 if (state->src_w != state->src_h)
566 return -EINVAL;
567
568 if (state->crtc_w != 32 && state->crtc_w != 64 &&
569 state->crtc_w != 128 && state->crtc_w != 256)
570 return -EINVAL;
571
572 err = tegra_plane_state_add(tegra, state);
573 if (err < 0)
574 return err;
575
576 return 0;
577 }
578
579 static void tegra_cursor_atomic_update(struct drm_plane *plane,
580 struct drm_plane_state *old_state)
581 {
582 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0);
583 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc);
584 struct drm_plane_state *state = plane->state;
585 u32 value = CURSOR_CLIP_DISPLAY;
586
587 /* rien ne va plus */
588 if (!plane->state->crtc || !plane->state->fb)
589 return;
590
591 switch (state->crtc_w) {
592 case 32:
593 value |= CURSOR_SIZE_32x32;
594 break;
595
596 case 64:
597 value |= CURSOR_SIZE_64x64;
598 break;
599
600 case 128:
601 value |= CURSOR_SIZE_128x128;
602 break;
603
604 case 256:
605 value |= CURSOR_SIZE_256x256;
606 break;
607
608 default:
609 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w,
610 state->crtc_h);
611 return;
612 }
613
614 value |= (bo->paddr >> 10) & 0x3fffff;
615 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR);
616
617 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
618 value = (bo->paddr >> 32) & 0x3;
619 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI);
620 #endif
621
622 /* enable cursor and set blend mode */
623 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
624 value |= CURSOR_ENABLE;
625 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
626
627 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
628 value &= ~CURSOR_DST_BLEND_MASK;
629 value &= ~CURSOR_SRC_BLEND_MASK;
630 value |= CURSOR_MODE_NORMAL;
631 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
632 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
633 value |= CURSOR_ALPHA;
634 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
635
636 /* position the cursor */
637 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff);
638 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
639 }
640
641 static void tegra_cursor_atomic_disable(struct drm_plane *plane,
642 struct drm_plane_state *old_state)
643 {
644 struct tegra_dc *dc;
645 u32 value;
646
647 /* rien ne va plus */
648 if (!old_state || !old_state->crtc)
649 return;
650
651 dc = to_tegra_dc(old_state->crtc);
652
653 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
654 value &= ~CURSOR_ENABLE;
655 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
656 }
657
658 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = {
659 .atomic_check = tegra_cursor_atomic_check,
660 .atomic_update = tegra_cursor_atomic_update,
661 .atomic_disable = tegra_cursor_atomic_disable,
662 };
663
664 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm,
665 struct tegra_dc *dc)
666 {
667 struct tegra_plane *plane;
668 unsigned int num_formats;
669 const u32 *formats;
670 int err;
671
672 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
673 if (!plane)
674 return ERR_PTR(-ENOMEM);
675
676 /*
677 * This index is kind of fake. The cursor isn't a regular plane, but
678 * its update and activation request bits in DC_CMD_STATE_CONTROL do
679 * use the same programming. Setting this fake index here allows the
680 * code in tegra_add_plane_state() to do the right thing without the
681 * need to special-casing the cursor plane.
682 */
683 plane->index = 6;
684 plane->dc = dc;
685
686 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats);
687 formats = tegra_cursor_plane_formats;
688
689 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
690 &tegra_plane_funcs, formats,
691 num_formats, NULL,
692 DRM_PLANE_TYPE_CURSOR, NULL);
693 if (err < 0) {
694 kfree(plane);
695 return ERR_PTR(err);
696 }
697
698 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs);
699
700 return &plane->base;
701 }
702
703 static const u32 tegra20_overlay_formats[] = {
704 DRM_FORMAT_ARGB4444,
705 DRM_FORMAT_ARGB1555,
706 DRM_FORMAT_RGB565,
707 DRM_FORMAT_RGBA5551,
708 DRM_FORMAT_ABGR8888,
709 DRM_FORMAT_ARGB8888,
710 /* planar formats */
711 DRM_FORMAT_UYVY,
712 DRM_FORMAT_YUYV,
713 DRM_FORMAT_YUV420,
714 DRM_FORMAT_YUV422,
715 };
716
717 static const u32 tegra114_overlay_formats[] = {
718 DRM_FORMAT_ARGB4444,
719 DRM_FORMAT_ARGB1555,
720 DRM_FORMAT_RGB565,
721 DRM_FORMAT_RGBA5551,
722 DRM_FORMAT_ABGR8888,
723 DRM_FORMAT_ARGB8888,
724 /* new on Tegra114 */
725 DRM_FORMAT_ABGR4444,
726 DRM_FORMAT_ABGR1555,
727 DRM_FORMAT_BGRA5551,
728 DRM_FORMAT_XRGB1555,
729 DRM_FORMAT_RGBX5551,
730 DRM_FORMAT_XBGR1555,
731 DRM_FORMAT_BGRX5551,
732 DRM_FORMAT_BGR565,
733 DRM_FORMAT_BGRA8888,
734 DRM_FORMAT_RGBA8888,
735 DRM_FORMAT_XRGB8888,
736 DRM_FORMAT_XBGR8888,
737 /* planar formats */
738 DRM_FORMAT_UYVY,
739 DRM_FORMAT_YUYV,
740 DRM_FORMAT_YUV420,
741 DRM_FORMAT_YUV422,
742 };
743
744 static const u32 tegra124_overlay_formats[] = {
745 DRM_FORMAT_ARGB4444,
746 DRM_FORMAT_ARGB1555,
747 DRM_FORMAT_RGB565,
748 DRM_FORMAT_RGBA5551,
749 DRM_FORMAT_ABGR8888,
750 DRM_FORMAT_ARGB8888,
751 /* new on Tegra114 */
752 DRM_FORMAT_ABGR4444,
753 DRM_FORMAT_ABGR1555,
754 DRM_FORMAT_BGRA5551,
755 DRM_FORMAT_XRGB1555,
756 DRM_FORMAT_RGBX5551,
757 DRM_FORMAT_XBGR1555,
758 DRM_FORMAT_BGRX5551,
759 DRM_FORMAT_BGR565,
760 DRM_FORMAT_BGRA8888,
761 DRM_FORMAT_RGBA8888,
762 DRM_FORMAT_XRGB8888,
763 DRM_FORMAT_XBGR8888,
764 /* new on Tegra124 */
765 DRM_FORMAT_RGBX8888,
766 DRM_FORMAT_BGRX8888,
767 /* planar formats */
768 DRM_FORMAT_UYVY,
769 DRM_FORMAT_YUYV,
770 DRM_FORMAT_YUV420,
771 DRM_FORMAT_YUV422,
772 };
773
774 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm,
775 struct tegra_dc *dc,
776 unsigned int index)
777 {
778 struct tegra_plane *plane;
779 unsigned int num_formats;
780 const u32 *formats;
781 int err;
782
783 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
784 if (!plane)
785 return ERR_PTR(-ENOMEM);
786
787 plane->offset = 0xa00 + 0x200 * index;
788 plane->index = index;
789 plane->depth = 0;
790 plane->dc = dc;
791
792 num_formats = dc->soc->num_overlay_formats;
793 formats = dc->soc->overlay_formats;
794
795 err = drm_universal_plane_init(drm, &plane->base, 1 << dc->pipe,
796 &tegra_plane_funcs, formats,
797 num_formats, NULL,
798 DRM_PLANE_TYPE_OVERLAY, NULL);
799 if (err < 0) {
800 kfree(plane);
801 return ERR_PTR(err);
802 }
803
804 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs);
805
806 return &plane->base;
807 }
808
809 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm,
810 struct tegra_dc *dc)
811 {
812 struct drm_plane *plane, *primary = NULL;
813 unsigned int i, j;
814
815 for (i = 0; i < dc->soc->num_wgrps; i++) {
816 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i];
817
818 if (wgrp->dc == dc->pipe) {
819 for (j = 0; j < wgrp->num_windows; j++) {
820 unsigned int index = wgrp->windows[j];
821
822 plane = tegra_shared_plane_create(drm, dc,
823 wgrp->index,
824 index);
825 if (IS_ERR(plane))
826 return plane;
827
828 /*
829 * Choose the first shared plane owned by this
830 * head as the primary plane.
831 */
832 if (!primary) {
833 plane->type = DRM_PLANE_TYPE_PRIMARY;
834 primary = plane;
835 }
836 }
837 }
838 }
839
840 return primary;
841 }
842
843 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm,
844 struct tegra_dc *dc)
845 {
846 struct drm_plane *plane, *primary;
847 unsigned int i;
848
849 primary = tegra_primary_plane_create(drm, dc);
850 if (IS_ERR(primary))
851 return primary;
852
853 for (i = 0; i < 2; i++) {
854 plane = tegra_dc_overlay_plane_create(drm, dc, 1 + i);
855 if (IS_ERR(plane)) {
856 /* XXX tegra_plane_destroy() */
857 drm_plane_cleanup(primary);
858 kfree(primary);
859 return plane;
860 }
861 }
862
863 return primary;
864 }
865
866 static void tegra_dc_destroy(struct drm_crtc *crtc)
867 {
868 drm_crtc_cleanup(crtc);
869 }
870
871 static void tegra_crtc_reset(struct drm_crtc *crtc)
872 {
873 struct tegra_dc_state *state;
874
875 if (crtc->state)
876 __drm_atomic_helper_crtc_destroy_state(crtc->state);
877
878 kfree(crtc->state);
879 crtc->state = NULL;
880
881 state = kzalloc(sizeof(*state), GFP_KERNEL);
882 if (state) {
883 crtc->state = &state->base;
884 crtc->state->crtc = crtc;
885 }
886
887 drm_crtc_vblank_reset(crtc);
888 }
889
890 static struct drm_crtc_state *
891 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
892 {
893 struct tegra_dc_state *state = to_dc_state(crtc->state);
894 struct tegra_dc_state *copy;
895
896 copy = kmalloc(sizeof(*copy), GFP_KERNEL);
897 if (!copy)
898 return NULL;
899
900 __drm_atomic_helper_crtc_duplicate_state(crtc, &copy->base);
901 copy->clk = state->clk;
902 copy->pclk = state->pclk;
903 copy->div = state->div;
904 copy->planes = state->planes;
905
906 return &copy->base;
907 }
908
909 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc,
910 struct drm_crtc_state *state)
911 {
912 __drm_atomic_helper_crtc_destroy_state(state);
913 kfree(state);
914 }
915
916 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
917
918 static const struct debugfs_reg32 tegra_dc_regs[] = {
919 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT),
920 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL),
921 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR),
922 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT),
923 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL),
924 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR),
925 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT),
926 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL),
927 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR),
928 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT),
929 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL),
930 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR),
931 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC),
932 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0),
933 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND),
934 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE),
935 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL),
936 DEBUGFS_REG32(DC_CMD_INT_STATUS),
937 DEBUGFS_REG32(DC_CMD_INT_MASK),
938 DEBUGFS_REG32(DC_CMD_INT_ENABLE),
939 DEBUGFS_REG32(DC_CMD_INT_TYPE),
940 DEBUGFS_REG32(DC_CMD_INT_POLARITY),
941 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1),
942 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2),
943 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3),
944 DEBUGFS_REG32(DC_CMD_STATE_ACCESS),
945 DEBUGFS_REG32(DC_CMD_STATE_CONTROL),
946 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER),
947 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL),
948 DEBUGFS_REG32(DC_COM_CRC_CONTROL),
949 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM),
950 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)),
951 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)),
952 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)),
953 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)),
954 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)),
955 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)),
956 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)),
957 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)),
958 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)),
959 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)),
960 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)),
961 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)),
962 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)),
963 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)),
964 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)),
965 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)),
966 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)),
967 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)),
968 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)),
969 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)),
970 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)),
971 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)),
972 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)),
973 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)),
974 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)),
975 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL),
976 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL),
977 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE),
978 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL),
979 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE),
980 DEBUGFS_REG32(DC_COM_SPI_CONTROL),
981 DEBUGFS_REG32(DC_COM_SPI_START_BYTE),
982 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB),
983 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD),
984 DEBUGFS_REG32(DC_COM_HSPI_CS_DC),
985 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A),
986 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B),
987 DEBUGFS_REG32(DC_COM_GPIO_CTRL),
988 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER),
989 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED),
990 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0),
991 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1),
992 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS),
993 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY),
994 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER),
995 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS),
996 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC),
997 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH),
998 DEBUGFS_REG32(DC_DISP_BACK_PORCH),
999 DEBUGFS_REG32(DC_DISP_ACTIVE),
1000 DEBUGFS_REG32(DC_DISP_FRONT_PORCH),
1001 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL),
1002 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A),
1003 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B),
1004 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C),
1005 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D),
1006 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL),
1007 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A),
1008 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B),
1009 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C),
1010 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D),
1011 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL),
1012 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A),
1013 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B),
1014 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C),
1015 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D),
1016 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL),
1017 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A),
1018 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B),
1019 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C),
1020 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL),
1021 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A),
1022 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B),
1023 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C),
1024 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL),
1025 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A),
1026 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL),
1027 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A),
1028 DEBUGFS_REG32(DC_DISP_M0_CONTROL),
1029 DEBUGFS_REG32(DC_DISP_M1_CONTROL),
1030 DEBUGFS_REG32(DC_DISP_DI_CONTROL),
1031 DEBUGFS_REG32(DC_DISP_PP_CONTROL),
1032 DEBUGFS_REG32(DC_DISP_PP_SELECT_A),
1033 DEBUGFS_REG32(DC_DISP_PP_SELECT_B),
1034 DEBUGFS_REG32(DC_DISP_PP_SELECT_C),
1035 DEBUGFS_REG32(DC_DISP_PP_SELECT_D),
1036 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL),
1037 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL),
1038 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL),
1039 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS),
1040 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS),
1041 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS),
1042 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS),
1043 DEBUGFS_REG32(DC_DISP_BORDER_COLOR),
1044 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER),
1045 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER),
1046 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER),
1047 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER),
1048 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND),
1049 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND),
1050 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR),
1051 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS),
1052 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION),
1053 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS),
1054 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL),
1055 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A),
1056 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B),
1057 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C),
1058 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D),
1059 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL),
1060 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST),
1061 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST),
1062 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST),
1063 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST),
1064 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL),
1065 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL),
1066 DEBUGFS_REG32(DC_DISP_SD_CONTROL),
1067 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF),
1068 DEBUGFS_REG32(DC_DISP_SD_LUT(0)),
1069 DEBUGFS_REG32(DC_DISP_SD_LUT(1)),
1070 DEBUGFS_REG32(DC_DISP_SD_LUT(2)),
1071 DEBUGFS_REG32(DC_DISP_SD_LUT(3)),
1072 DEBUGFS_REG32(DC_DISP_SD_LUT(4)),
1073 DEBUGFS_REG32(DC_DISP_SD_LUT(5)),
1074 DEBUGFS_REG32(DC_DISP_SD_LUT(6)),
1075 DEBUGFS_REG32(DC_DISP_SD_LUT(7)),
1076 DEBUGFS_REG32(DC_DISP_SD_LUT(8)),
1077 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL),
1078 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT),
1079 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)),
1080 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)),
1081 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)),
1082 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)),
1083 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)),
1084 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)),
1085 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)),
1086 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)),
1087 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)),
1088 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)),
1089 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)),
1090 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)),
1091 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL),
1092 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES),
1093 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES),
1094 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI),
1095 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL),
1096 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS),
1097 DEBUGFS_REG32(DC_WIN_BYTE_SWAP),
1098 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL),
1099 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH),
1100 DEBUGFS_REG32(DC_WIN_POSITION),
1101 DEBUGFS_REG32(DC_WIN_SIZE),
1102 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE),
1103 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA),
1104 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA),
1105 DEBUGFS_REG32(DC_WIN_DDA_INC),
1106 DEBUGFS_REG32(DC_WIN_LINE_STRIDE),
1107 DEBUGFS_REG32(DC_WIN_BUF_STRIDE),
1108 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE),
1109 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE),
1110 DEBUGFS_REG32(DC_WIN_DV_CONTROL),
1111 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY),
1112 DEBUGFS_REG32(DC_WIN_BLEND_1WIN),
1113 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X),
1114 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y),
1115 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY),
1116 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL),
1117 DEBUGFS_REG32(DC_WINBUF_START_ADDR),
1118 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS),
1119 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U),
1120 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS),
1121 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V),
1122 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS),
1123 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET),
1124 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS),
1125 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET),
1126 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS),
1127 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS),
1128 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS),
1129 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS),
1130 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS),
1131 };
1132
1133 static int tegra_dc_show_regs(struct seq_file *s, void *data)
1134 {
1135 struct drm_info_node *node = s->private;
1136 struct tegra_dc *dc = node->info_ent->data;
1137 unsigned int i;
1138 int err = 0;
1139
1140 drm_modeset_lock(&dc->base.mutex, NULL);
1141
1142 if (!dc->base.state->active) {
1143 err = -EBUSY;
1144 goto unlock;
1145 }
1146
1147 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) {
1148 unsigned int offset = tegra_dc_regs[i].offset;
1149
1150 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name,
1151 offset, tegra_dc_readl(dc, offset));
1152 }
1153
1154 unlock:
1155 drm_modeset_unlock(&dc->base.mutex);
1156 return err;
1157 }
1158
1159 static int tegra_dc_show_crc(struct seq_file *s, void *data)
1160 {
1161 struct drm_info_node *node = s->private;
1162 struct tegra_dc *dc = node->info_ent->data;
1163 int err = 0;
1164 u32 value;
1165
1166 drm_modeset_lock(&dc->base.mutex, NULL);
1167
1168 if (!dc->base.state->active) {
1169 err = -EBUSY;
1170 goto unlock;
1171 }
1172
1173 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE;
1174 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL);
1175 tegra_dc_commit(dc);
1176
1177 drm_crtc_wait_one_vblank(&dc->base);
1178 drm_crtc_wait_one_vblank(&dc->base);
1179
1180 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM);
1181 seq_printf(s, "%08x\n", value);
1182
1183 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL);
1184
1185 unlock:
1186 drm_modeset_unlock(&dc->base.mutex);
1187 return err;
1188 }
1189
1190 static int tegra_dc_show_stats(struct seq_file *s, void *data)
1191 {
1192 struct drm_info_node *node = s->private;
1193 struct tegra_dc *dc = node->info_ent->data;
1194
1195 seq_printf(s, "frames: %lu\n", dc->stats.frames);
1196 seq_printf(s, "vblank: %lu\n", dc->stats.vblank);
1197 seq_printf(s, "underflow: %lu\n", dc->stats.underflow);
1198 seq_printf(s, "overflow: %lu\n", dc->stats.overflow);
1199
1200 return 0;
1201 }
1202
1203 static struct drm_info_list debugfs_files[] = {
1204 { "regs", tegra_dc_show_regs, 0, NULL },
1205 { "crc", tegra_dc_show_crc, 0, NULL },
1206 { "stats", tegra_dc_show_stats, 0, NULL },
1207 };
1208
1209 static int tegra_dc_late_register(struct drm_crtc *crtc)
1210 {
1211 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1212 struct drm_minor *minor = crtc->dev->primary;
1213 struct dentry *root = crtc->debugfs_entry;
1214 struct tegra_dc *dc = to_tegra_dc(crtc);
1215 int err;
1216
1217 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1218 GFP_KERNEL);
1219 if (!dc->debugfs_files)
1220 return -ENOMEM;
1221
1222 for (i = 0; i < count; i++)
1223 dc->debugfs_files[i].data = dc;
1224
1225 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor);
1226 if (err < 0)
1227 goto free;
1228
1229 return 0;
1230
1231 free:
1232 kfree(dc->debugfs_files);
1233 dc->debugfs_files = NULL;
1234
1235 return err;
1236 }
1237
1238 static void tegra_dc_early_unregister(struct drm_crtc *crtc)
1239 {
1240 unsigned int count = ARRAY_SIZE(debugfs_files);
1241 struct drm_minor *minor = crtc->dev->primary;
1242 struct tegra_dc *dc = to_tegra_dc(crtc);
1243
1244 drm_debugfs_remove_files(dc->debugfs_files, count, minor);
1245 kfree(dc->debugfs_files);
1246 dc->debugfs_files = NULL;
1247 }
1248
1249 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc)
1250 {
1251 struct tegra_dc *dc = to_tegra_dc(crtc);
1252
1253 /* XXX vblank syncpoints don't work with nvdisplay yet */
1254 if (dc->syncpt && !dc->soc->has_nvdisplay)
1255 return host1x_syncpt_read(dc->syncpt);
1256
1257 /* fallback to software emulated VBLANK counter */
1258 return drm_crtc_vblank_count(&dc->base);
1259 }
1260
1261 static int tegra_dc_enable_vblank(struct drm_crtc *crtc)
1262 {
1263 struct tegra_dc *dc = to_tegra_dc(crtc);
1264 unsigned long value, flags;
1265
1266 spin_lock_irqsave(&dc->lock, flags);
1267
1268 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1269 value |= VBLANK_INT;
1270 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1271
1272 spin_unlock_irqrestore(&dc->lock, flags);
1273
1274 return 0;
1275 }
1276
1277 static void tegra_dc_disable_vblank(struct drm_crtc *crtc)
1278 {
1279 struct tegra_dc *dc = to_tegra_dc(crtc);
1280 unsigned long value, flags;
1281
1282 spin_lock_irqsave(&dc->lock, flags);
1283
1284 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1285 value &= ~VBLANK_INT;
1286 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1287
1288 spin_unlock_irqrestore(&dc->lock, flags);
1289 }
1290
1291 static const struct drm_crtc_funcs tegra_crtc_funcs = {
1292 .page_flip = drm_atomic_helper_page_flip,
1293 .set_config = drm_atomic_helper_set_config,
1294 .destroy = tegra_dc_destroy,
1295 .reset = tegra_crtc_reset,
1296 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state,
1297 .atomic_destroy_state = tegra_crtc_atomic_destroy_state,
1298 .late_register = tegra_dc_late_register,
1299 .early_unregister = tegra_dc_early_unregister,
1300 .get_vblank_counter = tegra_dc_get_vblank_counter,
1301 .enable_vblank = tegra_dc_enable_vblank,
1302 .disable_vblank = tegra_dc_disable_vblank,
1303 };
1304
1305 static int tegra_dc_set_timings(struct tegra_dc *dc,
1306 struct drm_display_mode *mode)
1307 {
1308 unsigned int h_ref_to_sync = 1;
1309 unsigned int v_ref_to_sync = 1;
1310 unsigned long value;
1311
1312 if (!dc->soc->has_nvdisplay) {
1313 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1314
1315 value = (v_ref_to_sync << 16) | h_ref_to_sync;
1316 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
1317 }
1318
1319 value = ((mode->vsync_end - mode->vsync_start) << 16) |
1320 ((mode->hsync_end - mode->hsync_start) << 0);
1321 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
1322
1323 value = ((mode->vtotal - mode->vsync_end) << 16) |
1324 ((mode->htotal - mode->hsync_end) << 0);
1325 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
1326
1327 value = ((mode->vsync_start - mode->vdisplay) << 16) |
1328 ((mode->hsync_start - mode->hdisplay) << 0);
1329 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
1330
1331 value = (mode->vdisplay << 16) | mode->hdisplay;
1332 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
1333
1334 return 0;
1335 }
1336
1337 /**
1338 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1339 * state
1340 * @dc: display controller
1341 * @crtc_state: CRTC atomic state
1342 * @clk: parent clock for display controller
1343 * @pclk: pixel clock
1344 * @div: shift clock divider
1345 *
1346 * Returns:
1347 * 0 on success or a negative error-code on failure.
1348 */
1349 int tegra_dc_state_setup_clock(struct tegra_dc *dc,
1350 struct drm_crtc_state *crtc_state,
1351 struct clk *clk, unsigned long pclk,
1352 unsigned int div)
1353 {
1354 struct tegra_dc_state *state = to_dc_state(crtc_state);
1355
1356 if (!clk_has_parent(dc->clk, clk))
1357 return -EINVAL;
1358
1359 state->clk = clk;
1360 state->pclk = pclk;
1361 state->div = div;
1362
1363 return 0;
1364 }
1365
1366 static void tegra_dc_commit_state(struct tegra_dc *dc,
1367 struct tegra_dc_state *state)
1368 {
1369 u32 value;
1370 int err;
1371
1372 err = clk_set_parent(dc->clk, state->clk);
1373 if (err < 0)
1374 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
1375
1376 /*
1377 * Outputs may not want to change the parent clock rate. This is only
1378 * relevant to Tegra20 where only a single display PLL is available.
1379 * Since that PLL would typically be used for HDMI, an internal LVDS
1380 * panel would need to be driven by some other clock such as PLL_P
1381 * which is shared with other peripherals. Changing the clock rate
1382 * should therefore be avoided.
1383 */
1384 if (state->pclk > 0) {
1385 err = clk_set_rate(state->clk, state->pclk);
1386 if (err < 0)
1387 dev_err(dc->dev,
1388 "failed to set clock rate to %lu Hz\n",
1389 state->pclk);
1390 }
1391
1392 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk),
1393 state->div);
1394 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk);
1395
1396 if (!dc->soc->has_nvdisplay) {
1397 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
1398 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
1399 }
1400
1401 err = clk_set_rate(dc->clk, state->pclk);
1402 if (err < 0)
1403 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n",
1404 dc->clk, state->pclk, err);
1405 }
1406
1407 static void tegra_dc_stop(struct tegra_dc *dc)
1408 {
1409 u32 value;
1410
1411 /* stop the display controller */
1412 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1413 value &= ~DISP_CTRL_MODE_MASK;
1414 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1415
1416 tegra_dc_commit(dc);
1417 }
1418
1419 static bool tegra_dc_idle(struct tegra_dc *dc)
1420 {
1421 u32 value;
1422
1423 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND);
1424
1425 return (value & DISP_CTRL_MODE_MASK) == 0;
1426 }
1427
1428 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout)
1429 {
1430 timeout = jiffies + msecs_to_jiffies(timeout);
1431
1432 while (time_before(jiffies, timeout)) {
1433 if (tegra_dc_idle(dc))
1434 return 0;
1435
1436 usleep_range(1000, 2000);
1437 }
1438
1439 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n");
1440 return -ETIMEDOUT;
1441 }
1442
1443 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
1444 struct drm_crtc_state *old_state)
1445 {
1446 struct tegra_dc *dc = to_tegra_dc(crtc);
1447 u32 value;
1448
1449 if (!tegra_dc_idle(dc)) {
1450 tegra_dc_stop(dc);
1451
1452 /*
1453 * Ignore the return value, there isn't anything useful to do
1454 * in case this fails.
1455 */
1456 tegra_dc_wait_idle(dc, 100);
1457 }
1458
1459 /*
1460 * This should really be part of the RGB encoder driver, but clearing
1461 * these bits has the side-effect of stopping the display controller.
1462 * When that happens no VBLANK interrupts will be raised. At the same
1463 * time the encoder is disabled before the display controller, so the
1464 * above code is always going to timeout waiting for the controller
1465 * to go idle.
1466 *
1467 * Given the close coupling between the RGB encoder and the display
1468 * controller doing it here is still kind of okay. None of the other
1469 * encoder drivers require these bits to be cleared.
1470 *
1471 * XXX: Perhaps given that the display controller is switched off at
1472 * this point anyway maybe clearing these bits isn't even useful for
1473 * the RGB encoder?
1474 */
1475 if (dc->rgb) {
1476 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1477 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1478 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1479 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1480 }
1481
1482 tegra_dc_stats_reset(&dc->stats);
1483 drm_crtc_vblank_off(crtc);
1484
1485 spin_lock_irq(&crtc->dev->event_lock);
1486
1487 if (crtc->state->event) {
1488 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1489 crtc->state->event = NULL;
1490 }
1491
1492 spin_unlock_irq(&crtc->dev->event_lock);
1493
1494 pm_runtime_put_sync(dc->dev);
1495 }
1496
1497 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
1498 struct drm_crtc_state *old_state)
1499 {
1500 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1501 struct tegra_dc_state *state = to_dc_state(crtc->state);
1502 struct tegra_dc *dc = to_tegra_dc(crtc);
1503 u32 value;
1504
1505 pm_runtime_get_sync(dc->dev);
1506
1507 /* initialize display controller */
1508 if (dc->syncpt) {
1509 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable;
1510
1511 if (dc->soc->has_nvdisplay)
1512 enable = 1 << 31;
1513 else
1514 enable = 1 << 8;
1515
1516 value = SYNCPT_CNTRL_NO_STALL;
1517 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1518
1519 value = enable | syncpt;
1520 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC);
1521 }
1522
1523 if (dc->soc->has_nvdisplay) {
1524 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1525 DSC_OBUF_UF_INT;
1526 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1527
1528 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT |
1529 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT |
1530 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT |
1531 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT |
1532 VBLANK_INT | FRAME_END_INT;
1533 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1534
1535 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT |
1536 FRAME_END_INT;
1537 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1538
1539 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT;
1540 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1541
1542 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
1543 } else {
1544 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1545 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1546 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1547
1548 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1549 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1550 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1551
1552 /* initialize timer */
1553 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1554 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1555 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1556
1557 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1558 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1559 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1560
1561 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1562 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1563 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1564
1565 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1566 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1567 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1568 }
1569
1570 if (dc->soc->supports_background_color)
1571 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR);
1572 else
1573 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1574
1575 /* apply PLL and pixel clock changes */
1576 tegra_dc_commit_state(dc, state);
1577
1578 /* program display mode */
1579 tegra_dc_set_timings(dc, mode);
1580
1581 /* interlacing isn't supported yet, so disable it */
1582 if (dc->soc->supports_interlacing) {
1583 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
1584 value &= ~INTERLACE_ENABLE;
1585 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
1586 }
1587
1588 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1589 value &= ~DISP_CTRL_MODE_MASK;
1590 value |= DISP_CTRL_MODE_C_DISPLAY;
1591 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1592
1593 if (!dc->soc->has_nvdisplay) {
1594 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1595 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1596 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
1597 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1598 }
1599
1600 /* enable underflow reporting and display red for missing pixels */
1601 if (dc->soc->has_nvdisplay) {
1602 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE;
1603 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW);
1604 }
1605
1606 tegra_dc_commit(dc);
1607
1608 drm_crtc_vblank_on(crtc);
1609 }
1610
1611 static int tegra_crtc_atomic_check(struct drm_crtc *crtc,
1612 struct drm_crtc_state *state)
1613 {
1614 struct tegra_atomic_state *s = to_tegra_atomic_state(state->state);
1615 struct tegra_dc_state *tegra = to_dc_state(state);
1616
1617 /*
1618 * The display hub display clock needs to be fed by the display clock
1619 * with the highest frequency to ensure proper functioning of all the
1620 * displays.
1621 *
1622 * Note that this isn't used before Tegra186, but it doesn't hurt and
1623 * conditionalizing it would make the code less clean.
1624 */
1625 if (state->active) {
1626 if (!s->clk_disp || tegra->pclk > s->rate) {
1627 s->dc = to_tegra_dc(crtc);
1628 s->clk_disp = s->dc->clk;
1629 s->rate = tegra->pclk;
1630 }
1631 }
1632
1633 return 0;
1634 }
1635
1636 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc,
1637 struct drm_crtc_state *old_crtc_state)
1638 {
1639 unsigned long flags;
1640
1641 if (crtc->state->event) {
1642 spin_lock_irqsave(&crtc->dev->event_lock, flags);
1643
1644 if (drm_crtc_vblank_get(crtc) != 0)
1645 drm_crtc_send_vblank_event(crtc, crtc->state->event);
1646 else
1647 drm_crtc_arm_vblank_event(crtc, crtc->state->event);
1648
1649 spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1650
1651 crtc->state->event = NULL;
1652 }
1653 }
1654
1655 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc,
1656 struct drm_crtc_state *old_crtc_state)
1657 {
1658 struct tegra_dc_state *state = to_dc_state(crtc->state);
1659 struct tegra_dc *dc = to_tegra_dc(crtc);
1660 u32 value;
1661
1662 value = state->planes << 8 | GENERAL_UPDATE;
1663 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1664 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1665
1666 value = state->planes | GENERAL_ACT_REQ;
1667 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
1668 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1669 }
1670
1671 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
1672 .atomic_check = tegra_crtc_atomic_check,
1673 .atomic_begin = tegra_crtc_atomic_begin,
1674 .atomic_flush = tegra_crtc_atomic_flush,
1675 .atomic_enable = tegra_crtc_atomic_enable,
1676 .atomic_disable = tegra_crtc_atomic_disable,
1677 };
1678
1679 static irqreturn_t tegra_dc_irq(int irq, void *data)
1680 {
1681 struct tegra_dc *dc = data;
1682 unsigned long status;
1683
1684 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1685 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1686
1687 if (status & FRAME_END_INT) {
1688 /*
1689 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
1690 */
1691 dc->stats.frames++;
1692 }
1693
1694 if (status & VBLANK_INT) {
1695 /*
1696 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
1697 */
1698 drm_crtc_handle_vblank(&dc->base);
1699 dc->stats.vblank++;
1700 }
1701
1702 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
1703 /*
1704 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
1705 */
1706 dc->stats.underflow++;
1707 }
1708
1709 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) {
1710 /*
1711 dev_dbg(dc->dev, "%s(): overflow\n", __func__);
1712 */
1713 dc->stats.overflow++;
1714 }
1715
1716 if (status & HEAD_UF_INT) {
1717 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__);
1718 dc->stats.underflow++;
1719 }
1720
1721 return IRQ_HANDLED;
1722 }
1723
1724 static int tegra_dc_init(struct host1x_client *client)
1725 {
1726 struct drm_device *drm = dev_get_drvdata(client->parent);
1727 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED;
1728 struct tegra_dc *dc = host1x_client_to_dc(client);
1729 struct tegra_drm *tegra = drm->dev_private;
1730 struct drm_plane *primary = NULL;
1731 struct drm_plane *cursor = NULL;
1732 int err;
1733
1734 dc->syncpt = host1x_syncpt_request(client, flags);
1735 if (!dc->syncpt)
1736 dev_warn(dc->dev, "failed to allocate syncpoint\n");
1737
1738 if (tegra->domain) {
1739 err = iommu_attach_device(tegra->domain, dc->dev);
1740 if (err < 0) {
1741 dev_err(dc->dev, "failed to attach to domain: %d\n",
1742 err);
1743 return err;
1744 }
1745
1746 dc->domain = tegra->domain;
1747 }
1748
1749 if (dc->soc->wgrps)
1750 primary = tegra_dc_add_shared_planes(drm, dc);
1751 else
1752 primary = tegra_dc_add_planes(drm, dc);
1753
1754 if (IS_ERR(primary)) {
1755 err = PTR_ERR(primary);
1756 goto cleanup;
1757 }
1758
1759 if (dc->soc->supports_cursor) {
1760 cursor = tegra_dc_cursor_plane_create(drm, dc);
1761 if (IS_ERR(cursor)) {
1762 err = PTR_ERR(cursor);
1763 goto cleanup;
1764 }
1765 }
1766
1767 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor,
1768 &tegra_crtc_funcs, NULL);
1769 if (err < 0)
1770 goto cleanup;
1771
1772 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1773
1774 /*
1775 * Keep track of the minimum pitch alignment across all display
1776 * controllers.
1777 */
1778 if (dc->soc->pitch_align > tegra->pitch_align)
1779 tegra->pitch_align = dc->soc->pitch_align;
1780
1781 err = tegra_dc_rgb_init(drm, dc);
1782 if (err < 0 && err != -ENODEV) {
1783 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1784 goto cleanup;
1785 }
1786
1787 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1788 dev_name(dc->dev), dc);
1789 if (err < 0) {
1790 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1791 err);
1792 goto cleanup;
1793 }
1794
1795 return 0;
1796
1797 cleanup:
1798 if (!IS_ERR_OR_NULL(cursor))
1799 drm_plane_cleanup(cursor);
1800
1801 if (!IS_ERR(primary))
1802 drm_plane_cleanup(primary);
1803
1804 if (tegra->domain) {
1805 iommu_detach_device(tegra->domain, dc->dev);
1806 dc->domain = NULL;
1807 }
1808
1809 return err;
1810 }
1811
1812 static int tegra_dc_exit(struct host1x_client *client)
1813 {
1814 struct tegra_dc *dc = host1x_client_to_dc(client);
1815 int err;
1816
1817 devm_free_irq(dc->dev, dc->irq, dc);
1818
1819 err = tegra_dc_rgb_exit(dc);
1820 if (err) {
1821 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1822 return err;
1823 }
1824
1825 if (dc->domain) {
1826 iommu_detach_device(dc->domain, dc->dev);
1827 dc->domain = NULL;
1828 }
1829
1830 host1x_syncpt_free(dc->syncpt);
1831
1832 return 0;
1833 }
1834
1835 static const struct host1x_client_ops dc_client_ops = {
1836 .init = tegra_dc_init,
1837 .exit = tegra_dc_exit,
1838 };
1839
1840 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1841 .supports_background_color = false,
1842 .supports_interlacing = false,
1843 .supports_cursor = false,
1844 .supports_block_linear = false,
1845 .pitch_align = 8,
1846 .has_powergate = false,
1847 .broken_reset = true,
1848 .has_nvdisplay = false,
1849 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1850 .primary_formats = tegra20_primary_formats,
1851 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1852 .overlay_formats = tegra20_overlay_formats,
1853 };
1854
1855 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1856 .supports_background_color = false,
1857 .supports_interlacing = false,
1858 .supports_cursor = false,
1859 .supports_block_linear = false,
1860 .pitch_align = 8,
1861 .has_powergate = false,
1862 .broken_reset = false,
1863 .has_nvdisplay = false,
1864 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats),
1865 .primary_formats = tegra20_primary_formats,
1866 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats),
1867 .overlay_formats = tegra20_overlay_formats,
1868 };
1869
1870 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1871 .supports_background_color = false,
1872 .supports_interlacing = false,
1873 .supports_cursor = false,
1874 .supports_block_linear = false,
1875 .pitch_align = 64,
1876 .has_powergate = true,
1877 .broken_reset = false,
1878 .has_nvdisplay = false,
1879 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1880 .primary_formats = tegra114_primary_formats,
1881 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1882 .overlay_formats = tegra114_overlay_formats,
1883 };
1884
1885 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1886 .supports_background_color = true,
1887 .supports_interlacing = true,
1888 .supports_cursor = true,
1889 .supports_block_linear = true,
1890 .pitch_align = 64,
1891 .has_powergate = true,
1892 .broken_reset = false,
1893 .has_nvdisplay = false,
1894 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats),
1895 .primary_formats = tegra114_primary_formats,
1896 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats),
1897 .overlay_formats = tegra114_overlay_formats,
1898 };
1899
1900 static const struct tegra_dc_soc_info tegra210_dc_soc_info = {
1901 .supports_background_color = true,
1902 .supports_interlacing = true,
1903 .supports_cursor = true,
1904 .supports_block_linear = true,
1905 .pitch_align = 64,
1906 .has_powergate = true,
1907 .broken_reset = false,
1908 .has_nvdisplay = false,
1909 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats),
1910 .primary_formats = tegra114_primary_formats,
1911 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats),
1912 .overlay_formats = tegra114_overlay_formats,
1913 };
1914
1915 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = {
1916 {
1917 .index = 0,
1918 .dc = 0,
1919 .windows = (const unsigned int[]) { 0 },
1920 .num_windows = 1,
1921 }, {
1922 .index = 1,
1923 .dc = 1,
1924 .windows = (const unsigned int[]) { 1 },
1925 .num_windows = 1,
1926 }, {
1927 .index = 2,
1928 .dc = 1,
1929 .windows = (const unsigned int[]) { 2 },
1930 .num_windows = 1,
1931 }, {
1932 .index = 3,
1933 .dc = 2,
1934 .windows = (const unsigned int[]) { 3 },
1935 .num_windows = 1,
1936 }, {
1937 .index = 4,
1938 .dc = 2,
1939 .windows = (const unsigned int[]) { 4 },
1940 .num_windows = 1,
1941 }, {
1942 .index = 5,
1943 .dc = 2,
1944 .windows = (const unsigned int[]) { 5 },
1945 .num_windows = 1,
1946 },
1947 };
1948
1949 static const struct tegra_dc_soc_info tegra186_dc_soc_info = {
1950 .supports_background_color = true,
1951 .supports_interlacing = true,
1952 .supports_cursor = true,
1953 .supports_block_linear = true,
1954 .pitch_align = 64,
1955 .has_powergate = false,
1956 .broken_reset = false,
1957 .has_nvdisplay = true,
1958 .wgrps = tegra186_dc_wgrps,
1959 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps),
1960 };
1961
1962 static const struct of_device_id tegra_dc_of_match[] = {
1963 {
1964 .compatible = "nvidia,tegra186-dc",
1965 .data = &tegra186_dc_soc_info,
1966 }, {
1967 .compatible = "nvidia,tegra210-dc",
1968 .data = &tegra210_dc_soc_info,
1969 }, {
1970 .compatible = "nvidia,tegra124-dc",
1971 .data = &tegra124_dc_soc_info,
1972 }, {
1973 .compatible = "nvidia,tegra114-dc",
1974 .data = &tegra114_dc_soc_info,
1975 }, {
1976 .compatible = "nvidia,tegra30-dc",
1977 .data = &tegra30_dc_soc_info,
1978 }, {
1979 .compatible = "nvidia,tegra20-dc",
1980 .data = &tegra20_dc_soc_info,
1981 }, {
1982 /* sentinel */
1983 }
1984 };
1985 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1986
1987 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1988 {
1989 struct device_node *np;
1990 u32 value = 0;
1991 int err;
1992
1993 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1994 if (err < 0) {
1995 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1996
1997 /*
1998 * If the nvidia,head property isn't present, try to find the
1999 * correct head number by looking up the position of this
2000 * display controller's node within the device tree. Assuming
2001 * that the nodes are ordered properly in the DTS file and
2002 * that the translation into a flattened device tree blob
2003 * preserves that ordering this will actually yield the right
2004 * head number.
2005 *
2006 * If those assumptions don't hold, this will still work for
2007 * cases where only a single display controller is used.
2008 */
2009 for_each_matching_node(np, tegra_dc_of_match) {
2010 if (np == dc->dev->of_node) {
2011 of_node_put(np);
2012 break;
2013 }
2014
2015 value++;
2016 }
2017 }
2018
2019 dc->pipe = value;
2020
2021 return 0;
2022 }
2023
2024 static int tegra_dc_probe(struct platform_device *pdev)
2025 {
2026 struct resource *regs;
2027 struct tegra_dc *dc;
2028 int err;
2029
2030 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
2031 if (!dc)
2032 return -ENOMEM;
2033
2034 dc->soc = of_device_get_match_data(&pdev->dev);
2035
2036 spin_lock_init(&dc->lock);
2037 INIT_LIST_HEAD(&dc->list);
2038 dc->dev = &pdev->dev;
2039
2040 err = tegra_dc_parse_dt(dc);
2041 if (err < 0)
2042 return err;
2043
2044 dc->clk = devm_clk_get(&pdev->dev, NULL);
2045 if (IS_ERR(dc->clk)) {
2046 dev_err(&pdev->dev, "failed to get clock\n");
2047 return PTR_ERR(dc->clk);
2048 }
2049
2050 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
2051 if (IS_ERR(dc->rst)) {
2052 dev_err(&pdev->dev, "failed to get reset\n");
2053 return PTR_ERR(dc->rst);
2054 }
2055
2056 /* assert reset and disable clock */
2057 if (!dc->soc->broken_reset) {
2058 err = clk_prepare_enable(dc->clk);
2059 if (err < 0)
2060 return err;
2061
2062 usleep_range(2000, 4000);
2063
2064 err = reset_control_assert(dc->rst);
2065 if (err < 0)
2066 return err;
2067
2068 usleep_range(2000, 4000);
2069
2070 clk_disable_unprepare(dc->clk);
2071 }
2072
2073 if (dc->soc->has_powergate) {
2074 if (dc->pipe == 0)
2075 dc->powergate = TEGRA_POWERGATE_DIS;
2076 else
2077 dc->powergate = TEGRA_POWERGATE_DISB;
2078
2079 tegra_powergate_power_off(dc->powergate);
2080 }
2081
2082 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2083 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
2084 if (IS_ERR(dc->regs))
2085 return PTR_ERR(dc->regs);
2086
2087 dc->irq = platform_get_irq(pdev, 0);
2088 if (dc->irq < 0) {
2089 dev_err(&pdev->dev, "failed to get IRQ\n");
2090 return -ENXIO;
2091 }
2092
2093 err = tegra_dc_rgb_probe(dc);
2094 if (err < 0 && err != -ENODEV) {
2095 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
2096 return err;
2097 }
2098
2099 platform_set_drvdata(pdev, dc);
2100 pm_runtime_enable(&pdev->dev);
2101
2102 INIT_LIST_HEAD(&dc->client.list);
2103 dc->client.ops = &dc_client_ops;
2104 dc->client.dev = &pdev->dev;
2105
2106 err = host1x_client_register(&dc->client);
2107 if (err < 0) {
2108 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
2109 err);
2110 return err;
2111 }
2112
2113 return 0;
2114 }
2115
2116 static int tegra_dc_remove(struct platform_device *pdev)
2117 {
2118 struct tegra_dc *dc = platform_get_drvdata(pdev);
2119 int err;
2120
2121 err = host1x_client_unregister(&dc->client);
2122 if (err < 0) {
2123 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
2124 err);
2125 return err;
2126 }
2127
2128 err = tegra_dc_rgb_remove(dc);
2129 if (err < 0) {
2130 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
2131 return err;
2132 }
2133
2134 pm_runtime_disable(&pdev->dev);
2135
2136 return 0;
2137 }
2138
2139 #ifdef CONFIG_PM
2140 static int tegra_dc_suspend(struct device *dev)
2141 {
2142 struct tegra_dc *dc = dev_get_drvdata(dev);
2143 int err;
2144
2145 if (!dc->soc->broken_reset) {
2146 err = reset_control_assert(dc->rst);
2147 if (err < 0) {
2148 dev_err(dev, "failed to assert reset: %d\n", err);
2149 return err;
2150 }
2151 }
2152
2153 if (dc->soc->has_powergate)
2154 tegra_powergate_power_off(dc->powergate);
2155
2156 clk_disable_unprepare(dc->clk);
2157
2158 return 0;
2159 }
2160
2161 static int tegra_dc_resume(struct device *dev)
2162 {
2163 struct tegra_dc *dc = dev_get_drvdata(dev);
2164 int err;
2165
2166 if (dc->soc->has_powergate) {
2167 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk,
2168 dc->rst);
2169 if (err < 0) {
2170 dev_err(dev, "failed to power partition: %d\n", err);
2171 return err;
2172 }
2173 } else {
2174 err = clk_prepare_enable(dc->clk);
2175 if (err < 0) {
2176 dev_err(dev, "failed to enable clock: %d\n", err);
2177 return err;
2178 }
2179
2180 if (!dc->soc->broken_reset) {
2181 err = reset_control_deassert(dc->rst);
2182 if (err < 0) {
2183 dev_err(dev,
2184 "failed to deassert reset: %d\n", err);
2185 return err;
2186 }
2187 }
2188 }
2189
2190 return 0;
2191 }
2192 #endif
2193
2194 static const struct dev_pm_ops tegra_dc_pm_ops = {
2195 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL)
2196 };
2197
2198 struct platform_driver tegra_dc_driver = {
2199 .driver = {
2200 .name = "tegra-dc",
2201 .of_match_table = tegra_dc_of_match,
2202 .pm = &tegra_dc_pm_ops,
2203 },
2204 .probe = tegra_dc_probe,
2205 .remove = tegra_dc_remove,
2206 };
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