2 * Copyright (c) 2015, NVIDIA Corporation.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/host1x.h>
11 #include <linux/iommu.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/of_platform.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
20 #include <soc/tegra/pmc.h>
37 struct tegra_drm_client client
;
38 struct host1x_channel
*channel
;
39 struct iommu_domain
*domain
;
42 struct reset_control
*rst
;
44 /* Platform configuration */
45 const struct vic_config
*config
;
48 static inline struct vic
*to_vic(struct tegra_drm_client
*client
)
50 return container_of(client
, struct vic
, client
);
53 static void vic_writel(struct vic
*vic
, u32 value
, unsigned int offset
)
55 writel(value
, vic
->regs
+ offset
);
58 static int vic_runtime_resume(struct device
*dev
)
60 struct vic
*vic
= dev_get_drvdata(dev
);
63 err
= clk_prepare_enable(vic
->clk
);
69 err
= reset_control_deassert(vic
->rst
);
78 clk_disable_unprepare(vic
->clk
);
82 static int vic_runtime_suspend(struct device
*dev
)
84 struct vic
*vic
= dev_get_drvdata(dev
);
87 err
= reset_control_assert(vic
->rst
);
91 usleep_range(2000, 4000);
93 clk_disable_unprepare(vic
->clk
);
100 static int vic_boot(struct vic
*vic
)
102 u32 fce_ucode_size
, fce_bin_data_offset
;
109 #ifdef CONFIG_IOMMU_API
110 if (vic
->config
->supports_sid
) {
111 struct iommu_fwspec
*spec
= dev_iommu_fwspec_get(vic
->dev
);
114 value
= TRANSCFG_ATT(1, TRANSCFG_SID_FALCON
) |
115 TRANSCFG_ATT(0, TRANSCFG_SID_HW
);
116 vic_writel(vic
, value
, VIC_TFBIF_TRANSCFG
);
118 if (spec
&& spec
->num_ids
> 0) {
119 value
= spec
->ids
[0] & 0xffff;
121 vic_writel(vic
, value
, VIC_THI_STREAMID0
);
122 vic_writel(vic
, value
, VIC_THI_STREAMID1
);
127 /* setup clockgating registers */
128 vic_writel(vic
, CG_IDLE_CG_DLY_CNT(4) |
130 CG_WAKEUP_DLY_CNT(4),
131 NV_PVIC_MISC_PRI_VIC_CG
);
133 err
= falcon_boot(&vic
->falcon
);
137 hdr
= vic
->falcon
.firmware
.vaddr
;
138 fce_bin_data_offset
= *(u32
*)(hdr
+ VIC_UCODE_FCE_DATA_OFFSET
);
139 hdr
= vic
->falcon
.firmware
.vaddr
+
140 *(u32
*)(hdr
+ VIC_UCODE_FCE_HEADER_OFFSET
);
141 fce_ucode_size
= *(u32
*)(hdr
+ FCE_UCODE_SIZE_OFFSET
);
143 falcon_execute_method(&vic
->falcon
, VIC_SET_APPLICATION_ID
, 1);
144 falcon_execute_method(&vic
->falcon
, VIC_SET_FCE_UCODE_SIZE
,
146 falcon_execute_method(&vic
->falcon
, VIC_SET_FCE_UCODE_OFFSET
,
147 (vic
->falcon
.firmware
.paddr
+ fce_bin_data_offset
)
150 err
= falcon_wait_idle(&vic
->falcon
);
153 "failed to set application ID and FCE base\n");
162 static void *vic_falcon_alloc(struct falcon
*falcon
, size_t size
,
165 struct tegra_drm
*tegra
= falcon
->data
;
167 return tegra_drm_alloc(tegra
, size
, iova
);
170 static void vic_falcon_free(struct falcon
*falcon
, size_t size
,
171 dma_addr_t iova
, void *va
)
173 struct tegra_drm
*tegra
= falcon
->data
;
175 return tegra_drm_free(tegra
, size
, va
, iova
);
178 static const struct falcon_ops vic_falcon_ops
= {
179 .alloc
= vic_falcon_alloc
,
180 .free
= vic_falcon_free
183 static int vic_init(struct host1x_client
*client
)
185 struct tegra_drm_client
*drm
= host1x_to_drm_client(client
);
186 struct iommu_group
*group
= iommu_group_get(client
->dev
);
187 struct drm_device
*dev
= dev_get_drvdata(client
->parent
);
188 struct tegra_drm
*tegra
= dev
->dev_private
;
189 struct vic
*vic
= to_vic(drm
);
192 if (group
&& tegra
->domain
) {
193 err
= iommu_attach_group(tegra
->domain
, group
);
195 dev_err(vic
->dev
, "failed to attach to domain: %d\n",
200 vic
->domain
= tegra
->domain
;
203 vic
->channel
= host1x_channel_request(client
->dev
);
209 client
->syncpts
[0] = host1x_syncpt_request(client
, 0);
210 if (!client
->syncpts
[0]) {
215 err
= tegra_drm_register_client(tegra
, drm
);
222 host1x_syncpt_free(client
->syncpts
[0]);
224 host1x_channel_put(vic
->channel
);
226 if (group
&& tegra
->domain
)
227 iommu_detach_group(tegra
->domain
, group
);
232 static int vic_exit(struct host1x_client
*client
)
234 struct tegra_drm_client
*drm
= host1x_to_drm_client(client
);
235 struct iommu_group
*group
= iommu_group_get(client
->dev
);
236 struct drm_device
*dev
= dev_get_drvdata(client
->parent
);
237 struct tegra_drm
*tegra
= dev
->dev_private
;
238 struct vic
*vic
= to_vic(drm
);
241 err
= tegra_drm_unregister_client(tegra
, drm
);
245 host1x_syncpt_free(client
->syncpts
[0]);
246 host1x_channel_put(vic
->channel
);
249 iommu_detach_group(vic
->domain
, group
);
256 static const struct host1x_client_ops vic_client_ops
= {
261 static int vic_load_firmware(struct vic
*vic
)
265 if (vic
->falcon
.data
)
268 vic
->falcon
.data
= vic
->client
.drm
;
270 err
= falcon_read_firmware(&vic
->falcon
, vic
->config
->firmware
);
274 err
= falcon_load_firmware(&vic
->falcon
);
281 vic
->falcon
.data
= NULL
;
285 static int vic_open_channel(struct tegra_drm_client
*client
,
286 struct tegra_drm_context
*context
)
288 struct vic
*vic
= to_vic(client
);
291 err
= pm_runtime_get_sync(vic
->dev
);
295 err
= vic_load_firmware(vic
);
303 context
->channel
= host1x_channel_get(vic
->channel
);
304 if (!context
->channel
) {
312 pm_runtime_put(vic
->dev
);
316 static void vic_close_channel(struct tegra_drm_context
*context
)
318 struct vic
*vic
= to_vic(context
->client
);
320 host1x_channel_put(context
->channel
);
322 pm_runtime_put(vic
->dev
);
325 static const struct tegra_drm_client_ops vic_ops
= {
326 .open_channel
= vic_open_channel
,
327 .close_channel
= vic_close_channel
,
328 .submit
= tegra_drm_submit
,
331 #define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
333 static const struct vic_config vic_t124_config
= {
334 .firmware
= NVIDIA_TEGRA_124_VIC_FIRMWARE
,
336 .supports_sid
= false,
339 #define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
341 static const struct vic_config vic_t210_config
= {
342 .firmware
= NVIDIA_TEGRA_210_VIC_FIRMWARE
,
344 .supports_sid
= false,
347 #define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
349 static const struct vic_config vic_t186_config
= {
350 .firmware
= NVIDIA_TEGRA_186_VIC_FIRMWARE
,
352 .supports_sid
= true,
355 #define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
357 static const struct vic_config vic_t194_config
= {
358 .firmware
= NVIDIA_TEGRA_194_VIC_FIRMWARE
,
360 .supports_sid
= true,
363 static const struct of_device_id vic_match
[] = {
364 { .compatible
= "nvidia,tegra124-vic", .data
= &vic_t124_config
},
365 { .compatible
= "nvidia,tegra210-vic", .data
= &vic_t210_config
},
366 { .compatible
= "nvidia,tegra186-vic", .data
= &vic_t186_config
},
367 { .compatible
= "nvidia,tegra194-vic", .data
= &vic_t194_config
},
371 static int vic_probe(struct platform_device
*pdev
)
373 struct device
*dev
= &pdev
->dev
;
374 struct host1x_syncpt
**syncpts
;
375 struct resource
*regs
;
379 vic
= devm_kzalloc(dev
, sizeof(*vic
), GFP_KERNEL
);
383 vic
->config
= of_device_get_match_data(dev
);
385 syncpts
= devm_kzalloc(dev
, sizeof(*syncpts
), GFP_KERNEL
);
389 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
391 dev_err(&pdev
->dev
, "failed to get registers\n");
395 vic
->regs
= devm_ioremap_resource(dev
, regs
);
396 if (IS_ERR(vic
->regs
))
397 return PTR_ERR(vic
->regs
);
399 vic
->clk
= devm_clk_get(dev
, NULL
);
400 if (IS_ERR(vic
->clk
)) {
401 dev_err(&pdev
->dev
, "failed to get clock\n");
402 return PTR_ERR(vic
->clk
);
405 if (!dev
->pm_domain
) {
406 vic
->rst
= devm_reset_control_get(dev
, "vic");
407 if (IS_ERR(vic
->rst
)) {
408 dev_err(&pdev
->dev
, "failed to get reset\n");
409 return PTR_ERR(vic
->rst
);
413 vic
->falcon
.dev
= dev
;
414 vic
->falcon
.regs
= vic
->regs
;
415 vic
->falcon
.ops
= &vic_falcon_ops
;
417 err
= falcon_init(&vic
->falcon
);
421 platform_set_drvdata(pdev
, vic
);
423 INIT_LIST_HEAD(&vic
->client
.base
.list
);
424 vic
->client
.base
.ops
= &vic_client_ops
;
425 vic
->client
.base
.dev
= dev
;
426 vic
->client
.base
.class = HOST1X_CLASS_VIC
;
427 vic
->client
.base
.syncpts
= syncpts
;
428 vic
->client
.base
.num_syncpts
= 1;
431 INIT_LIST_HEAD(&vic
->client
.list
);
432 vic
->client
.version
= vic
->config
->version
;
433 vic
->client
.ops
= &vic_ops
;
435 err
= host1x_client_register(&vic
->client
.base
);
437 dev_err(dev
, "failed to register host1x client: %d\n", err
);
441 pm_runtime_enable(&pdev
->dev
);
442 if (!pm_runtime_enabled(&pdev
->dev
)) {
443 err
= vic_runtime_resume(&pdev
->dev
);
445 goto unregister_client
;
451 host1x_client_unregister(&vic
->client
.base
);
453 falcon_exit(&vic
->falcon
);
458 static int vic_remove(struct platform_device
*pdev
)
460 struct vic
*vic
= platform_get_drvdata(pdev
);
463 err
= host1x_client_unregister(&vic
->client
.base
);
465 dev_err(&pdev
->dev
, "failed to unregister host1x client: %d\n",
470 if (pm_runtime_enabled(&pdev
->dev
))
471 pm_runtime_disable(&pdev
->dev
);
473 vic_runtime_suspend(&pdev
->dev
);
475 falcon_exit(&vic
->falcon
);
480 static const struct dev_pm_ops vic_pm_ops
= {
481 SET_RUNTIME_PM_OPS(vic_runtime_suspend
, vic_runtime_resume
, NULL
)
484 struct platform_driver tegra_vic_driver
= {
487 .of_match_table
= vic_match
,
491 .remove
= vic_remove
,
494 #if IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC)
495 MODULE_FIRMWARE(NVIDIA_TEGRA_124_VIC_FIRMWARE
);
497 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
498 MODULE_FIRMWARE(NVIDIA_TEGRA_210_VIC_FIRMWARE
);
500 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
501 MODULE_FIRMWARE(NVIDIA_TEGRA_186_VIC_FIRMWARE
);
503 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC)
504 MODULE_FIRMWARE(NVIDIA_TEGRA_194_VIC_FIRMWARE
);