2 * Copyright (C) 2015 Broadcom
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #include <linux/mm_types.h>
10 #include <linux/reservation.h>
12 #include <drm/drm_util.h>
13 #include <drm/drm_encoder.h>
14 #include <drm/drm_gem_cma_helper.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_syncobj.h>
18 #include "uapi/drm/vc4_drm.h"
20 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to
23 enum vc4_kernel_bo_type
{
24 /* Any kernel allocation (gem_create_object hook) before it
25 * gets another type set.
29 VC4_BO_TYPE_V3D_SHADER
,
34 VC4_BO_TYPE_KERNEL_CACHE
,
38 /* Performance monitor object. The perform lifetime is controlled by userspace
39 * using perfmon related ioctls. A perfmon can be attached to a submit_cl
40 * request, and when this is the case, HW perf counters will be activated just
41 * before the submit_cl is submitted to the GPU and disabled when the job is
42 * done. This way, only events related to a specific job will be counted.
45 /* Tracks the number of users of the perfmon, when this counter reaches
46 * zero the perfmon is destroyed.
50 /* Number of counters activated in this perfmon instance
51 * (should be less than DRM_VC4_MAX_PERF_COUNTERS).
55 /* Events counted by the HW perf counters. */
56 u8 events
[DRM_VC4_MAX_PERF_COUNTERS
];
58 /* Storage for counter values. Counters are incremented by the HW
59 * perf counter values every time the perfmon is attached to a GPU job.
60 * This way, perfmon users don't have to retrieve the results after
61 * each job if they want to track events covering several submissions.
62 * Note that counter values can't be reset, but you can fake a reset by
63 * destroying the perfmon and creating a new one.
69 struct drm_device
*dev
;
71 struct vc4_hdmi
*hdmi
;
79 struct vc4_hang_state
*hang_state
;
81 /* The kernel-space BO cache. Tracks buffers that have been
82 * unreferenced by all other users (refcounts of 0!) but not
83 * yet freed, so we can do cheap allocations.
86 /* Array of list heads for entries in the BO cache,
87 * based on number of pages, so we can do O(1) lookups
88 * in the cache when allocating.
90 struct list_head
*size_list
;
91 uint32_t size_list_size
;
93 /* List of all BOs in the cache, ordered by age, so we
94 * can do O(1) lookups when trying to free old
97 struct list_head time_list
;
98 struct work_struct time_work
;
99 struct timer_list time_timer
;
109 /* Protects bo_cache and bo_labels. */
110 struct mutex bo_lock
;
112 /* Purgeable BO pool. All BOs in this pool can have their memory
113 * reclaimed if the driver is unable to allocate new BOs. We also
114 * keep stats related to the purge mechanism here.
117 struct list_head list
;
120 unsigned int purged_num
;
125 uint64_t dma_fence_context
;
127 /* Sequence number for the last job queued in bin_job_list.
128 * Starts at 0 (no jobs emitted).
132 /* Sequence number for the last completed job on the GPU.
133 * Starts at 0 (no jobs completed).
135 uint64_t finished_seqno
;
137 /* List of all struct vc4_exec_info for jobs to be executed in
138 * the binner. The first job in the list is the one currently
139 * programmed into ct0ca for execution.
141 struct list_head bin_job_list
;
143 /* List of all struct vc4_exec_info for jobs that have
144 * completed binning and are ready for rendering. The first
145 * job in the list is the one currently programmed into ct1ca
148 struct list_head render_job_list
;
150 /* List of the finished vc4_exec_infos waiting to be freed by
153 struct list_head job_done_list
;
154 /* Spinlock used to synchronize the job_list and seqno
155 * accesses between the IRQ handler and GEM ioctls.
158 wait_queue_head_t job_wait_queue
;
159 struct work_struct job_done_work
;
161 /* Used to track the active perfmon if any. Access to this field is
162 * protected by job_lock.
164 struct vc4_perfmon
*active_perfmon
;
166 /* List of struct vc4_seqno_cb for callbacks to be made from a
167 * workqueue when the given seqno is passed.
169 struct list_head seqno_cb_list
;
171 /* The memory used for storing binner tile alloc, tile state,
172 * and overflow memory allocations. This is freed when V3D
175 struct vc4_bo
*bin_bo
;
177 /* Size of blocks allocated within bin_bo. */
178 uint32_t bin_alloc_size
;
180 /* Bitmask of the bin_alloc_size chunks in bin_bo that are
183 uint32_t bin_alloc_used
;
185 /* Bitmask of the current bin_alloc used for overflow memory. */
186 uint32_t bin_alloc_overflow
;
188 struct work_struct overflow_mem_work
;
192 /* Mutex controlling the power refcount. */
193 struct mutex power_lock
;
196 struct timer_list timer
;
197 struct work_struct reset_work
;
200 struct semaphore async_modeset
;
202 struct drm_modeset_lock ctm_state_lock
;
203 struct drm_private_obj ctm_manager
;
206 static inline struct vc4_dev
*
207 to_vc4_dev(struct drm_device
*dev
)
209 return (struct vc4_dev
*)dev
->dev_private
;
213 struct drm_gem_cma_object base
;
215 /* seqno of the last job to render using this BO. */
218 /* seqno of the last job to use the RCL to write to this BO.
220 * Note that this doesn't include binner overflow memory
223 uint64_t write_seqno
;
227 /* List entry for the BO's position in either
228 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list
230 struct list_head unref_head
;
232 /* Time in jiffies when the BO was put in vc4->bo_cache. */
233 unsigned long free_time
;
235 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */
236 struct list_head size_head
;
238 /* Struct for shader validation state, if created by
239 * DRM_IOCTL_VC4_CREATE_SHADER_BO.
241 struct vc4_validated_shader_info
*validated_shader
;
243 /* normally (resv == &_resv) except for imported bo's */
244 struct reservation_object
*resv
;
245 struct reservation_object _resv
;
247 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i
248 * for user-allocated labels.
252 /* Count the number of active users. This is needed to determine
253 * whether we can move the BO to the purgeable list or not (when the BO
254 * is used by the GPU or the display engine we can't purge it).
258 /* Store purgeable/purged state here */
260 struct mutex madv_lock
;
263 static inline struct vc4_bo
*
264 to_vc4_bo(struct drm_gem_object
*bo
)
266 return (struct vc4_bo
*)bo
;
270 struct dma_fence base
;
271 struct drm_device
*dev
;
272 /* vc4 seqno for signaled() test */
276 static inline struct vc4_fence
*
277 to_vc4_fence(struct dma_fence
*fence
)
279 return (struct vc4_fence
*)fence
;
282 struct vc4_seqno_cb
{
283 struct work_struct work
;
285 void (*func
)(struct vc4_seqno_cb
*cb
);
290 struct platform_device
*pdev
;
296 struct platform_device
*pdev
;
300 /* Memory manager for CRTCs to allocate space in the display
301 * list. Units are dwords.
303 struct drm_mm dlist_mm
;
304 /* Memory manager for the LBM memory used by HVS scaling. */
305 struct drm_mm lbm_mm
;
308 struct drm_mm_node mitchell_netravali_filter
;
312 struct drm_plane base
;
315 static inline struct vc4_plane
*
316 to_vc4_plane(struct drm_plane
*plane
)
318 return (struct vc4_plane
*)plane
;
321 enum vc4_scaling_mode
{
327 struct vc4_plane_state
{
328 struct drm_plane_state base
;
329 /* System memory copy of the display list for this element, computed
330 * at atomic_check time.
333 u32 dlist_size
; /* Number of dwords allocated for the display list */
334 u32 dlist_count
; /* Number of used dwords in the display list. */
336 /* Offset in the dlist to various words, for pageflip or
344 /* Offset where the plane's dlist was last stored in the
345 * hardware at vc4_crtc_atomic_flush() time.
347 u32 __iomem
*hw_dlist
;
349 /* Clipped coordinates of the plane on the display. */
350 int crtc_x
, crtc_y
, crtc_w
, crtc_h
;
351 /* Clipped area being scanned from in the FB. */
354 u32 src_w
[2], src_h
[2];
356 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */
357 enum vc4_scaling_mode x_scaling
[2], y_scaling
[2];
361 /* Offset to start scanning out from the start of the plane's
366 /* Our allocation in LBM for temporary storage during scaling. */
367 struct drm_mm_node lbm
;
369 /* Set when the plane has per-pixel alpha content or does not cover
370 * the entire screen. This is a hint to the CRTC that it might need
371 * to enable background color fill.
375 /* Mark the dlist as initialized. Useful to avoid initializing it twice
376 * when async update is not possible.
378 bool dlist_initialized
;
381 static inline struct vc4_plane_state
*
382 to_vc4_plane_state(struct drm_plane_state
*state
)
384 return (struct vc4_plane_state
*)state
;
387 enum vc4_encoder_type
{
388 VC4_ENCODER_TYPE_NONE
,
389 VC4_ENCODER_TYPE_HDMI
,
390 VC4_ENCODER_TYPE_VEC
,
391 VC4_ENCODER_TYPE_DSI0
,
392 VC4_ENCODER_TYPE_DSI1
,
393 VC4_ENCODER_TYPE_SMI
,
394 VC4_ENCODER_TYPE_DPI
,
398 struct drm_encoder base
;
399 enum vc4_encoder_type type
;
403 static inline struct vc4_encoder
*
404 to_vc4_encoder(struct drm_encoder
*encoder
)
406 return container_of(encoder
, struct vc4_encoder
, base
);
409 struct vc4_crtc_data
{
410 /* Which channel of the HVS this pixelvalve sources from. */
413 enum vc4_encoder_type encoder_types
[4];
417 struct drm_crtc base
;
418 const struct vc4_crtc_data
*data
;
421 /* Timestamp at start of vblank irq - unaffected by lock delays. */
424 /* Which HVS channel we're using for our CRTC. */
430 /* Size in pixels of the COB memory allocated to this CRTC. */
433 struct drm_pending_vblank_event
*event
;
436 static inline struct vc4_crtc
*
437 to_vc4_crtc(struct drm_crtc
*crtc
)
439 return (struct vc4_crtc
*)crtc
;
442 #define V3D_READ(offset) readl(vc4->v3d->regs + offset)
443 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)
444 #define HVS_READ(offset) readl(vc4->hvs->regs + offset)
445 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset)
447 struct vc4_exec_info
{
448 /* Sequence number for this bin/render job. */
451 /* Latest write_seqno of any BO that binning depends on. */
452 uint64_t bin_dep_seqno
;
454 struct dma_fence
*fence
;
456 /* Last current addresses the hardware was processing when the
457 * hangcheck timer checked on us.
459 uint32_t last_ct0ca
, last_ct1ca
;
461 /* Kernel-space copy of the ioctl arguments */
462 struct drm_vc4_submit_cl
*args
;
464 /* This is the array of BOs that were looked up at the start of exec.
465 * Command validation will use indices into this array.
467 struct drm_gem_cma_object
**bo
;
470 /* List of BOs that are being written by the RCL. Other than
471 * the binner temporary storage, this is all the BOs written
474 struct drm_gem_cma_object
*rcl_write_bo
[4];
475 uint32_t rcl_write_bo_count
;
477 /* Pointers for our position in vc4->job_list */
478 struct list_head head
;
480 /* List of other BOs used in the job that need to be released
481 * once the job is complete.
483 struct list_head unref_list
;
485 /* Current unvalidated indices into @bo loaded by the non-hardware
486 * VC4_PACKET_GEM_HANDLES.
488 uint32_t bo_index
[2];
490 /* This is the BO where we store the validated command lists, shader
491 * records, and uniforms.
493 struct drm_gem_cma_object
*exec_bo
;
496 * This tracks the per-shader-record state (packet 64) that
497 * determines the length of the shader record and the offset
498 * it's expected to be found at. It gets read in from the
501 struct vc4_shader_state
{
503 /* Maximum vertex index referenced by any primitive using this
509 /** How many shader states the user declared they were using. */
510 uint32_t shader_state_size
;
511 /** How many shader state records the validator has seen. */
512 uint32_t shader_state_count
;
514 bool found_tile_binning_mode_config_packet
;
515 bool found_start_tile_binning_packet
;
516 bool found_increment_semaphore_packet
;
518 uint8_t bin_tiles_x
, bin_tiles_y
;
519 /* Physical address of the start of the tile alloc array
520 * (where each tile's binned CL will start)
522 uint32_t tile_alloc_offset
;
523 /* Bitmask of which binner slots are freed when this job completes. */
527 * Computed addresses pointing into exec_bo where we start the
528 * bin thread (ct0) and render thread (ct1).
530 uint32_t ct0ca
, ct0ea
;
531 uint32_t ct1ca
, ct1ea
;
533 /* Pointer to the unvalidated bin CL (if present). */
536 /* Pointers to the shader recs. These paddr gets incremented as CL
537 * packets are relocated in validate_gl_shader_state, and the vaddrs
538 * (u and v) get incremented and size decremented as the shader recs
539 * themselves are validated.
543 uint32_t shader_rec_p
;
544 uint32_t shader_rec_size
;
546 /* Pointers to the uniform data. These pointers are incremented, and
547 * size decremented, as each batch of uniforms is uploaded.
552 uint32_t uniforms_size
;
554 /* Pointer to a performance monitor object if the user requested it,
557 struct vc4_perfmon
*perfmon
;
560 /* Per-open file private data. Any driver-specific resource that has to be
561 * released when the DRM file is closed should be placed here.
570 static inline struct vc4_exec_info
*
571 vc4_first_bin_job(struct vc4_dev
*vc4
)
573 return list_first_entry_or_null(&vc4
->bin_job_list
,
574 struct vc4_exec_info
, head
);
577 static inline struct vc4_exec_info
*
578 vc4_first_render_job(struct vc4_dev
*vc4
)
580 return list_first_entry_or_null(&vc4
->render_job_list
,
581 struct vc4_exec_info
, head
);
584 static inline struct vc4_exec_info
*
585 vc4_last_render_job(struct vc4_dev
*vc4
)
587 if (list_empty(&vc4
->render_job_list
))
589 return list_last_entry(&vc4
->render_job_list
,
590 struct vc4_exec_info
, head
);
594 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture
597 * This will be used at draw time to relocate the reference to the texture
598 * contents in p0, and validate that the offset combined with
599 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO.
600 * Note that the hardware treats unprovided config parameters as 0, so not all
601 * of them need to be set up for every texure sample, and we'll store ~0 as
602 * the offset to mark the unused ones.
604 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit
605 * Setup") for definitions of the texture parameters.
607 struct vc4_texture_sample_info
{
609 uint32_t p_offset
[4];
613 * struct vc4_validated_shader_info - information about validated shaders that
614 * needs to be used from command list validation.
616 * For a given shader, each time a shader state record references it, we need
617 * to verify that the shader doesn't read more uniforms than the shader state
618 * record's uniform BO pointer can provide, and we need to apply relocations
619 * and validate the shader state record's uniforms that define the texture
622 struct vc4_validated_shader_info
{
623 uint32_t uniforms_size
;
624 uint32_t uniforms_src_size
;
625 uint32_t num_texture_samples
;
626 struct vc4_texture_sample_info
*texture_samples
;
628 uint32_t num_uniform_addr_offsets
;
629 uint32_t *uniform_addr_offsets
;
635 * _wait_for - magic (register) wait macro
637 * Does the right thing for modeset paths when run under kdgb or similar atomic
638 * contexts. Note that it's important that we check the condition again after
639 * having timed out, since the timeout could be due to preemption or similar and
640 * we've never had a chance to check the condition before the timeout.
642 #define _wait_for(COND, MS, W) ({ \
643 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
646 if (time_after(jiffies, timeout__)) { \
648 ret__ = -ETIMEDOUT; \
651 if (W && drm_can_sleep()) { \
660 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
663 struct drm_gem_object
*vc4_create_object(struct drm_device
*dev
, size_t size
);
664 void vc4_free_object(struct drm_gem_object
*gem_obj
);
665 struct vc4_bo
*vc4_bo_create(struct drm_device
*dev
, size_t size
,
666 bool from_cache
, enum vc4_kernel_bo_type type
);
667 int vc4_dumb_create(struct drm_file
*file_priv
,
668 struct drm_device
*dev
,
669 struct drm_mode_create_dumb
*args
);
670 struct dma_buf
*vc4_prime_export(struct drm_device
*dev
,
671 struct drm_gem_object
*obj
, int flags
);
672 int vc4_create_bo_ioctl(struct drm_device
*dev
, void *data
,
673 struct drm_file
*file_priv
);
674 int vc4_create_shader_bo_ioctl(struct drm_device
*dev
, void *data
,
675 struct drm_file
*file_priv
);
676 int vc4_mmap_bo_ioctl(struct drm_device
*dev
, void *data
,
677 struct drm_file
*file_priv
);
678 int vc4_set_tiling_ioctl(struct drm_device
*dev
, void *data
,
679 struct drm_file
*file_priv
);
680 int vc4_get_tiling_ioctl(struct drm_device
*dev
, void *data
,
681 struct drm_file
*file_priv
);
682 int vc4_get_hang_state_ioctl(struct drm_device
*dev
, void *data
,
683 struct drm_file
*file_priv
);
684 int vc4_label_bo_ioctl(struct drm_device
*dev
, void *data
,
685 struct drm_file
*file_priv
);
686 vm_fault_t
vc4_fault(struct vm_fault
*vmf
);
687 int vc4_mmap(struct file
*filp
, struct vm_area_struct
*vma
);
688 struct reservation_object
*vc4_prime_res_obj(struct drm_gem_object
*obj
);
689 int vc4_prime_mmap(struct drm_gem_object
*obj
, struct vm_area_struct
*vma
);
690 struct drm_gem_object
*vc4_prime_import_sg_table(struct drm_device
*dev
,
691 struct dma_buf_attachment
*attach
,
692 struct sg_table
*sgt
);
693 void *vc4_prime_vmap(struct drm_gem_object
*obj
);
694 int vc4_bo_cache_init(struct drm_device
*dev
);
695 void vc4_bo_cache_destroy(struct drm_device
*dev
);
696 int vc4_bo_stats_debugfs(struct seq_file
*m
, void *arg
);
697 int vc4_bo_inc_usecnt(struct vc4_bo
*bo
);
698 void vc4_bo_dec_usecnt(struct vc4_bo
*bo
);
699 void vc4_bo_add_to_purgeable_pool(struct vc4_bo
*bo
);
700 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo
*bo
);
703 extern struct platform_driver vc4_crtc_driver
;
704 int vc4_crtc_debugfs_regs(struct seq_file
*m
, void *arg
);
705 bool vc4_crtc_get_scanoutpos(struct drm_device
*dev
, unsigned int crtc_id
,
706 bool in_vblank_irq
, int *vpos
, int *hpos
,
707 ktime_t
*stime
, ktime_t
*etime
,
708 const struct drm_display_mode
*mode
);
709 void vc4_crtc_handle_vblank(struct vc4_crtc
*crtc
);
710 void vc4_crtc_txp_armed(struct drm_crtc_state
*state
);
711 void vc4_crtc_get_margins(struct drm_crtc_state
*state
,
712 unsigned int *right
, unsigned int *left
,
713 unsigned int *top
, unsigned int *bottom
);
716 int vc4_debugfs_init(struct drm_minor
*minor
);
719 void __iomem
*vc4_ioremap_regs(struct platform_device
*dev
, int index
);
722 extern struct platform_driver vc4_dpi_driver
;
723 int vc4_dpi_debugfs_regs(struct seq_file
*m
, void *unused
);
726 extern struct platform_driver vc4_dsi_driver
;
727 int vc4_dsi_debugfs_regs(struct seq_file
*m
, void *unused
);
730 extern const struct dma_fence_ops vc4_fence_ops
;
733 void vc4_gem_init(struct drm_device
*dev
);
734 void vc4_gem_destroy(struct drm_device
*dev
);
735 int vc4_submit_cl_ioctl(struct drm_device
*dev
, void *data
,
736 struct drm_file
*file_priv
);
737 int vc4_wait_seqno_ioctl(struct drm_device
*dev
, void *data
,
738 struct drm_file
*file_priv
);
739 int vc4_wait_bo_ioctl(struct drm_device
*dev
, void *data
,
740 struct drm_file
*file_priv
);
741 void vc4_submit_next_bin_job(struct drm_device
*dev
);
742 void vc4_submit_next_render_job(struct drm_device
*dev
);
743 void vc4_move_job_to_render(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
744 int vc4_wait_for_seqno(struct drm_device
*dev
, uint64_t seqno
,
745 uint64_t timeout_ns
, bool interruptible
);
746 void vc4_job_handle_completed(struct vc4_dev
*vc4
);
747 int vc4_queue_seqno_cb(struct drm_device
*dev
,
748 struct vc4_seqno_cb
*cb
, uint64_t seqno
,
749 void (*func
)(struct vc4_seqno_cb
*cb
));
750 int vc4_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
751 struct drm_file
*file_priv
);
754 extern struct platform_driver vc4_hdmi_driver
;
755 int vc4_hdmi_debugfs_regs(struct seq_file
*m
, void *unused
);
758 extern struct platform_driver vc4_vec_driver
;
759 int vc4_vec_debugfs_regs(struct seq_file
*m
, void *unused
);
762 extern struct platform_driver vc4_txp_driver
;
763 int vc4_txp_debugfs_regs(struct seq_file
*m
, void *unused
);
766 irqreturn_t
vc4_irq(int irq
, void *arg
);
767 void vc4_irq_preinstall(struct drm_device
*dev
);
768 int vc4_irq_postinstall(struct drm_device
*dev
);
769 void vc4_irq_uninstall(struct drm_device
*dev
);
770 void vc4_irq_reset(struct drm_device
*dev
);
773 extern struct platform_driver vc4_hvs_driver
;
774 void vc4_hvs_dump_state(struct drm_device
*dev
);
775 int vc4_hvs_debugfs_regs(struct seq_file
*m
, void *unused
);
778 int vc4_kms_load(struct drm_device
*dev
);
781 struct drm_plane
*vc4_plane_init(struct drm_device
*dev
,
782 enum drm_plane_type type
);
783 u32
vc4_plane_write_dlist(struct drm_plane
*plane
, u32 __iomem
*dlist
);
784 u32
vc4_plane_dlist_size(const struct drm_plane_state
*state
);
785 void vc4_plane_async_set_fb(struct drm_plane
*plane
,
786 struct drm_framebuffer
*fb
);
789 extern struct platform_driver vc4_v3d_driver
;
790 int vc4_v3d_debugfs_ident(struct seq_file
*m
, void *unused
);
791 int vc4_v3d_debugfs_regs(struct seq_file
*m
, void *unused
);
792 int vc4_v3d_get_bin_slot(struct vc4_dev
*vc4
);
796 vc4_validate_bin_cl(struct drm_device
*dev
,
799 struct vc4_exec_info
*exec
);
802 vc4_validate_shader_recs(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
804 struct drm_gem_cma_object
*vc4_use_bo(struct vc4_exec_info
*exec
,
807 int vc4_get_rcl(struct drm_device
*dev
, struct vc4_exec_info
*exec
);
809 bool vc4_check_tex_size(struct vc4_exec_info
*exec
,
810 struct drm_gem_cma_object
*fbo
,
811 uint32_t offset
, uint8_t tiling_format
,
812 uint32_t width
, uint32_t height
, uint8_t cpp
);
814 /* vc4_validate_shader.c */
815 struct vc4_validated_shader_info
*
816 vc4_validate_shader(struct drm_gem_cma_object
*shader_obj
);
819 void vc4_perfmon_get(struct vc4_perfmon
*perfmon
);
820 void vc4_perfmon_put(struct vc4_perfmon
*perfmon
);
821 void vc4_perfmon_start(struct vc4_dev
*vc4
, struct vc4_perfmon
*perfmon
);
822 void vc4_perfmon_stop(struct vc4_dev
*vc4
, struct vc4_perfmon
*perfmon
,
824 struct vc4_perfmon
*vc4_perfmon_find(struct vc4_file
*vc4file
, int id
);
825 void vc4_perfmon_open_file(struct vc4_file
*vc4file
);
826 void vc4_perfmon_close_file(struct vc4_file
*vc4file
);
827 int vc4_perfmon_create_ioctl(struct drm_device
*dev
, void *data
,
828 struct drm_file
*file_priv
);
829 int vc4_perfmon_destroy_ioctl(struct drm_device
*dev
, void *data
,
830 struct drm_file
*file_priv
);
831 int vc4_perfmon_get_values_ioctl(struct drm_device
*dev
, void *data
,
832 struct drm_file
*file_priv
);