2 * Copyright (C) 2012-2014 Mentor Graphics Inc.
3 * Copyright 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/spinlock.h>
17 #include <linux/bitrev.h>
19 #include <linux/err.h>
20 #include <linux/sizes.h>
23 /* IC Register Offsets */
24 #define IC_CONF 0x0000
25 #define IC_PRP_ENC_RSC 0x0004
26 #define IC_PRP_VF_RSC 0x0008
27 #define IC_PP_RSC 0x000C
28 #define IC_CMBP_1 0x0010
29 #define IC_CMBP_2 0x0014
30 #define IC_IDMAC_1 0x0018
31 #define IC_IDMAC_2 0x001C
32 #define IC_IDMAC_3 0x0020
33 #define IC_IDMAC_4 0x0024
35 /* IC Register Fields */
36 #define IC_CONF_PRPENC_EN (1 << 0)
37 #define IC_CONF_PRPENC_CSC1 (1 << 1)
38 #define IC_CONF_PRPENC_ROT_EN (1 << 2)
39 #define IC_CONF_PRPVF_EN (1 << 8)
40 #define IC_CONF_PRPVF_CSC1 (1 << 9)
41 #define IC_CONF_PRPVF_CSC2 (1 << 10)
42 #define IC_CONF_PRPVF_CMB (1 << 11)
43 #define IC_CONF_PRPVF_ROT_EN (1 << 12)
44 #define IC_CONF_PP_EN (1 << 16)
45 #define IC_CONF_PP_CSC1 (1 << 17)
46 #define IC_CONF_PP_CSC2 (1 << 18)
47 #define IC_CONF_PP_CMB (1 << 19)
48 #define IC_CONF_PP_ROT_EN (1 << 20)
49 #define IC_CONF_IC_GLB_LOC_A (1 << 28)
50 #define IC_CONF_KEY_COLOR_EN (1 << 29)
51 #define IC_CONF_RWS_EN (1 << 30)
52 #define IC_CONF_CSI_MEM_WR_EN (1 << 31)
54 #define IC_IDMAC_1_CB0_BURST_16 (1 << 0)
55 #define IC_IDMAC_1_CB1_BURST_16 (1 << 1)
56 #define IC_IDMAC_1_CB2_BURST_16 (1 << 2)
57 #define IC_IDMAC_1_CB3_BURST_16 (1 << 3)
58 #define IC_IDMAC_1_CB4_BURST_16 (1 << 4)
59 #define IC_IDMAC_1_CB5_BURST_16 (1 << 5)
60 #define IC_IDMAC_1_CB6_BURST_16 (1 << 6)
61 #define IC_IDMAC_1_CB7_BURST_16 (1 << 7)
62 #define IC_IDMAC_1_PRPENC_ROT_MASK (0x7 << 11)
63 #define IC_IDMAC_1_PRPENC_ROT_OFFSET 11
64 #define IC_IDMAC_1_PRPVF_ROT_MASK (0x7 << 14)
65 #define IC_IDMAC_1_PRPVF_ROT_OFFSET 14
66 #define IC_IDMAC_1_PP_ROT_MASK (0x7 << 17)
67 #define IC_IDMAC_1_PP_ROT_OFFSET 17
68 #define IC_IDMAC_1_PP_FLIP_RS (1 << 22)
69 #define IC_IDMAC_1_PRPVF_FLIP_RS (1 << 21)
70 #define IC_IDMAC_1_PRPENC_FLIP_RS (1 << 20)
72 #define IC_IDMAC_2_PRPENC_HEIGHT_MASK (0x3ff << 0)
73 #define IC_IDMAC_2_PRPENC_HEIGHT_OFFSET 0
74 #define IC_IDMAC_2_PRPVF_HEIGHT_MASK (0x3ff << 10)
75 #define IC_IDMAC_2_PRPVF_HEIGHT_OFFSET 10
76 #define IC_IDMAC_2_PP_HEIGHT_MASK (0x3ff << 20)
77 #define IC_IDMAC_2_PP_HEIGHT_OFFSET 20
79 #define IC_IDMAC_3_PRPENC_WIDTH_MASK (0x3ff << 0)
80 #define IC_IDMAC_3_PRPENC_WIDTH_OFFSET 0
81 #define IC_IDMAC_3_PRPVF_WIDTH_MASK (0x3ff << 10)
82 #define IC_IDMAC_3_PRPVF_WIDTH_OFFSET 10
83 #define IC_IDMAC_3_PP_WIDTH_MASK (0x3ff << 20)
84 #define IC_IDMAC_3_PP_WIDTH_OFFSET 20
86 struct ic_task_regoffs
{
91 struct ic_task_bitfields
{
97 u32 ic_cmb_galpha_bit
;
100 static const struct ic_task_regoffs ic_task_reg
[IC_NUM_TASKS
] = {
101 [IC_TASK_ENCODER
] = {
102 .rsc
= IC_PRP_ENC_RSC
,
103 .tpmem_csc
= {0x2008, 0},
105 [IC_TASK_VIEWFINDER
] = {
106 .rsc
= IC_PRP_VF_RSC
,
107 .tpmem_csc
= {0x4028, 0x4040},
109 [IC_TASK_POST_PROCESSOR
] = {
111 .tpmem_csc
= {0x6060, 0x6078},
115 static const struct ic_task_bitfields ic_task_bit
[IC_NUM_TASKS
] = {
116 [IC_TASK_ENCODER
] = {
117 .ic_conf_en
= IC_CONF_PRPENC_EN
,
118 .ic_conf_rot_en
= IC_CONF_PRPENC_ROT_EN
,
119 .ic_conf_cmb_en
= 0, /* NA */
120 .ic_conf_csc1_en
= IC_CONF_PRPENC_CSC1
,
121 .ic_conf_csc2_en
= 0, /* NA */
122 .ic_cmb_galpha_bit
= 0, /* NA */
124 [IC_TASK_VIEWFINDER
] = {
125 .ic_conf_en
= IC_CONF_PRPVF_EN
,
126 .ic_conf_rot_en
= IC_CONF_PRPVF_ROT_EN
,
127 .ic_conf_cmb_en
= IC_CONF_PRPVF_CMB
,
128 .ic_conf_csc1_en
= IC_CONF_PRPVF_CSC1
,
129 .ic_conf_csc2_en
= IC_CONF_PRPVF_CSC2
,
130 .ic_cmb_galpha_bit
= 0,
132 [IC_TASK_POST_PROCESSOR
] = {
133 .ic_conf_en
= IC_CONF_PP_EN
,
134 .ic_conf_rot_en
= IC_CONF_PP_ROT_EN
,
135 .ic_conf_cmb_en
= IC_CONF_PP_CMB
,
136 .ic_conf_csc1_en
= IC_CONF_PP_CSC1
,
137 .ic_conf_csc2_en
= IC_CONF_PP_CSC2
,
138 .ic_cmb_galpha_bit
= 8,
145 enum ipu_ic_task task
;
146 const struct ic_task_regoffs
*reg
;
147 const struct ic_task_bitfields
*bit
;
149 enum ipu_color_space in_cs
, g_in_cs
;
150 enum ipu_color_space out_cs
;
155 struct ipu_ic_priv
*priv
;
160 void __iomem
*tpmem_base
;
165 struct ipu_ic task
[IC_NUM_TASKS
];
168 static inline u32
ipu_ic_read(struct ipu_ic
*ic
, unsigned offset
)
170 return readl(ic
->priv
->base
+ offset
);
173 static inline void ipu_ic_write(struct ipu_ic
*ic
, u32 value
, unsigned offset
)
175 writel(value
, ic
->priv
->base
+ offset
);
178 struct ic_csc_params
{
179 s16 coeff
[3][3]; /* signed 9-bit integer coefficients */
180 s16 offset
[3]; /* signed 11+2-bit fixed point offset */
181 u8 scale
:2; /* scale coefficients * 2^(scale-1) */
182 bool sat
:1; /* saturate to (16, 235(Y) / 240(U, V)) */
186 * Y = R * .299 + G * .587 + B * .114;
187 * U = R * -.169 + G * -.332 + B * .500 + 128.;
188 * V = R * .500 + G * -.419 + B * -.0813 + 128.;
190 static const struct ic_csc_params ic_csc_rgb2ycbcr
= {
196 .offset
= { 0, 512, 512 },
200 /* transparent RGB->RGB matrix for graphics combining */
201 static const struct ic_csc_params ic_csc_rgb2rgb
= {
211 * R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
212 * G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
213 * B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
215 static const struct ic_csc_params ic_csc_ycbcr2rgb
= {
221 .offset
= { -446, 266, -554 },
225 static int init_csc(struct ipu_ic
*ic
,
226 enum ipu_color_space inf
,
227 enum ipu_color_space outf
,
230 struct ipu_ic_priv
*priv
= ic
->priv
;
231 const struct ic_csc_params
*params
;
237 base
= (u32 __iomem
*)
238 (priv
->tpmem_base
+ ic
->reg
->tpmem_csc
[csc_index
]);
240 if (inf
== IPUV3_COLORSPACE_YUV
&& outf
== IPUV3_COLORSPACE_RGB
)
241 params
= &ic_csc_ycbcr2rgb
;
242 else if (inf
== IPUV3_COLORSPACE_RGB
&& outf
== IPUV3_COLORSPACE_YUV
)
243 params
= &ic_csc_rgb2ycbcr
;
244 else if (inf
== IPUV3_COLORSPACE_RGB
&& outf
== IPUV3_COLORSPACE_RGB
)
245 params
= &ic_csc_rgb2rgb
;
247 dev_err(priv
->ipu
->dev
, "Unsupported color space conversion\n");
251 /* Cast to unsigned */
252 c
= (const u16 (*)[3])params
->coeff
;
253 a
= (const u16
*)params
->offset
;
255 param
= ((a
[0] & 0x1f) << 27) | ((c
[0][0] & 0x1ff) << 18) |
256 ((c
[1][1] & 0x1ff) << 9) | (c
[2][2] & 0x1ff);
257 writel(param
, base
++);
259 param
= ((a
[0] & 0x1fe0) >> 5) | (params
->scale
<< 8) |
261 writel(param
, base
++);
263 param
= ((a
[1] & 0x1f) << 27) | ((c
[0][1] & 0x1ff) << 18) |
264 ((c
[1][0] & 0x1ff) << 9) | (c
[2][0] & 0x1ff);
265 writel(param
, base
++);
267 param
= ((a
[1] & 0x1fe0) >> 5);
268 writel(param
, base
++);
270 param
= ((a
[2] & 0x1f) << 27) | ((c
[0][2] & 0x1ff) << 18) |
271 ((c
[1][2] & 0x1ff) << 9) | (c
[2][1] & 0x1ff);
272 writel(param
, base
++);
274 param
= ((a
[2] & 0x1fe0) >> 5);
275 writel(param
, base
++);
280 static int calc_resize_coeffs(struct ipu_ic
*ic
,
281 u32 in_size
, u32 out_size
,
285 struct ipu_ic_priv
*priv
= ic
->priv
;
286 struct ipu_soc
*ipu
= priv
->ipu
;
287 u32 temp_size
, temp_downsize
;
290 * Input size cannot be more than 4096, and output size cannot
293 if (in_size
> 4096) {
294 dev_err(ipu
->dev
, "Unsupported resize (in_size > 4096)\n");
297 if (out_size
> 1024) {
298 dev_err(ipu
->dev
, "Unsupported resize (out_size > 1024)\n");
302 /* Cannot downsize more than 4:1 */
303 if ((out_size
<< 2) < in_size
) {
304 dev_err(ipu
->dev
, "Unsupported downsize\n");
308 /* Compute downsizing coefficient */
311 while (((temp_size
> 1024) || (temp_size
>= out_size
* 2)) &&
312 (temp_downsize
< 2)) {
316 *downsize_coeff
= temp_downsize
;
319 * compute resizing coefficient using the following equation:
320 * resize_coeff = M * (SI - 1) / (SO - 1)
321 * where M = 2^13, SI = input size, SO = output size
323 *resize_coeff
= (8192L * (temp_size
- 1)) / (out_size
- 1);
324 if (*resize_coeff
>= 16384L) {
325 dev_err(ipu
->dev
, "Warning! Overflow on resize coeff.\n");
326 *resize_coeff
= 0x3FFF;
332 void ipu_ic_task_enable(struct ipu_ic
*ic
)
334 struct ipu_ic_priv
*priv
= ic
->priv
;
338 spin_lock_irqsave(&priv
->lock
, flags
);
340 ic_conf
= ipu_ic_read(ic
, IC_CONF
);
342 ic_conf
|= ic
->bit
->ic_conf_en
;
345 ic_conf
|= ic
->bit
->ic_conf_rot_en
;
347 if (ic
->in_cs
!= ic
->out_cs
)
348 ic_conf
|= ic
->bit
->ic_conf_csc1_en
;
351 ic_conf
|= ic
->bit
->ic_conf_cmb_en
;
352 ic_conf
|= ic
->bit
->ic_conf_csc1_en
;
354 if (ic
->g_in_cs
!= ic
->out_cs
)
355 ic_conf
|= ic
->bit
->ic_conf_csc2_en
;
358 ipu_ic_write(ic
, ic_conf
, IC_CONF
);
360 spin_unlock_irqrestore(&priv
->lock
, flags
);
362 EXPORT_SYMBOL_GPL(ipu_ic_task_enable
);
364 void ipu_ic_task_disable(struct ipu_ic
*ic
)
366 struct ipu_ic_priv
*priv
= ic
->priv
;
370 spin_lock_irqsave(&priv
->lock
, flags
);
372 ic_conf
= ipu_ic_read(ic
, IC_CONF
);
374 ic_conf
&= ~(ic
->bit
->ic_conf_en
|
375 ic
->bit
->ic_conf_csc1_en
|
376 ic
->bit
->ic_conf_rot_en
);
377 if (ic
->bit
->ic_conf_csc2_en
)
378 ic_conf
&= ~ic
->bit
->ic_conf_csc2_en
;
379 if (ic
->bit
->ic_conf_cmb_en
)
380 ic_conf
&= ~ic
->bit
->ic_conf_cmb_en
;
382 ipu_ic_write(ic
, ic_conf
, IC_CONF
);
384 spin_unlock_irqrestore(&priv
->lock
, flags
);
386 EXPORT_SYMBOL_GPL(ipu_ic_task_disable
);
388 int ipu_ic_task_graphics_init(struct ipu_ic
*ic
,
389 enum ipu_color_space in_g_cs
,
390 bool galpha_en
, u32 galpha
,
391 bool colorkey_en
, u32 colorkey
)
393 struct ipu_ic_priv
*priv
= ic
->priv
;
398 if (ic
->task
== IC_TASK_ENCODER
)
401 spin_lock_irqsave(&priv
->lock
, flags
);
403 ic_conf
= ipu_ic_read(ic
, IC_CONF
);
405 if (!(ic_conf
& ic
->bit
->ic_conf_csc1_en
)) {
406 /* need transparent CSC1 conversion */
407 ret
= init_csc(ic
, IPUV3_COLORSPACE_RGB
,
408 IPUV3_COLORSPACE_RGB
, 0);
413 ic
->g_in_cs
= in_g_cs
;
415 if (ic
->g_in_cs
!= ic
->out_cs
) {
416 ret
= init_csc(ic
, ic
->g_in_cs
, ic
->out_cs
, 1);
422 ic_conf
|= IC_CONF_IC_GLB_LOC_A
;
423 reg
= ipu_ic_read(ic
, IC_CMBP_1
);
424 reg
&= ~(0xff << ic
->bit
->ic_cmb_galpha_bit
);
425 reg
|= (galpha
<< ic
->bit
->ic_cmb_galpha_bit
);
426 ipu_ic_write(ic
, reg
, IC_CMBP_1
);
428 ic_conf
&= ~IC_CONF_IC_GLB_LOC_A
;
431 ic_conf
|= IC_CONF_KEY_COLOR_EN
;
432 ipu_ic_write(ic
, colorkey
, IC_CMBP_2
);
434 ic_conf
&= ~IC_CONF_KEY_COLOR_EN
;
436 ipu_ic_write(ic
, ic_conf
, IC_CONF
);
440 spin_unlock_irqrestore(&priv
->lock
, flags
);
443 EXPORT_SYMBOL_GPL(ipu_ic_task_graphics_init
);
445 int ipu_ic_task_init_rsc(struct ipu_ic
*ic
,
446 int in_width
, int in_height
,
447 int out_width
, int out_height
,
448 enum ipu_color_space in_cs
,
449 enum ipu_color_space out_cs
,
452 struct ipu_ic_priv
*priv
= ic
->priv
;
453 u32 downsize_coeff
, resize_coeff
;
458 /* Setup vertical resizing */
460 ret
= calc_resize_coeffs(ic
, in_height
, out_height
,
461 &resize_coeff
, &downsize_coeff
);
465 rsc
= (downsize_coeff
<< 30) | (resize_coeff
<< 16);
467 /* Setup horizontal resizing */
468 ret
= calc_resize_coeffs(ic
, in_width
, out_width
,
469 &resize_coeff
, &downsize_coeff
);
473 rsc
|= (downsize_coeff
<< 14) | resize_coeff
;
476 spin_lock_irqsave(&priv
->lock
, flags
);
478 ipu_ic_write(ic
, rsc
, ic
->reg
->rsc
);
480 /* Setup color space conversion */
484 if (ic
->in_cs
!= ic
->out_cs
) {
485 ret
= init_csc(ic
, ic
->in_cs
, ic
->out_cs
, 0);
491 spin_unlock_irqrestore(&priv
->lock
, flags
);
495 int ipu_ic_task_init(struct ipu_ic
*ic
,
496 int in_width
, int in_height
,
497 int out_width
, int out_height
,
498 enum ipu_color_space in_cs
,
499 enum ipu_color_space out_cs
)
501 return ipu_ic_task_init_rsc(ic
, in_width
, in_height
, out_width
,
502 out_height
, in_cs
, out_cs
, 0);
504 EXPORT_SYMBOL_GPL(ipu_ic_task_init
);
506 int ipu_ic_task_idma_init(struct ipu_ic
*ic
, struct ipuv3_channel
*channel
,
507 u32 width
, u32 height
, int burst_size
,
508 enum ipu_rotate_mode rot
)
510 struct ipu_ic_priv
*priv
= ic
->priv
;
511 struct ipu_soc
*ipu
= priv
->ipu
;
512 u32 ic_idmac_1
, ic_idmac_2
, ic_idmac_3
;
513 u32 temp_rot
= bitrev8(rot
) >> 5;
514 bool need_hor_flip
= false;
518 if ((burst_size
!= 8) && (burst_size
!= 16)) {
519 dev_err(ipu
->dev
, "Illegal burst length for IC\n");
526 if (temp_rot
& 0x2) /* Need horizontal flip */
527 need_hor_flip
= true;
529 spin_lock_irqsave(&priv
->lock
, flags
);
531 ic_idmac_1
= ipu_ic_read(ic
, IC_IDMAC_1
);
532 ic_idmac_2
= ipu_ic_read(ic
, IC_IDMAC_2
);
533 ic_idmac_3
= ipu_ic_read(ic
, IC_IDMAC_3
);
535 switch (channel
->num
) {
536 case IPUV3_CHANNEL_IC_PP_MEM
:
537 if (burst_size
== 16)
538 ic_idmac_1
|= IC_IDMAC_1_CB2_BURST_16
;
540 ic_idmac_1
&= ~IC_IDMAC_1_CB2_BURST_16
;
543 ic_idmac_1
|= IC_IDMAC_1_PP_FLIP_RS
;
545 ic_idmac_1
&= ~IC_IDMAC_1_PP_FLIP_RS
;
547 ic_idmac_2
&= ~IC_IDMAC_2_PP_HEIGHT_MASK
;
548 ic_idmac_2
|= height
<< IC_IDMAC_2_PP_HEIGHT_OFFSET
;
550 ic_idmac_3
&= ~IC_IDMAC_3_PP_WIDTH_MASK
;
551 ic_idmac_3
|= width
<< IC_IDMAC_3_PP_WIDTH_OFFSET
;
553 case IPUV3_CHANNEL_MEM_IC_PP
:
554 if (burst_size
== 16)
555 ic_idmac_1
|= IC_IDMAC_1_CB5_BURST_16
;
557 ic_idmac_1
&= ~IC_IDMAC_1_CB5_BURST_16
;
559 case IPUV3_CHANNEL_MEM_ROT_PP
:
560 ic_idmac_1
&= ~IC_IDMAC_1_PP_ROT_MASK
;
561 ic_idmac_1
|= temp_rot
<< IC_IDMAC_1_PP_ROT_OFFSET
;
563 case IPUV3_CHANNEL_MEM_IC_PRP_VF
:
564 if (burst_size
== 16)
565 ic_idmac_1
|= IC_IDMAC_1_CB6_BURST_16
;
567 ic_idmac_1
&= ~IC_IDMAC_1_CB6_BURST_16
;
569 case IPUV3_CHANNEL_IC_PRP_ENC_MEM
:
570 if (burst_size
== 16)
571 ic_idmac_1
|= IC_IDMAC_1_CB0_BURST_16
;
573 ic_idmac_1
&= ~IC_IDMAC_1_CB0_BURST_16
;
576 ic_idmac_1
|= IC_IDMAC_1_PRPENC_FLIP_RS
;
578 ic_idmac_1
&= ~IC_IDMAC_1_PRPENC_FLIP_RS
;
580 ic_idmac_2
&= ~IC_IDMAC_2_PRPENC_HEIGHT_MASK
;
581 ic_idmac_2
|= height
<< IC_IDMAC_2_PRPENC_HEIGHT_OFFSET
;
583 ic_idmac_3
&= ~IC_IDMAC_3_PRPENC_WIDTH_MASK
;
584 ic_idmac_3
|= width
<< IC_IDMAC_3_PRPENC_WIDTH_OFFSET
;
586 case IPUV3_CHANNEL_MEM_ROT_ENC
:
587 ic_idmac_1
&= ~IC_IDMAC_1_PRPENC_ROT_MASK
;
588 ic_idmac_1
|= temp_rot
<< IC_IDMAC_1_PRPENC_ROT_OFFSET
;
590 case IPUV3_CHANNEL_IC_PRP_VF_MEM
:
591 if (burst_size
== 16)
592 ic_idmac_1
|= IC_IDMAC_1_CB1_BURST_16
;
594 ic_idmac_1
&= ~IC_IDMAC_1_CB1_BURST_16
;
597 ic_idmac_1
|= IC_IDMAC_1_PRPVF_FLIP_RS
;
599 ic_idmac_1
&= ~IC_IDMAC_1_PRPVF_FLIP_RS
;
601 ic_idmac_2
&= ~IC_IDMAC_2_PRPVF_HEIGHT_MASK
;
602 ic_idmac_2
|= height
<< IC_IDMAC_2_PRPVF_HEIGHT_OFFSET
;
604 ic_idmac_3
&= ~IC_IDMAC_3_PRPVF_WIDTH_MASK
;
605 ic_idmac_3
|= width
<< IC_IDMAC_3_PRPVF_WIDTH_OFFSET
;
607 case IPUV3_CHANNEL_MEM_ROT_VF
:
608 ic_idmac_1
&= ~IC_IDMAC_1_PRPVF_ROT_MASK
;
609 ic_idmac_1
|= temp_rot
<< IC_IDMAC_1_PRPVF_ROT_OFFSET
;
611 case IPUV3_CHANNEL_G_MEM_IC_PRP_VF
:
612 if (burst_size
== 16)
613 ic_idmac_1
|= IC_IDMAC_1_CB3_BURST_16
;
615 ic_idmac_1
&= ~IC_IDMAC_1_CB3_BURST_16
;
617 case IPUV3_CHANNEL_G_MEM_IC_PP
:
618 if (burst_size
== 16)
619 ic_idmac_1
|= IC_IDMAC_1_CB4_BURST_16
;
621 ic_idmac_1
&= ~IC_IDMAC_1_CB4_BURST_16
;
623 case IPUV3_CHANNEL_VDI_MEM_IC_VF
:
624 if (burst_size
== 16)
625 ic_idmac_1
|= IC_IDMAC_1_CB7_BURST_16
;
627 ic_idmac_1
&= ~IC_IDMAC_1_CB7_BURST_16
;
633 ipu_ic_write(ic
, ic_idmac_1
, IC_IDMAC_1
);
634 ipu_ic_write(ic
, ic_idmac_2
, IC_IDMAC_2
);
635 ipu_ic_write(ic
, ic_idmac_3
, IC_IDMAC_3
);
637 if (ipu_rot_mode_is_irt(rot
))
641 spin_unlock_irqrestore(&priv
->lock
, flags
);
644 EXPORT_SYMBOL_GPL(ipu_ic_task_idma_init
);
646 static void ipu_irt_enable(struct ipu_ic
*ic
)
648 struct ipu_ic_priv
*priv
= ic
->priv
;
650 if (!priv
->irt_use_count
)
651 ipu_module_enable(priv
->ipu
, IPU_CONF_ROT_EN
);
653 priv
->irt_use_count
++;
656 static void ipu_irt_disable(struct ipu_ic
*ic
)
658 struct ipu_ic_priv
*priv
= ic
->priv
;
660 if (priv
->irt_use_count
) {
661 if (!--priv
->irt_use_count
)
662 ipu_module_disable(priv
->ipu
, IPU_CONF_ROT_EN
);
666 int ipu_ic_enable(struct ipu_ic
*ic
)
668 struct ipu_ic_priv
*priv
= ic
->priv
;
671 spin_lock_irqsave(&priv
->lock
, flags
);
673 if (!priv
->use_count
)
674 ipu_module_enable(priv
->ipu
, IPU_CONF_IC_EN
);
681 spin_unlock_irqrestore(&priv
->lock
, flags
);
685 EXPORT_SYMBOL_GPL(ipu_ic_enable
);
687 int ipu_ic_disable(struct ipu_ic
*ic
)
689 struct ipu_ic_priv
*priv
= ic
->priv
;
692 spin_lock_irqsave(&priv
->lock
, flags
);
696 if (!priv
->use_count
)
697 ipu_module_disable(priv
->ipu
, IPU_CONF_IC_EN
);
699 if (priv
->use_count
< 0)
705 ic
->rotation
= ic
->graphics
= false;
707 spin_unlock_irqrestore(&priv
->lock
, flags
);
711 EXPORT_SYMBOL_GPL(ipu_ic_disable
);
713 struct ipu_ic
*ipu_ic_get(struct ipu_soc
*ipu
, enum ipu_ic_task task
)
715 struct ipu_ic_priv
*priv
= ipu
->ic_priv
;
717 struct ipu_ic
*ic
, *ret
;
719 if (task
>= IC_NUM_TASKS
)
720 return ERR_PTR(-EINVAL
);
722 ic
= &priv
->task
[task
];
724 spin_lock_irqsave(&priv
->lock
, flags
);
727 ret
= ERR_PTR(-EBUSY
);
735 spin_unlock_irqrestore(&priv
->lock
, flags
);
738 EXPORT_SYMBOL_GPL(ipu_ic_get
);
740 void ipu_ic_put(struct ipu_ic
*ic
)
742 struct ipu_ic_priv
*priv
= ic
->priv
;
745 spin_lock_irqsave(&priv
->lock
, flags
);
747 spin_unlock_irqrestore(&priv
->lock
, flags
);
749 EXPORT_SYMBOL_GPL(ipu_ic_put
);
751 int ipu_ic_init(struct ipu_soc
*ipu
, struct device
*dev
,
752 unsigned long base
, unsigned long tpmem_base
)
754 struct ipu_ic_priv
*priv
;
757 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
763 spin_lock_init(&priv
->lock
);
764 priv
->base
= devm_ioremap(dev
, base
, PAGE_SIZE
);
767 priv
->tpmem_base
= devm_ioremap(dev
, tpmem_base
, SZ_64K
);
768 if (!priv
->tpmem_base
)
771 dev_dbg(dev
, "IC base: 0x%08lx remapped to %p\n", base
, priv
->base
);
775 for (i
= 0; i
< IC_NUM_TASKS
; i
++) {
776 priv
->task
[i
].task
= i
;
777 priv
->task
[i
].priv
= priv
;
778 priv
->task
[i
].reg
= &ic_task_reg
[i
];
779 priv
->task
[i
].bit
= &ic_task_bit
[i
];
785 void ipu_ic_exit(struct ipu_soc
*ipu
)
789 void ipu_ic_dump(struct ipu_ic
*ic
)
791 struct ipu_ic_priv
*priv
= ic
->priv
;
792 struct ipu_soc
*ipu
= priv
->ipu
;
794 dev_dbg(ipu
->dev
, "IC_CONF = \t0x%08X\n",
795 ipu_ic_read(ic
, IC_CONF
));
796 dev_dbg(ipu
->dev
, "IC_PRP_ENC_RSC = \t0x%08X\n",
797 ipu_ic_read(ic
, IC_PRP_ENC_RSC
));
798 dev_dbg(ipu
->dev
, "IC_PRP_VF_RSC = \t0x%08X\n",
799 ipu_ic_read(ic
, IC_PRP_VF_RSC
));
800 dev_dbg(ipu
->dev
, "IC_PP_RSC = \t0x%08X\n",
801 ipu_ic_read(ic
, IC_PP_RSC
));
802 dev_dbg(ipu
->dev
, "IC_CMBP_1 = \t0x%08X\n",
803 ipu_ic_read(ic
, IC_CMBP_1
));
804 dev_dbg(ipu
->dev
, "IC_CMBP_2 = \t0x%08X\n",
805 ipu_ic_read(ic
, IC_CMBP_2
));
806 dev_dbg(ipu
->dev
, "IC_IDMAC_1 = \t0x%08X\n",
807 ipu_ic_read(ic
, IC_IDMAC_1
));
808 dev_dbg(ipu
->dev
, "IC_IDMAC_2 = \t0x%08X\n",
809 ipu_ic_read(ic
, IC_IDMAC_2
));
810 dev_dbg(ipu
->dev
, "IC_IDMAC_3 = \t0x%08X\n",
811 ipu_ic_read(ic
, IC_IDMAC_3
));
812 dev_dbg(ipu
->dev
, "IC_IDMAC_4 = \t0x%08X\n",
813 ipu_ic_read(ic
, IC_IDMAC_4
));
815 EXPORT_SYMBOL_GPL(ipu_ic_dump
);