1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2012-2016 Mentor Graphics Inc.
5 * Queued image conversion support, with tiling and rotation.
8 #include <linux/interrupt.h>
9 #include <linux/dma-mapping.h>
10 #include <video/imx-ipu-image-convert.h>
14 * The IC Resizer has a restriction that the output frame from the
15 * resizer must be 1024 or less in both width (pixels) and height
18 * The image converter attempts to split up a conversion when
19 * the desired output (converted) frame resolution exceeds the
20 * IC resizer limit of 1024 in either dimension.
22 * If either dimension of the output frame exceeds the limit, the
23 * dimension is split into 1, 2, or 4 equal stripes, for a maximum
24 * of 4*4 or 16 tiles. A conversion is then carried out for each
25 * tile (but taking care to pass the full frame stride length to
26 * the DMA channel's parameter memory!). IDMA double-buffering is used
27 * to convert each tile back-to-back when possible (see note below
28 * when double_buffering boolean is set).
30 * Note that the input frame must be split up into the same number
31 * of tiles as the output frame:
34 * +-----+---+ | A | B |
36 * +-----+---+ --> +---------+-----+
41 * Clockwise 90° rotations are handled by first rescaling into a
42 * reusable temporary tile buffer and then rotating with the 8x8
43 * block rotator, writing to the correct destination:
47 * +-----+---+ +---------+ | C | A |
48 * | A | B | | A,B, | | | | |
49 * +-----+---+ --> | C,D | | --> | | |
50 * | C | D | +---------+ +-----+-----+
51 * +-----+---+ | D | B |
55 * If the 8x8 block rotator is used, horizontal or vertical flipping
56 * is done during the rotation step, otherwise flipping is done
57 * during the scaling step.
58 * With rotation or flipping, tile order changes between input and
59 * output image. Tiles are numbered row major from top left to bottom
60 * right for both input and output image.
63 #define MAX_STRIPES_W 4
64 #define MAX_STRIPES_H 4
65 #define MAX_TILES (MAX_STRIPES_W * MAX_STRIPES_H)
72 enum ipu_image_convert_type
{
77 struct ipu_image_convert_dma_buf
{
83 struct ipu_image_convert_dma_chan
{
93 /* dimensions of one tile */
94 struct ipu_image_tile
{
99 /* size and strides are in bytes */
103 /* start Y or packed offset of this tile */
105 /* offset from start to tile in U plane, for planar formats */
107 /* offset from start to tile in V plane, for planar formats */
111 struct ipu_image_convert_image
{
112 struct ipu_image base
;
113 enum ipu_image_convert_type type
;
115 const struct ipu_image_pixfmt
*fmt
;
118 /* # of rows (horizontal stripes) if dest height is > 1024 */
119 unsigned int num_rows
;
120 /* # of columns (vertical stripes) if dest width is > 1024 */
121 unsigned int num_cols
;
123 struct ipu_image_tile tile
[MAX_TILES
];
126 struct ipu_image_pixfmt
{
127 u32 fourcc
; /* V4L2 fourcc */
128 int bpp
; /* total bpp */
129 int uv_width_dec
; /* decimation in width for U/V planes */
130 int uv_height_dec
; /* decimation in height for U/V planes */
131 bool planar
; /* planar format */
132 bool uv_swapped
; /* U and V planes are swapped */
133 bool uv_packed
; /* partial planar (U and V in same plane) */
136 struct ipu_image_convert_ctx
;
137 struct ipu_image_convert_chan
;
138 struct ipu_image_convert_priv
;
140 struct ipu_image_convert_ctx
{
141 struct ipu_image_convert_chan
*chan
;
143 ipu_image_convert_cb_t complete
;
144 void *complete_context
;
146 /* Source/destination image data and rotation mode */
147 struct ipu_image_convert_image in
;
148 struct ipu_image_convert_image out
;
149 enum ipu_rotate_mode rot_mode
;
150 u32 downsize_coeff_h
;
151 u32 downsize_coeff_v
;
152 u32 image_resize_coeff_h
;
153 u32 image_resize_coeff_v
;
154 u32 resize_coeffs_h
[MAX_STRIPES_W
];
155 u32 resize_coeffs_v
[MAX_STRIPES_H
];
157 /* intermediate buffer for rotation */
158 struct ipu_image_convert_dma_buf rot_intermediate
[2];
160 /* current buffer number for double buffering */
164 struct completion aborted
;
166 /* can we use double-buffering for this conversion operation? */
167 bool double_buffering
;
168 /* num_rows * num_cols */
169 unsigned int num_tiles
;
170 /* next tile to process */
171 unsigned int next_tile
;
172 /* where to place converted tile in dest image */
173 unsigned int out_tile_map
[MAX_TILES
];
175 struct list_head list
;
178 struct ipu_image_convert_chan
{
179 struct ipu_image_convert_priv
*priv
;
181 enum ipu_ic_task ic_task
;
182 const struct ipu_image_convert_dma_chan
*dma_ch
;
185 struct ipuv3_channel
*in_chan
;
186 struct ipuv3_channel
*out_chan
;
187 struct ipuv3_channel
*rotation_in_chan
;
188 struct ipuv3_channel
*rotation_out_chan
;
190 /* the IPU end-of-frame irqs */
196 /* list of convert contexts */
197 struct list_head ctx_list
;
198 /* queue of conversion runs */
199 struct list_head pending_q
;
200 /* queue of completed runs */
201 struct list_head done_q
;
203 /* the current conversion run */
204 struct ipu_image_convert_run
*current_run
;
207 struct ipu_image_convert_priv
{
208 struct ipu_image_convert_chan chan
[IC_NUM_TASKS
];
212 static const struct ipu_image_convert_dma_chan
213 image_convert_dma_chan
[IC_NUM_TASKS
] = {
214 [IC_TASK_VIEWFINDER
] = {
215 .in
= IPUV3_CHANNEL_MEM_IC_PRP_VF
,
216 .out
= IPUV3_CHANNEL_IC_PRP_VF_MEM
,
217 .rot_in
= IPUV3_CHANNEL_MEM_ROT_VF
,
218 .rot_out
= IPUV3_CHANNEL_ROT_VF_MEM
,
219 .vdi_in_p
= IPUV3_CHANNEL_MEM_VDI_PREV
,
220 .vdi_in
= IPUV3_CHANNEL_MEM_VDI_CUR
,
221 .vdi_in_n
= IPUV3_CHANNEL_MEM_VDI_NEXT
,
223 [IC_TASK_POST_PROCESSOR
] = {
224 .in
= IPUV3_CHANNEL_MEM_IC_PP
,
225 .out
= IPUV3_CHANNEL_IC_PP_MEM
,
226 .rot_in
= IPUV3_CHANNEL_MEM_ROT_PP
,
227 .rot_out
= IPUV3_CHANNEL_ROT_PP_MEM
,
231 static const struct ipu_image_pixfmt image_convert_formats
[] = {
233 .fourcc
= V4L2_PIX_FMT_RGB565
,
236 .fourcc
= V4L2_PIX_FMT_RGB24
,
239 .fourcc
= V4L2_PIX_FMT_BGR24
,
242 .fourcc
= V4L2_PIX_FMT_RGB32
,
245 .fourcc
= V4L2_PIX_FMT_BGR32
,
248 .fourcc
= V4L2_PIX_FMT_XRGB32
,
251 .fourcc
= V4L2_PIX_FMT_XBGR32
,
254 .fourcc
= V4L2_PIX_FMT_YUYV
,
259 .fourcc
= V4L2_PIX_FMT_UYVY
,
264 .fourcc
= V4L2_PIX_FMT_YUV420
,
270 .fourcc
= V4L2_PIX_FMT_YVU420
,
277 .fourcc
= V4L2_PIX_FMT_NV12
,
284 .fourcc
= V4L2_PIX_FMT_YUV422P
,
290 .fourcc
= V4L2_PIX_FMT_NV16
,
299 static const struct ipu_image_pixfmt
*get_format(u32 fourcc
)
301 const struct ipu_image_pixfmt
*ret
= NULL
;
304 for (i
= 0; i
< ARRAY_SIZE(image_convert_formats
); i
++) {
305 if (image_convert_formats
[i
].fourcc
== fourcc
) {
306 ret
= &image_convert_formats
[i
];
314 static void dump_format(struct ipu_image_convert_ctx
*ctx
,
315 struct ipu_image_convert_image
*ic_image
)
317 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
318 struct ipu_image_convert_priv
*priv
= chan
->priv
;
320 dev_dbg(priv
->ipu
->dev
,
321 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n",
323 ic_image
->type
== IMAGE_CONVERT_OUT
? "Output" : "Input",
324 ic_image
->base
.pix
.width
, ic_image
->base
.pix
.height
,
325 ic_image
->num_cols
, ic_image
->num_rows
,
326 ic_image
->fmt
->fourcc
& 0xff,
327 (ic_image
->fmt
->fourcc
>> 8) & 0xff,
328 (ic_image
->fmt
->fourcc
>> 16) & 0xff,
329 (ic_image
->fmt
->fourcc
>> 24) & 0xff);
332 int ipu_image_convert_enum_format(int index
, u32
*fourcc
)
334 const struct ipu_image_pixfmt
*fmt
;
336 if (index
>= (int)ARRAY_SIZE(image_convert_formats
))
340 fmt
= &image_convert_formats
[index
];
341 *fourcc
= fmt
->fourcc
;
344 EXPORT_SYMBOL_GPL(ipu_image_convert_enum_format
);
346 static void free_dma_buf(struct ipu_image_convert_priv
*priv
,
347 struct ipu_image_convert_dma_buf
*buf
)
350 dma_free_coherent(priv
->ipu
->dev
,
351 buf
->len
, buf
->virt
, buf
->phys
);
356 static int alloc_dma_buf(struct ipu_image_convert_priv
*priv
,
357 struct ipu_image_convert_dma_buf
*buf
,
360 buf
->len
= PAGE_ALIGN(size
);
361 buf
->virt
= dma_alloc_coherent(priv
->ipu
->dev
, buf
->len
, &buf
->phys
,
362 GFP_DMA
| GFP_KERNEL
);
364 dev_err(priv
->ipu
->dev
, "failed to alloc dma buffer\n");
371 static inline int num_stripes(int dim
)
373 return (dim
- 1) / 1024 + 1;
377 * Calculate downsizing coefficients, which are the same for all tiles,
378 * and bilinear resizing coefficients, which are used to find the best
381 static int calc_image_resize_coefficients(struct ipu_image_convert_ctx
*ctx
,
382 struct ipu_image
*in
,
383 struct ipu_image
*out
)
385 u32 downsized_width
= in
->rect
.width
;
386 u32 downsized_height
= in
->rect
.height
;
387 u32 downsize_coeff_v
= 0;
388 u32 downsize_coeff_h
= 0;
389 u32 resized_width
= out
->rect
.width
;
390 u32 resized_height
= out
->rect
.height
;
394 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
395 resized_width
= out
->rect
.height
;
396 resized_height
= out
->rect
.width
;
399 /* Do not let invalid input lead to an endless loop below */
400 if (WARN_ON(resized_width
== 0 || resized_height
== 0))
403 while (downsized_width
>= resized_width
* 2) {
404 downsized_width
>>= 1;
408 while (downsized_height
>= resized_height
* 2) {
409 downsized_height
>>= 1;
414 * Calculate the bilinear resizing coefficients that could be used if
415 * we were converting with a single tile. The bottom right output pixel
416 * should sample as close as possible to the bottom right input pixel
417 * out of the decimator, but not overshoot it:
419 resize_coeff_h
= 8192 * (downsized_width
- 1) / (resized_width
- 1);
420 resize_coeff_v
= 8192 * (downsized_height
- 1) / (resized_height
- 1);
422 dev_dbg(ctx
->chan
->priv
->ipu
->dev
,
423 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n",
424 __func__
, downsize_coeff_h
, resize_coeff_h
, downsize_coeff_v
,
425 resize_coeff_v
, ctx
->in
.num_cols
, ctx
->in
.num_rows
);
427 if (downsize_coeff_h
> 2 || downsize_coeff_v
> 2 ||
428 resize_coeff_h
> 0x3fff || resize_coeff_v
> 0x3fff)
431 ctx
->downsize_coeff_h
= downsize_coeff_h
;
432 ctx
->downsize_coeff_v
= downsize_coeff_v
;
433 ctx
->image_resize_coeff_h
= resize_coeff_h
;
434 ctx
->image_resize_coeff_v
= resize_coeff_v
;
439 #define round_closest(x, y) round_down((x) + (y)/2, (y))
442 * Find the best aligned seam position in the inverval [out_start, out_end].
443 * Rotation and image offsets are out of scope.
445 * @out_start: start of inverval, must be within 1024 pixels / lines
447 * @out_end: end of interval, smaller than or equal to out_edge
448 * @in_edge: input right / bottom edge
449 * @out_edge: output right / bottom edge
450 * @in_align: input alignment, either horizontal 8-byte line start address
451 * alignment, or pixel alignment due to image format
452 * @out_align: output alignment, either horizontal 8-byte line start address
453 * alignment, or pixel alignment due to image format or rotator
455 * @in_burst: horizontal input burst size in case of horizontal flip
456 * @out_burst: horizontal output burst size or rotator block size
457 * @downsize_coeff: downsizing section coefficient
458 * @resize_coeff: main processing section resizing coefficient
459 * @_in_seam: aligned input seam position return value
460 * @_out_seam: aligned output seam position return value
462 static void find_best_seam(struct ipu_image_convert_ctx
*ctx
,
463 unsigned int out_start
,
464 unsigned int out_end
,
465 unsigned int in_edge
,
466 unsigned int out_edge
,
467 unsigned int in_align
,
468 unsigned int out_align
,
469 unsigned int in_burst
,
470 unsigned int out_burst
,
471 unsigned int downsize_coeff
,
472 unsigned int resize_coeff
,
476 struct device
*dev
= ctx
->chan
->priv
->ipu
->dev
;
477 unsigned int out_pos
;
478 /* Input / output seam position candidates */
479 unsigned int out_seam
= 0;
480 unsigned int in_seam
= 0;
481 unsigned int min_diff
= UINT_MAX
;
484 * Output tiles must start at a multiple of 8 bytes horizontally and
485 * possibly at an even line horizontally depending on the pixel format.
486 * Only consider output aligned positions for the seam.
488 out_start
= round_up(out_start
, out_align
);
489 for (out_pos
= out_start
; out_pos
< out_end
; out_pos
+= out_align
) {
491 unsigned int in_pos_aligned
;
492 unsigned int abs_diff
;
495 * Tiles in the right row / bottom column may not be allowed to
496 * overshoot horizontally / vertically. out_burst may be the
497 * actual DMA burst size, or the rotator block size.
499 if ((out_burst
> 1) && (out_edge
- out_pos
) % out_burst
)
503 * Input sample position, corresponding to out_pos, 19.13 fixed
506 in_pos
= (out_pos
* resize_coeff
) << downsize_coeff
;
508 * The closest input sample position that we could actually
509 * start the input tile at, 19.13 fixed point.
511 in_pos_aligned
= round_closest(in_pos
, 8192U * in_align
);
513 if ((in_burst
> 1) &&
514 (in_edge
- in_pos_aligned
/ 8192U) % in_burst
)
517 if (in_pos
< in_pos_aligned
)
518 abs_diff
= in_pos_aligned
- in_pos
;
520 abs_diff
= in_pos
- in_pos_aligned
;
522 if (abs_diff
< min_diff
) {
523 in_seam
= in_pos_aligned
;
529 *_out_seam
= out_seam
;
530 /* Convert 19.13 fixed point to integer seam position */
531 *_in_seam
= DIV_ROUND_CLOSEST(in_seam
, 8192U);
533 dev_dbg(dev
, "%s: out_seam %u(%u) in [%u, %u], in_seam %u(%u) diff %u.%03u\n",
534 __func__
, out_seam
, out_align
, out_start
, out_end
,
535 *_in_seam
, in_align
, min_diff
/ 8192,
536 DIV_ROUND_CLOSEST(min_diff
% 8192 * 1000, 8192));
540 * Tile left edges are required to be aligned to multiples of 8 bytes
543 static inline u32
tile_left_align(const struct ipu_image_pixfmt
*fmt
)
546 return fmt
->uv_packed
? 8 : 8 * fmt
->uv_width_dec
;
548 return fmt
->bpp
== 32 ? 2 : fmt
->bpp
== 16 ? 4 : 8;
552 * Tile top edge alignment is only limited by chroma subsampling.
554 static inline u32
tile_top_align(const struct ipu_image_pixfmt
*fmt
)
556 return fmt
->uv_height_dec
> 1 ? 2 : 1;
559 static inline u32
tile_width_align(enum ipu_image_convert_type type
,
560 const struct ipu_image_pixfmt
*fmt
,
561 enum ipu_rotate_mode rot_mode
)
563 if (type
== IMAGE_CONVERT_IN
) {
565 * The IC burst reads 8 pixels at a time. Reading beyond the
566 * end of the line is usually acceptable. Those pixels are
567 * ignored, unless the IC has to write the scaled line in
570 return (!ipu_rot_mode_is_irt(rot_mode
) &&
571 (rot_mode
& IPU_ROT_BIT_HFLIP
)) ? 8 : 2;
575 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled
576 * formats to guarantee 8-byte aligned line start addresses in the
577 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size
578 * for all other formats.
580 return (ipu_rot_mode_is_irt(rot_mode
) &&
581 fmt
->planar
&& !fmt
->uv_packed
) ?
582 8 * fmt
->uv_width_dec
: 8;
585 static inline u32
tile_height_align(enum ipu_image_convert_type type
,
586 const struct ipu_image_pixfmt
*fmt
,
587 enum ipu_rotate_mode rot_mode
)
589 if (type
== IMAGE_CONVERT_IN
|| !ipu_rot_mode_is_irt(rot_mode
))
593 * Align to 16x16 pixel blocks for planar 4:2:0 chroma subsampled
594 * formats to guarantee 8-byte aligned line start addresses in the
595 * chroma planes when IRT is used. Align to 8x8 pixel IRT block size
596 * for all other formats.
598 return (fmt
->planar
&& !fmt
->uv_packed
) ? 8 * fmt
->uv_width_dec
: 8;
602 * Fill in left position and width and for all tiles in an input column, and
603 * for all corresponding output tiles. If the 90° rotator is used, the output
604 * tiles are in a row, and output tile top position and height are set.
606 static void fill_tile_column(struct ipu_image_convert_ctx
*ctx
,
608 struct ipu_image_convert_image
*in
,
609 unsigned int in_left
, unsigned int in_width
,
610 struct ipu_image_convert_image
*out
,
611 unsigned int out_left
, unsigned int out_width
)
613 unsigned int row
, tile_idx
;
614 struct ipu_image_tile
*in_tile
, *out_tile
;
616 for (row
= 0; row
< in
->num_rows
; row
++) {
617 tile_idx
= in
->num_cols
* row
+ col
;
618 in_tile
= &in
->tile
[tile_idx
];
619 out_tile
= &out
->tile
[ctx
->out_tile_map
[tile_idx
]];
621 in_tile
->left
= in_left
;
622 in_tile
->width
= in_width
;
624 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
625 out_tile
->top
= out_left
;
626 out_tile
->height
= out_width
;
628 out_tile
->left
= out_left
;
629 out_tile
->width
= out_width
;
635 * Fill in top position and height and for all tiles in an input row, and
636 * for all corresponding output tiles. If the 90° rotator is used, the output
637 * tiles are in a column, and output tile left position and width are set.
639 static void fill_tile_row(struct ipu_image_convert_ctx
*ctx
, unsigned int row
,
640 struct ipu_image_convert_image
*in
,
641 unsigned int in_top
, unsigned int in_height
,
642 struct ipu_image_convert_image
*out
,
643 unsigned int out_top
, unsigned int out_height
)
645 unsigned int col
, tile_idx
;
646 struct ipu_image_tile
*in_tile
, *out_tile
;
648 for (col
= 0; col
< in
->num_cols
; col
++) {
649 tile_idx
= in
->num_cols
* row
+ col
;
650 in_tile
= &in
->tile
[tile_idx
];
651 out_tile
= &out
->tile
[ctx
->out_tile_map
[tile_idx
]];
653 in_tile
->top
= in_top
;
654 in_tile
->height
= in_height
;
656 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
657 out_tile
->left
= out_top
;
658 out_tile
->width
= out_height
;
660 out_tile
->top
= out_top
;
661 out_tile
->height
= out_height
;
667 * Find the best horizontal and vertical seam positions to split into tiles.
668 * Minimize the fractional part of the input sampling position for the
669 * top / left pixels of each tile.
671 static void find_seams(struct ipu_image_convert_ctx
*ctx
,
672 struct ipu_image_convert_image
*in
,
673 struct ipu_image_convert_image
*out
)
675 struct device
*dev
= ctx
->chan
->priv
->ipu
->dev
;
676 unsigned int resized_width
= out
->base
.rect
.width
;
677 unsigned int resized_height
= out
->base
.rect
.height
;
680 unsigned int in_left_align
= tile_left_align(in
->fmt
);
681 unsigned int in_top_align
= tile_top_align(in
->fmt
);
682 unsigned int out_left_align
= tile_left_align(out
->fmt
);
683 unsigned int out_top_align
= tile_top_align(out
->fmt
);
684 unsigned int out_width_align
= tile_width_align(out
->type
, out
->fmt
,
686 unsigned int out_height_align
= tile_height_align(out
->type
, out
->fmt
,
688 unsigned int in_right
= in
->base
.rect
.width
;
689 unsigned int in_bottom
= in
->base
.rect
.height
;
690 unsigned int out_right
= out
->base
.rect
.width
;
691 unsigned int out_bottom
= out
->base
.rect
.height
;
692 unsigned int flipped_out_left
;
693 unsigned int flipped_out_top
;
695 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
696 /* Switch width/height and align top left to IRT block size */
697 resized_width
= out
->base
.rect
.height
;
698 resized_height
= out
->base
.rect
.width
;
699 out_left_align
= out_height_align
;
700 out_top_align
= out_width_align
;
701 out_width_align
= out_left_align
;
702 out_height_align
= out_top_align
;
703 out_right
= out
->base
.rect
.height
;
704 out_bottom
= out
->base
.rect
.width
;
707 for (col
= in
->num_cols
- 1; col
> 0; col
--) {
708 bool allow_in_overshoot
= ipu_rot_mode_is_irt(ctx
->rot_mode
) ||
709 !(ctx
->rot_mode
& IPU_ROT_BIT_HFLIP
);
710 bool allow_out_overshoot
= (col
< in
->num_cols
- 1) &&
711 !(ctx
->rot_mode
& IPU_ROT_BIT_HFLIP
);
712 unsigned int out_start
;
713 unsigned int out_end
;
714 unsigned int in_left
;
715 unsigned int out_left
;
718 * Align input width to burst length if the scaling step flips
722 /* Start within 1024 pixels of the right edge */
723 out_start
= max_t(int, 0, out_right
- 1024);
724 /* End before having to add more columns to the left */
725 out_end
= min_t(unsigned int, out_right
, col
* 1024);
727 find_best_seam(ctx
, out_start
, out_end
,
729 in_left_align
, out_left_align
,
730 allow_in_overshoot
? 1 : 8 /* burst length */,
731 allow_out_overshoot
? 1 : out_width_align
,
732 ctx
->downsize_coeff_h
, ctx
->image_resize_coeff_h
,
733 &in_left
, &out_left
);
735 if (ctx
->rot_mode
& IPU_ROT_BIT_HFLIP
)
736 flipped_out_left
= resized_width
- out_right
;
738 flipped_out_left
= out_left
;
740 fill_tile_column(ctx
, col
, in
, in_left
, in_right
- in_left
,
741 out
, flipped_out_left
, out_right
- out_left
);
743 dev_dbg(dev
, "%s: col %u: %u, %u -> %u, %u\n", __func__
, col
,
744 in_left
, in_right
- in_left
,
745 flipped_out_left
, out_right
- out_left
);
748 out_right
= out_left
;
751 flipped_out_left
= (ctx
->rot_mode
& IPU_ROT_BIT_HFLIP
) ?
752 resized_width
- out_right
: 0;
754 fill_tile_column(ctx
, 0, in
, 0, in_right
,
755 out
, flipped_out_left
, out_right
);
757 dev_dbg(dev
, "%s: col 0: 0, %u -> %u, %u\n", __func__
,
758 in_right
, flipped_out_left
, out_right
);
760 for (row
= in
->num_rows
- 1; row
> 0; row
--) {
761 bool allow_overshoot
= row
< in
->num_rows
- 1;
762 unsigned int out_start
;
763 unsigned int out_end
;
765 unsigned int out_top
;
767 /* Start within 1024 lines of the bottom edge */
768 out_start
= max_t(int, 0, out_bottom
- 1024);
769 /* End before having to add more rows above */
770 out_end
= min_t(unsigned int, out_bottom
, row
* 1024);
772 find_best_seam(ctx
, out_start
, out_end
,
773 in_bottom
, out_bottom
,
774 in_top_align
, out_top_align
,
775 1, allow_overshoot
? 1 : out_height_align
,
776 ctx
->downsize_coeff_v
, ctx
->image_resize_coeff_v
,
779 if ((ctx
->rot_mode
& IPU_ROT_BIT_VFLIP
) ^
780 ipu_rot_mode_is_irt(ctx
->rot_mode
))
781 flipped_out_top
= resized_height
- out_bottom
;
783 flipped_out_top
= out_top
;
785 fill_tile_row(ctx
, row
, in
, in_top
, in_bottom
- in_top
,
786 out
, flipped_out_top
, out_bottom
- out_top
);
788 dev_dbg(dev
, "%s: row %u: %u, %u -> %u, %u\n", __func__
, row
,
789 in_top
, in_bottom
- in_top
,
790 flipped_out_top
, out_bottom
- out_top
);
793 out_bottom
= out_top
;
796 if ((ctx
->rot_mode
& IPU_ROT_BIT_VFLIP
) ^
797 ipu_rot_mode_is_irt(ctx
->rot_mode
))
798 flipped_out_top
= resized_height
- out_bottom
;
802 fill_tile_row(ctx
, 0, in
, 0, in_bottom
,
803 out
, flipped_out_top
, out_bottom
);
805 dev_dbg(dev
, "%s: row 0: 0, %u -> %u, %u\n", __func__
,
806 in_bottom
, flipped_out_top
, out_bottom
);
809 static void calc_tile_dimensions(struct ipu_image_convert_ctx
*ctx
,
810 struct ipu_image_convert_image
*image
)
812 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
813 struct ipu_image_convert_priv
*priv
= chan
->priv
;
816 for (i
= 0; i
< ctx
->num_tiles
; i
++) {
817 struct ipu_image_tile
*tile
;
818 const unsigned int row
= i
/ image
->num_cols
;
819 const unsigned int col
= i
% image
->num_cols
;
821 if (image
->type
== IMAGE_CONVERT_OUT
)
822 tile
= &image
->tile
[ctx
->out_tile_map
[i
]];
824 tile
= &image
->tile
[i
];
826 tile
->size
= ((tile
->height
* image
->fmt
->bpp
) >> 3) *
829 if (image
->fmt
->planar
) {
830 tile
->stride
= tile
->width
;
831 tile
->rot_stride
= tile
->height
;
834 (image
->fmt
->bpp
* tile
->width
) >> 3;
836 (image
->fmt
->bpp
* tile
->height
) >> 3;
839 dev_dbg(priv
->ipu
->dev
,
840 "task %u: ctx %p: %s@[%u,%u]: %ux%u@%u,%u\n",
842 image
->type
== IMAGE_CONVERT_IN
? "Input" : "Output",
844 tile
->width
, tile
->height
, tile
->left
, tile
->top
);
849 * Use the rotation transformation to find the tile coordinates
850 * (row, col) of a tile in the destination frame that corresponds
851 * to the given tile coordinates of a source frame. The destination
852 * coordinate is then converted to a tile index.
854 static int transform_tile_index(struct ipu_image_convert_ctx
*ctx
,
855 int src_row
, int src_col
)
857 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
858 struct ipu_image_convert_priv
*priv
= chan
->priv
;
859 struct ipu_image_convert_image
*s_image
= &ctx
->in
;
860 struct ipu_image_convert_image
*d_image
= &ctx
->out
;
861 int dst_row
, dst_col
;
863 /* with no rotation it's a 1:1 mapping */
864 if (ctx
->rot_mode
== IPU_ROTATE_NONE
)
865 return src_row
* s_image
->num_cols
+ src_col
;
868 * before doing the transform, first we have to translate
869 * source row,col for an origin in the center of s_image
871 src_row
= src_row
* 2 - (s_image
->num_rows
- 1);
872 src_col
= src_col
* 2 - (s_image
->num_cols
- 1);
874 /* do the rotation transform */
875 if (ctx
->rot_mode
& IPU_ROT_BIT_90
) {
884 if (ctx
->rot_mode
& IPU_ROT_BIT_HFLIP
)
886 if (ctx
->rot_mode
& IPU_ROT_BIT_VFLIP
)
889 dev_dbg(priv
->ipu
->dev
, "task %u: ctx %p: [%d,%d] --> [%d,%d]\n",
890 chan
->ic_task
, ctx
, src_col
, src_row
, dst_col
, dst_row
);
893 * finally translate dest row,col using an origin in upper
896 dst_row
+= d_image
->num_rows
- 1;
897 dst_col
+= d_image
->num_cols
- 1;
901 return dst_row
* d_image
->num_cols
+ dst_col
;
905 * Fill the out_tile_map[] with transformed destination tile indeces.
907 static void calc_out_tile_map(struct ipu_image_convert_ctx
*ctx
)
909 struct ipu_image_convert_image
*s_image
= &ctx
->in
;
910 unsigned int row
, col
, tile
= 0;
912 for (row
= 0; row
< s_image
->num_rows
; row
++) {
913 for (col
= 0; col
< s_image
->num_cols
; col
++) {
914 ctx
->out_tile_map
[tile
] =
915 transform_tile_index(ctx
, row
, col
);
921 static int calc_tile_offsets_planar(struct ipu_image_convert_ctx
*ctx
,
922 struct ipu_image_convert_image
*image
)
924 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
925 struct ipu_image_convert_priv
*priv
= chan
->priv
;
926 const struct ipu_image_pixfmt
*fmt
= image
->fmt
;
927 unsigned int row
, col
, tile
= 0;
928 u32 H
, top
, y_stride
, uv_stride
;
929 u32 uv_row_off
, uv_col_off
, uv_off
, u_off
, v_off
, tmp
;
930 u32 y_row_off
, y_col_off
, y_off
;
933 /* setup some convenience vars */
934 H
= image
->base
.pix
.height
;
936 y_stride
= image
->stride
;
937 uv_stride
= y_stride
/ fmt
->uv_width_dec
;
941 y_size
= H
* y_stride
;
942 uv_size
= y_size
/ (fmt
->uv_width_dec
* fmt
->uv_height_dec
);
944 for (row
= 0; row
< image
->num_rows
; row
++) {
945 top
= image
->tile
[tile
].top
;
946 y_row_off
= top
* y_stride
;
947 uv_row_off
= (top
* uv_stride
) / fmt
->uv_height_dec
;
949 for (col
= 0; col
< image
->num_cols
; col
++) {
950 y_col_off
= image
->tile
[tile
].left
;
951 uv_col_off
= y_col_off
/ fmt
->uv_width_dec
;
955 y_off
= y_row_off
+ y_col_off
;
956 uv_off
= uv_row_off
+ uv_col_off
;
958 u_off
= y_size
- y_off
+ uv_off
;
959 v_off
= (fmt
->uv_packed
) ? 0 : u_off
+ uv_size
;
960 if (fmt
->uv_swapped
) {
966 image
->tile
[tile
].offset
= y_off
;
967 image
->tile
[tile
].u_off
= u_off
;
968 image
->tile
[tile
++].v_off
= v_off
;
970 if ((y_off
& 0x7) || (u_off
& 0x7) || (v_off
& 0x7)) {
971 dev_err(priv
->ipu
->dev
,
972 "task %u: ctx %p: %s@[%d,%d]: "
973 "y_off %08x, u_off %08x, v_off %08x\n",
975 image
->type
== IMAGE_CONVERT_IN
?
976 "Input" : "Output", row
, col
,
977 y_off
, u_off
, v_off
);
986 static int calc_tile_offsets_packed(struct ipu_image_convert_ctx
*ctx
,
987 struct ipu_image_convert_image
*image
)
989 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
990 struct ipu_image_convert_priv
*priv
= chan
->priv
;
991 const struct ipu_image_pixfmt
*fmt
= image
->fmt
;
992 unsigned int row
, col
, tile
= 0;
993 u32 bpp
, stride
, offset
;
994 u32 row_off
, col_off
;
996 /* setup some convenience vars */
997 stride
= image
->stride
;
1000 for (row
= 0; row
< image
->num_rows
; row
++) {
1001 row_off
= image
->tile
[tile
].top
* stride
;
1003 for (col
= 0; col
< image
->num_cols
; col
++) {
1004 col_off
= (image
->tile
[tile
].left
* bpp
) >> 3;
1006 offset
= row_off
+ col_off
;
1008 image
->tile
[tile
].offset
= offset
;
1009 image
->tile
[tile
].u_off
= 0;
1010 image
->tile
[tile
++].v_off
= 0;
1013 dev_err(priv
->ipu
->dev
,
1014 "task %u: ctx %p: %s@[%d,%d]: "
1017 image
->type
== IMAGE_CONVERT_IN
?
1018 "Input" : "Output", row
, col
,
1028 static int calc_tile_offsets(struct ipu_image_convert_ctx
*ctx
,
1029 struct ipu_image_convert_image
*image
)
1031 if (image
->fmt
->planar
)
1032 return calc_tile_offsets_planar(ctx
, image
);
1034 return calc_tile_offsets_packed(ctx
, image
);
1038 * Calculate the resizing ratio for the IC main processing section given input
1039 * size, fixed downsizing coefficient, and output size.
1040 * Either round to closest for the next tile's first pixel to minimize seams
1041 * and distortion (for all but right column / bottom row), or round down to
1042 * avoid sampling beyond the edges of the input image for this tile's last
1044 * Returns the resizing coefficient, resizing ratio is 8192.0 / resize_coeff.
1046 static u32
calc_resize_coeff(u32 input_size
, u32 downsize_coeff
,
1047 u32 output_size
, bool allow_overshoot
)
1049 u32 downsized
= input_size
>> downsize_coeff
;
1051 if (allow_overshoot
)
1052 return DIV_ROUND_CLOSEST(8192 * downsized
, output_size
);
1054 return 8192 * (downsized
- 1) / (output_size
- 1);
1058 * Slightly modify resize coefficients per tile to hide the bilinear
1059 * interpolator reset at tile borders, shifting the right / bottom edge
1060 * by up to a half input pixel. This removes noticeable seams between
1061 * tiles at higher upscaling factors.
1063 static void calc_tile_resize_coefficients(struct ipu_image_convert_ctx
*ctx
)
1065 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1066 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1067 struct ipu_image_tile
*in_tile
, *out_tile
;
1068 unsigned int col
, row
, tile_idx
;
1069 unsigned int last_output
;
1071 for (col
= 0; col
< ctx
->in
.num_cols
; col
++) {
1072 bool closest
= (col
< ctx
->in
.num_cols
- 1) &&
1073 !(ctx
->rot_mode
& IPU_ROT_BIT_HFLIP
);
1078 in_tile
= &ctx
->in
.tile
[tile_idx
];
1079 out_tile
= &ctx
->out
.tile
[ctx
->out_tile_map
[tile_idx
]];
1081 if (ipu_rot_mode_is_irt(ctx
->rot_mode
))
1082 resized_width
= out_tile
->height
;
1084 resized_width
= out_tile
->width
;
1086 resize_coeff_h
= calc_resize_coeff(in_tile
->width
,
1087 ctx
->downsize_coeff_h
,
1088 resized_width
, closest
);
1090 dev_dbg(priv
->ipu
->dev
, "%s: column %u hscale: *8192/%u\n",
1091 __func__
, col
, resize_coeff_h
);
1094 for (row
= 0; row
< ctx
->in
.num_rows
; row
++) {
1095 tile_idx
= row
* ctx
->in
.num_cols
+ col
;
1096 in_tile
= &ctx
->in
.tile
[tile_idx
];
1097 out_tile
= &ctx
->out
.tile
[ctx
->out_tile_map
[tile_idx
]];
1100 * With the horizontal scaling factor known, round up
1101 * resized width (output width or height) to burst size.
1103 if (ipu_rot_mode_is_irt(ctx
->rot_mode
))
1104 out_tile
->height
= round_up(resized_width
, 8);
1106 out_tile
->width
= round_up(resized_width
, 8);
1109 * Calculate input width from the last accessed input
1110 * pixel given resized width and scaling coefficients.
1111 * Round up to burst size.
1113 last_output
= round_up(resized_width
, 8) - 1;
1116 in_tile
->width
= round_up(
1117 (DIV_ROUND_UP(last_output
* resize_coeff_h
,
1119 << ctx
->downsize_coeff_h
, 8);
1122 ctx
->resize_coeffs_h
[col
] = resize_coeff_h
;
1125 for (row
= 0; row
< ctx
->in
.num_rows
; row
++) {
1126 bool closest
= (row
< ctx
->in
.num_rows
- 1) &&
1127 !(ctx
->rot_mode
& IPU_ROT_BIT_VFLIP
);
1131 tile_idx
= row
* ctx
->in
.num_cols
;
1132 in_tile
= &ctx
->in
.tile
[tile_idx
];
1133 out_tile
= &ctx
->out
.tile
[ctx
->out_tile_map
[tile_idx
]];
1135 if (ipu_rot_mode_is_irt(ctx
->rot_mode
))
1136 resized_height
= out_tile
->width
;
1138 resized_height
= out_tile
->height
;
1140 resize_coeff_v
= calc_resize_coeff(in_tile
->height
,
1141 ctx
->downsize_coeff_v
,
1142 resized_height
, closest
);
1144 dev_dbg(priv
->ipu
->dev
, "%s: row %u vscale: *8192/%u\n",
1145 __func__
, row
, resize_coeff_v
);
1147 for (col
= 0; col
< ctx
->in
.num_cols
; col
++) {
1148 tile_idx
= row
* ctx
->in
.num_cols
+ col
;
1149 in_tile
= &ctx
->in
.tile
[tile_idx
];
1150 out_tile
= &ctx
->out
.tile
[ctx
->out_tile_map
[tile_idx
]];
1153 * With the vertical scaling factor known, round up
1154 * resized height (output width or height) to IDMAC
1157 if (ipu_rot_mode_is_irt(ctx
->rot_mode
))
1158 out_tile
->width
= round_up(resized_height
, 2);
1160 out_tile
->height
= round_up(resized_height
, 2);
1163 * Calculate input width from the last accessed input
1164 * pixel given resized height and scaling coefficients.
1165 * Align to IDMAC restrictions.
1167 last_output
= round_up(resized_height
, 2) - 1;
1170 in_tile
->height
= round_up(
1171 (DIV_ROUND_UP(last_output
* resize_coeff_v
,
1173 << ctx
->downsize_coeff_v
, 2);
1176 ctx
->resize_coeffs_v
[row
] = resize_coeff_v
;
1181 * return the number of runs in given queue (pending_q or done_q)
1182 * for this context. hold irqlock when calling.
1184 static int get_run_count(struct ipu_image_convert_ctx
*ctx
,
1185 struct list_head
*q
)
1187 struct ipu_image_convert_run
*run
;
1190 lockdep_assert_held(&ctx
->chan
->irqlock
);
1192 list_for_each_entry(run
, q
, list
) {
1193 if (run
->ctx
== ctx
)
1200 static void convert_stop(struct ipu_image_convert_run
*run
)
1202 struct ipu_image_convert_ctx
*ctx
= run
->ctx
;
1203 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1204 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1206 dev_dbg(priv
->ipu
->dev
, "%s: task %u: stopping ctx %p run %p\n",
1207 __func__
, chan
->ic_task
, ctx
, run
);
1209 /* disable IC tasks and the channels */
1210 ipu_ic_task_disable(chan
->ic
);
1211 ipu_idmac_disable_channel(chan
->in_chan
);
1212 ipu_idmac_disable_channel(chan
->out_chan
);
1214 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1215 ipu_idmac_disable_channel(chan
->rotation_in_chan
);
1216 ipu_idmac_disable_channel(chan
->rotation_out_chan
);
1217 ipu_idmac_unlink(chan
->out_chan
, chan
->rotation_in_chan
);
1220 ipu_ic_disable(chan
->ic
);
1223 static void init_idmac_channel(struct ipu_image_convert_ctx
*ctx
,
1224 struct ipuv3_channel
*channel
,
1225 struct ipu_image_convert_image
*image
,
1226 enum ipu_rotate_mode rot_mode
,
1227 bool rot_swap_width_height
,
1230 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1231 unsigned int burst_size
;
1232 u32 width
, height
, stride
;
1233 dma_addr_t addr0
, addr1
= 0;
1234 struct ipu_image tile_image
;
1235 unsigned int tile_idx
[2];
1237 if (image
->type
== IMAGE_CONVERT_OUT
) {
1238 tile_idx
[0] = ctx
->out_tile_map
[tile
];
1239 tile_idx
[1] = ctx
->out_tile_map
[1];
1245 if (rot_swap_width_height
) {
1246 width
= image
->tile
[tile_idx
[0]].height
;
1247 height
= image
->tile
[tile_idx
[0]].width
;
1248 stride
= image
->tile
[tile_idx
[0]].rot_stride
;
1249 addr0
= ctx
->rot_intermediate
[0].phys
;
1250 if (ctx
->double_buffering
)
1251 addr1
= ctx
->rot_intermediate
[1].phys
;
1253 width
= image
->tile
[tile_idx
[0]].width
;
1254 height
= image
->tile
[tile_idx
[0]].height
;
1255 stride
= image
->stride
;
1256 addr0
= image
->base
.phys0
+
1257 image
->tile
[tile_idx
[0]].offset
;
1258 if (ctx
->double_buffering
)
1259 addr1
= image
->base
.phys0
+
1260 image
->tile
[tile_idx
[1]].offset
;
1263 ipu_cpmem_zero(channel
);
1265 memset(&tile_image
, 0, sizeof(tile_image
));
1266 tile_image
.pix
.width
= tile_image
.rect
.width
= width
;
1267 tile_image
.pix
.height
= tile_image
.rect
.height
= height
;
1268 tile_image
.pix
.bytesperline
= stride
;
1269 tile_image
.pix
.pixelformat
= image
->fmt
->fourcc
;
1270 tile_image
.phys0
= addr0
;
1271 tile_image
.phys1
= addr1
;
1272 if (image
->fmt
->planar
&& !rot_swap_width_height
) {
1273 tile_image
.u_offset
= image
->tile
[tile_idx
[0]].u_off
;
1274 tile_image
.v_offset
= image
->tile
[tile_idx
[0]].v_off
;
1277 ipu_cpmem_set_image(channel
, &tile_image
);
1280 ipu_cpmem_set_rotation(channel
, rot_mode
);
1282 if (channel
== chan
->rotation_in_chan
||
1283 channel
== chan
->rotation_out_chan
) {
1285 ipu_cpmem_set_block_mode(channel
);
1287 burst_size
= (width
% 16) ? 8 : 16;
1289 ipu_cpmem_set_burstsize(channel
, burst_size
);
1291 ipu_ic_task_idma_init(chan
->ic
, channel
, width
, height
,
1292 burst_size
, rot_mode
);
1295 * Setting a non-zero AXI ID collides with the PRG AXI snooping, so
1296 * only do this when there is no PRG present.
1298 if (!channel
->ipu
->prg_priv
)
1299 ipu_cpmem_set_axi_id(channel
, 1);
1301 ipu_idmac_set_double_buffer(channel
, ctx
->double_buffering
);
1304 static int convert_start(struct ipu_image_convert_run
*run
, unsigned int tile
)
1306 struct ipu_image_convert_ctx
*ctx
= run
->ctx
;
1307 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1308 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1309 struct ipu_image_convert_image
*s_image
= &ctx
->in
;
1310 struct ipu_image_convert_image
*d_image
= &ctx
->out
;
1311 enum ipu_color_space src_cs
, dest_cs
;
1312 unsigned int dst_tile
= ctx
->out_tile_map
[tile
];
1313 unsigned int dest_width
, dest_height
;
1314 unsigned int col
, row
;
1318 dev_dbg(priv
->ipu
->dev
, "%s: task %u: starting ctx %p run %p tile %u -> %u\n",
1319 __func__
, chan
->ic_task
, ctx
, run
, tile
, dst_tile
);
1321 src_cs
= ipu_pixelformat_to_colorspace(s_image
->fmt
->fourcc
);
1322 dest_cs
= ipu_pixelformat_to_colorspace(d_image
->fmt
->fourcc
);
1324 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1325 /* swap width/height for resizer */
1326 dest_width
= d_image
->tile
[dst_tile
].height
;
1327 dest_height
= d_image
->tile
[dst_tile
].width
;
1329 dest_width
= d_image
->tile
[dst_tile
].width
;
1330 dest_height
= d_image
->tile
[dst_tile
].height
;
1333 row
= tile
/ s_image
->num_cols
;
1334 col
= tile
% s_image
->num_cols
;
1336 rsc
= (ctx
->downsize_coeff_v
<< 30) |
1337 (ctx
->resize_coeffs_v
[row
] << 16) |
1338 (ctx
->downsize_coeff_h
<< 14) |
1339 (ctx
->resize_coeffs_h
[col
]);
1341 dev_dbg(priv
->ipu
->dev
, "%s: %ux%u -> %ux%u (rsc = 0x%x)\n",
1342 __func__
, s_image
->tile
[tile
].width
,
1343 s_image
->tile
[tile
].height
, dest_width
, dest_height
, rsc
);
1345 /* setup the IC resizer and CSC */
1346 ret
= ipu_ic_task_init_rsc(chan
->ic
,
1347 s_image
->tile
[tile
].width
,
1348 s_image
->tile
[tile
].height
,
1354 dev_err(priv
->ipu
->dev
, "ipu_ic_task_init failed, %d\n", ret
);
1358 /* init the source MEM-->IC PP IDMAC channel */
1359 init_idmac_channel(ctx
, chan
->in_chan
, s_image
,
1360 IPU_ROTATE_NONE
, false, tile
);
1362 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1363 /* init the IC PP-->MEM IDMAC channel */
1364 init_idmac_channel(ctx
, chan
->out_chan
, d_image
,
1365 IPU_ROTATE_NONE
, true, tile
);
1367 /* init the MEM-->IC PP ROT IDMAC channel */
1368 init_idmac_channel(ctx
, chan
->rotation_in_chan
, d_image
,
1369 ctx
->rot_mode
, true, tile
);
1371 /* init the destination IC PP ROT-->MEM IDMAC channel */
1372 init_idmac_channel(ctx
, chan
->rotation_out_chan
, d_image
,
1373 IPU_ROTATE_NONE
, false, tile
);
1375 /* now link IC PP-->MEM to MEM-->IC PP ROT */
1376 ipu_idmac_link(chan
->out_chan
, chan
->rotation_in_chan
);
1378 /* init the destination IC PP-->MEM IDMAC channel */
1379 init_idmac_channel(ctx
, chan
->out_chan
, d_image
,
1380 ctx
->rot_mode
, false, tile
);
1384 ipu_ic_enable(chan
->ic
);
1386 /* set buffers ready */
1387 ipu_idmac_select_buffer(chan
->in_chan
, 0);
1388 ipu_idmac_select_buffer(chan
->out_chan
, 0);
1389 if (ipu_rot_mode_is_irt(ctx
->rot_mode
))
1390 ipu_idmac_select_buffer(chan
->rotation_out_chan
, 0);
1391 if (ctx
->double_buffering
) {
1392 ipu_idmac_select_buffer(chan
->in_chan
, 1);
1393 ipu_idmac_select_buffer(chan
->out_chan
, 1);
1394 if (ipu_rot_mode_is_irt(ctx
->rot_mode
))
1395 ipu_idmac_select_buffer(chan
->rotation_out_chan
, 1);
1398 /* enable the channels! */
1399 ipu_idmac_enable_channel(chan
->in_chan
);
1400 ipu_idmac_enable_channel(chan
->out_chan
);
1401 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1402 ipu_idmac_enable_channel(chan
->rotation_in_chan
);
1403 ipu_idmac_enable_channel(chan
->rotation_out_chan
);
1406 ipu_ic_task_enable(chan
->ic
);
1408 ipu_cpmem_dump(chan
->in_chan
);
1409 ipu_cpmem_dump(chan
->out_chan
);
1410 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1411 ipu_cpmem_dump(chan
->rotation_in_chan
);
1412 ipu_cpmem_dump(chan
->rotation_out_chan
);
1415 ipu_dump(priv
->ipu
);
1420 /* hold irqlock when calling */
1421 static int do_run(struct ipu_image_convert_run
*run
)
1423 struct ipu_image_convert_ctx
*ctx
= run
->ctx
;
1424 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1426 lockdep_assert_held(&chan
->irqlock
);
1428 ctx
->in
.base
.phys0
= run
->in_phys
;
1429 ctx
->out
.base
.phys0
= run
->out_phys
;
1431 ctx
->cur_buf_num
= 0;
1434 /* remove run from pending_q and set as current */
1435 list_del(&run
->list
);
1436 chan
->current_run
= run
;
1438 return convert_start(run
, 0);
1441 /* hold irqlock when calling */
1442 static void run_next(struct ipu_image_convert_chan
*chan
)
1444 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1445 struct ipu_image_convert_run
*run
, *tmp
;
1448 lockdep_assert_held(&chan
->irqlock
);
1450 list_for_each_entry_safe(run
, tmp
, &chan
->pending_q
, list
) {
1451 /* skip contexts that are aborting */
1452 if (run
->ctx
->aborting
) {
1453 dev_dbg(priv
->ipu
->dev
,
1454 "%s: task %u: skipping aborting ctx %p run %p\n",
1455 __func__
, chan
->ic_task
, run
->ctx
, run
);
1464 * something went wrong with start, add the run
1465 * to done q and continue to the next run in the
1469 list_add_tail(&run
->list
, &chan
->done_q
);
1470 chan
->current_run
= NULL
;
1474 static void empty_done_q(struct ipu_image_convert_chan
*chan
)
1476 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1477 struct ipu_image_convert_run
*run
;
1478 unsigned long flags
;
1480 spin_lock_irqsave(&chan
->irqlock
, flags
);
1482 while (!list_empty(&chan
->done_q
)) {
1483 run
= list_entry(chan
->done_q
.next
,
1484 struct ipu_image_convert_run
,
1487 list_del(&run
->list
);
1489 dev_dbg(priv
->ipu
->dev
,
1490 "%s: task %u: completing ctx %p run %p with %d\n",
1491 __func__
, chan
->ic_task
, run
->ctx
, run
, run
->status
);
1493 /* call the completion callback and free the run */
1494 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1495 run
->ctx
->complete(run
, run
->ctx
->complete_context
);
1496 spin_lock_irqsave(&chan
->irqlock
, flags
);
1499 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1503 * the bottom half thread clears out the done_q, calling the
1504 * completion handler for each.
1506 static irqreturn_t
do_bh(int irq
, void *dev_id
)
1508 struct ipu_image_convert_chan
*chan
= dev_id
;
1509 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1510 struct ipu_image_convert_ctx
*ctx
;
1511 unsigned long flags
;
1513 dev_dbg(priv
->ipu
->dev
, "%s: task %u: enter\n", __func__
,
1518 spin_lock_irqsave(&chan
->irqlock
, flags
);
1521 * the done_q is cleared out, signal any contexts
1522 * that are aborting that abort can complete.
1524 list_for_each_entry(ctx
, &chan
->ctx_list
, list
) {
1525 if (ctx
->aborting
) {
1526 dev_dbg(priv
->ipu
->dev
,
1527 "%s: task %u: signaling abort for ctx %p\n",
1528 __func__
, chan
->ic_task
, ctx
);
1529 complete_all(&ctx
->aborted
);
1533 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1535 dev_dbg(priv
->ipu
->dev
, "%s: task %u: exit\n", __func__
,
1541 static bool ic_settings_changed(struct ipu_image_convert_ctx
*ctx
)
1543 unsigned int cur_tile
= ctx
->next_tile
- 1;
1544 unsigned int next_tile
= ctx
->next_tile
;
1546 if (ctx
->resize_coeffs_h
[cur_tile
% ctx
->in
.num_cols
] !=
1547 ctx
->resize_coeffs_h
[next_tile
% ctx
->in
.num_cols
] ||
1548 ctx
->resize_coeffs_v
[cur_tile
/ ctx
->in
.num_cols
] !=
1549 ctx
->resize_coeffs_v
[next_tile
/ ctx
->in
.num_cols
] ||
1550 ctx
->in
.tile
[cur_tile
].width
!= ctx
->in
.tile
[next_tile
].width
||
1551 ctx
->in
.tile
[cur_tile
].height
!= ctx
->in
.tile
[next_tile
].height
||
1552 ctx
->out
.tile
[cur_tile
].width
!= ctx
->out
.tile
[next_tile
].width
||
1553 ctx
->out
.tile
[cur_tile
].height
!= ctx
->out
.tile
[next_tile
].height
)
1559 /* hold irqlock when calling */
1560 static irqreturn_t
do_irq(struct ipu_image_convert_run
*run
)
1562 struct ipu_image_convert_ctx
*ctx
= run
->ctx
;
1563 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1564 struct ipu_image_tile
*src_tile
, *dst_tile
;
1565 struct ipu_image_convert_image
*s_image
= &ctx
->in
;
1566 struct ipu_image_convert_image
*d_image
= &ctx
->out
;
1567 struct ipuv3_channel
*outch
;
1568 unsigned int dst_idx
;
1570 lockdep_assert_held(&chan
->irqlock
);
1572 outch
= ipu_rot_mode_is_irt(ctx
->rot_mode
) ?
1573 chan
->rotation_out_chan
: chan
->out_chan
;
1576 * It is difficult to stop the channel DMA before the channels
1577 * enter the paused state. Without double-buffering the channels
1578 * are always in a paused state when the EOF irq occurs, so it
1579 * is safe to stop the channels now. For double-buffering we
1580 * just ignore the abort until the operation completes, when it
1581 * is safe to shut down.
1583 if (ctx
->aborting
&& !ctx
->double_buffering
) {
1589 if (ctx
->next_tile
== ctx
->num_tiles
) {
1591 * the conversion is complete
1599 * not done, place the next tile buffers.
1601 if (!ctx
->double_buffering
) {
1602 if (ic_settings_changed(ctx
)) {
1604 convert_start(run
, ctx
->next_tile
);
1606 src_tile
= &s_image
->tile
[ctx
->next_tile
];
1607 dst_idx
= ctx
->out_tile_map
[ctx
->next_tile
];
1608 dst_tile
= &d_image
->tile
[dst_idx
];
1610 ipu_cpmem_set_buffer(chan
->in_chan
, 0,
1611 s_image
->base
.phys0
+
1613 ipu_cpmem_set_buffer(outch
, 0,
1614 d_image
->base
.phys0
+
1616 if (s_image
->fmt
->planar
)
1617 ipu_cpmem_set_uv_offset(chan
->in_chan
,
1620 if (d_image
->fmt
->planar
)
1621 ipu_cpmem_set_uv_offset(outch
,
1625 ipu_idmac_select_buffer(chan
->in_chan
, 0);
1626 ipu_idmac_select_buffer(outch
, 0);
1628 } else if (ctx
->next_tile
< ctx
->num_tiles
- 1) {
1630 src_tile
= &s_image
->tile
[ctx
->next_tile
+ 1];
1631 dst_idx
= ctx
->out_tile_map
[ctx
->next_tile
+ 1];
1632 dst_tile
= &d_image
->tile
[dst_idx
];
1634 ipu_cpmem_set_buffer(chan
->in_chan
, ctx
->cur_buf_num
,
1635 s_image
->base
.phys0
+ src_tile
->offset
);
1636 ipu_cpmem_set_buffer(outch
, ctx
->cur_buf_num
,
1637 d_image
->base
.phys0
+ dst_tile
->offset
);
1639 ipu_idmac_select_buffer(chan
->in_chan
, ctx
->cur_buf_num
);
1640 ipu_idmac_select_buffer(outch
, ctx
->cur_buf_num
);
1642 ctx
->cur_buf_num
^= 1;
1648 list_add_tail(&run
->list
, &chan
->done_q
);
1649 chan
->current_run
= NULL
;
1651 return IRQ_WAKE_THREAD
;
1654 static irqreturn_t
norotate_irq(int irq
, void *data
)
1656 struct ipu_image_convert_chan
*chan
= data
;
1657 struct ipu_image_convert_ctx
*ctx
;
1658 struct ipu_image_convert_run
*run
;
1659 unsigned long flags
;
1662 spin_lock_irqsave(&chan
->irqlock
, flags
);
1664 /* get current run and its context */
1665 run
= chan
->current_run
;
1673 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1674 /* this is a rotation operation, just ignore */
1675 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1681 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1685 static irqreturn_t
rotate_irq(int irq
, void *data
)
1687 struct ipu_image_convert_chan
*chan
= data
;
1688 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1689 struct ipu_image_convert_ctx
*ctx
;
1690 struct ipu_image_convert_run
*run
;
1691 unsigned long flags
;
1694 spin_lock_irqsave(&chan
->irqlock
, flags
);
1696 /* get current run and its context */
1697 run
= chan
->current_run
;
1705 if (!ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
1706 /* this was NOT a rotation operation, shouldn't happen */
1707 dev_err(priv
->ipu
->dev
, "Unexpected rotation interrupt\n");
1708 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1714 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1719 * try to force the completion of runs for this ctx. Called when
1720 * abort wait times out in ipu_image_convert_abort().
1722 static void force_abort(struct ipu_image_convert_ctx
*ctx
)
1724 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
1725 struct ipu_image_convert_run
*run
;
1726 unsigned long flags
;
1728 spin_lock_irqsave(&chan
->irqlock
, flags
);
1730 run
= chan
->current_run
;
1731 if (run
&& run
->ctx
== ctx
) {
1734 list_add_tail(&run
->list
, &chan
->done_q
);
1735 chan
->current_run
= NULL
;
1739 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
1744 static void release_ipu_resources(struct ipu_image_convert_chan
*chan
)
1746 if (chan
->out_eof_irq
>= 0)
1747 free_irq(chan
->out_eof_irq
, chan
);
1748 if (chan
->rot_out_eof_irq
>= 0)
1749 free_irq(chan
->rot_out_eof_irq
, chan
);
1751 if (!IS_ERR_OR_NULL(chan
->in_chan
))
1752 ipu_idmac_put(chan
->in_chan
);
1753 if (!IS_ERR_OR_NULL(chan
->out_chan
))
1754 ipu_idmac_put(chan
->out_chan
);
1755 if (!IS_ERR_OR_NULL(chan
->rotation_in_chan
))
1756 ipu_idmac_put(chan
->rotation_in_chan
);
1757 if (!IS_ERR_OR_NULL(chan
->rotation_out_chan
))
1758 ipu_idmac_put(chan
->rotation_out_chan
);
1759 if (!IS_ERR_OR_NULL(chan
->ic
))
1760 ipu_ic_put(chan
->ic
);
1762 chan
->in_chan
= chan
->out_chan
= chan
->rotation_in_chan
=
1763 chan
->rotation_out_chan
= NULL
;
1764 chan
->out_eof_irq
= chan
->rot_out_eof_irq
= -1;
1767 static int get_ipu_resources(struct ipu_image_convert_chan
*chan
)
1769 const struct ipu_image_convert_dma_chan
*dma
= chan
->dma_ch
;
1770 struct ipu_image_convert_priv
*priv
= chan
->priv
;
1774 chan
->ic
= ipu_ic_get(priv
->ipu
, chan
->ic_task
);
1775 if (IS_ERR(chan
->ic
)) {
1776 dev_err(priv
->ipu
->dev
, "could not acquire IC\n");
1777 ret
= PTR_ERR(chan
->ic
);
1781 /* get IDMAC channels */
1782 chan
->in_chan
= ipu_idmac_get(priv
->ipu
, dma
->in
);
1783 chan
->out_chan
= ipu_idmac_get(priv
->ipu
, dma
->out
);
1784 if (IS_ERR(chan
->in_chan
) || IS_ERR(chan
->out_chan
)) {
1785 dev_err(priv
->ipu
->dev
, "could not acquire idmac channels\n");
1790 chan
->rotation_in_chan
= ipu_idmac_get(priv
->ipu
, dma
->rot_in
);
1791 chan
->rotation_out_chan
= ipu_idmac_get(priv
->ipu
, dma
->rot_out
);
1792 if (IS_ERR(chan
->rotation_in_chan
) || IS_ERR(chan
->rotation_out_chan
)) {
1793 dev_err(priv
->ipu
->dev
,
1794 "could not acquire idmac rotation channels\n");
1799 /* acquire the EOF interrupts */
1800 chan
->out_eof_irq
= ipu_idmac_channel_irq(priv
->ipu
,
1804 ret
= request_threaded_irq(chan
->out_eof_irq
, norotate_irq
, do_bh
,
1807 dev_err(priv
->ipu
->dev
, "could not acquire irq %d\n",
1809 chan
->out_eof_irq
= -1;
1813 chan
->rot_out_eof_irq
= ipu_idmac_channel_irq(priv
->ipu
,
1814 chan
->rotation_out_chan
,
1817 ret
= request_threaded_irq(chan
->rot_out_eof_irq
, rotate_irq
, do_bh
,
1820 dev_err(priv
->ipu
->dev
, "could not acquire irq %d\n",
1821 chan
->rot_out_eof_irq
);
1822 chan
->rot_out_eof_irq
= -1;
1828 release_ipu_resources(chan
);
1832 static int fill_image(struct ipu_image_convert_ctx
*ctx
,
1833 struct ipu_image_convert_image
*ic_image
,
1834 struct ipu_image
*image
,
1835 enum ipu_image_convert_type type
)
1837 struct ipu_image_convert_priv
*priv
= ctx
->chan
->priv
;
1839 ic_image
->base
= *image
;
1840 ic_image
->type
= type
;
1842 ic_image
->fmt
= get_format(image
->pix
.pixelformat
);
1843 if (!ic_image
->fmt
) {
1844 dev_err(priv
->ipu
->dev
, "pixelformat not supported for %s\n",
1845 type
== IMAGE_CONVERT_OUT
? "Output" : "Input");
1849 if (ic_image
->fmt
->planar
)
1850 ic_image
->stride
= ic_image
->base
.pix
.width
;
1852 ic_image
->stride
= ic_image
->base
.pix
.bytesperline
;
1857 /* borrowed from drivers/media/v4l2-core/v4l2-common.c */
1858 static unsigned int clamp_align(unsigned int x
, unsigned int min
,
1859 unsigned int max
, unsigned int align
)
1861 /* Bits that must be zero to be aligned */
1862 unsigned int mask
= ~((1 << align
) - 1);
1864 /* Clamp to aligned min and max */
1865 x
= clamp(x
, (min
+ ~mask
) & mask
, max
& mask
);
1867 /* Round to nearest aligned value */
1869 x
= (x
+ (1 << (align
- 1))) & mask
;
1874 /* Adjusts input/output images to IPU restrictions */
1875 void ipu_image_convert_adjust(struct ipu_image
*in
, struct ipu_image
*out
,
1876 enum ipu_rotate_mode rot_mode
)
1878 const struct ipu_image_pixfmt
*infmt
, *outfmt
;
1879 u32 w_align
, h_align
;
1881 infmt
= get_format(in
->pix
.pixelformat
);
1882 outfmt
= get_format(out
->pix
.pixelformat
);
1884 /* set some default pixel formats if needed */
1886 in
->pix
.pixelformat
= V4L2_PIX_FMT_RGB24
;
1887 infmt
= get_format(V4L2_PIX_FMT_RGB24
);
1890 out
->pix
.pixelformat
= V4L2_PIX_FMT_RGB24
;
1891 outfmt
= get_format(V4L2_PIX_FMT_RGB24
);
1894 /* image converter does not handle fields */
1895 in
->pix
.field
= out
->pix
.field
= V4L2_FIELD_NONE
;
1897 /* resizer cannot downsize more than 4:1 */
1898 if (ipu_rot_mode_is_irt(rot_mode
)) {
1899 out
->pix
.height
= max_t(__u32
, out
->pix
.height
,
1901 out
->pix
.width
= max_t(__u32
, out
->pix
.width
,
1902 in
->pix
.height
/ 4);
1904 out
->pix
.width
= max_t(__u32
, out
->pix
.width
,
1906 out
->pix
.height
= max_t(__u32
, out
->pix
.height
,
1907 in
->pix
.height
/ 4);
1910 /* align input width/height */
1911 w_align
= ilog2(tile_width_align(IMAGE_CONVERT_IN
, infmt
, rot_mode
));
1912 h_align
= ilog2(tile_height_align(IMAGE_CONVERT_IN
, infmt
, rot_mode
));
1913 in
->pix
.width
= clamp_align(in
->pix
.width
, MIN_W
, MAX_W
, w_align
);
1914 in
->pix
.height
= clamp_align(in
->pix
.height
, MIN_H
, MAX_H
, h_align
);
1916 /* align output width/height */
1917 w_align
= ilog2(tile_width_align(IMAGE_CONVERT_OUT
, outfmt
, rot_mode
));
1918 h_align
= ilog2(tile_height_align(IMAGE_CONVERT_OUT
, outfmt
, rot_mode
));
1919 out
->pix
.width
= clamp_align(out
->pix
.width
, MIN_W
, MAX_W
, w_align
);
1920 out
->pix
.height
= clamp_align(out
->pix
.height
, MIN_H
, MAX_H
, h_align
);
1922 /* set input/output strides and image sizes */
1923 in
->pix
.bytesperline
= infmt
->planar
?
1924 clamp_align(in
->pix
.width
, 2 << w_align
, MAX_W
, w_align
) :
1925 clamp_align((in
->pix
.width
* infmt
->bpp
) >> 3,
1926 2 << w_align
, MAX_W
, w_align
);
1927 in
->pix
.sizeimage
= infmt
->planar
?
1928 (in
->pix
.height
* in
->pix
.bytesperline
* infmt
->bpp
) >> 3 :
1929 in
->pix
.height
* in
->pix
.bytesperline
;
1930 out
->pix
.bytesperline
= outfmt
->planar
? out
->pix
.width
:
1931 (out
->pix
.width
* outfmt
->bpp
) >> 3;
1932 out
->pix
.sizeimage
= outfmt
->planar
?
1933 (out
->pix
.height
* out
->pix
.bytesperline
* outfmt
->bpp
) >> 3 :
1934 out
->pix
.height
* out
->pix
.bytesperline
;
1936 EXPORT_SYMBOL_GPL(ipu_image_convert_adjust
);
1939 * this is used by ipu_image_convert_prepare() to verify set input and
1940 * output images are valid before starting the conversion. Clients can
1941 * also call it before calling ipu_image_convert_prepare().
1943 int ipu_image_convert_verify(struct ipu_image
*in
, struct ipu_image
*out
,
1944 enum ipu_rotate_mode rot_mode
)
1946 struct ipu_image testin
, testout
;
1951 ipu_image_convert_adjust(&testin
, &testout
, rot_mode
);
1953 if (testin
.pix
.width
!= in
->pix
.width
||
1954 testin
.pix
.height
!= in
->pix
.height
||
1955 testout
.pix
.width
!= out
->pix
.width
||
1956 testout
.pix
.height
!= out
->pix
.height
)
1961 EXPORT_SYMBOL_GPL(ipu_image_convert_verify
);
1964 * Call ipu_image_convert_prepare() to prepare for the conversion of
1965 * given images and rotation mode. Returns a new conversion context.
1967 struct ipu_image_convert_ctx
*
1968 ipu_image_convert_prepare(struct ipu_soc
*ipu
, enum ipu_ic_task ic_task
,
1969 struct ipu_image
*in
, struct ipu_image
*out
,
1970 enum ipu_rotate_mode rot_mode
,
1971 ipu_image_convert_cb_t complete
,
1972 void *complete_context
)
1974 struct ipu_image_convert_priv
*priv
= ipu
->image_convert_priv
;
1975 struct ipu_image_convert_image
*s_image
, *d_image
;
1976 struct ipu_image_convert_chan
*chan
;
1977 struct ipu_image_convert_ctx
*ctx
;
1978 unsigned long flags
;
1983 if (!in
|| !out
|| !complete
||
1984 (ic_task
!= IC_TASK_VIEWFINDER
&&
1985 ic_task
!= IC_TASK_POST_PROCESSOR
))
1986 return ERR_PTR(-EINVAL
);
1988 /* verify the in/out images before continuing */
1989 ret
= ipu_image_convert_verify(in
, out
, rot_mode
);
1991 dev_err(priv
->ipu
->dev
, "%s: in/out formats invalid\n",
1993 return ERR_PTR(ret
);
1996 chan
= &priv
->chan
[ic_task
];
1998 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
2000 return ERR_PTR(-ENOMEM
);
2002 dev_dbg(priv
->ipu
->dev
, "%s: task %u: ctx %p\n", __func__
,
2003 chan
->ic_task
, ctx
);
2006 init_completion(&ctx
->aborted
);
2009 d_image
= &ctx
->out
;
2011 /* set tiling and rotation */
2012 d_image
->num_rows
= num_stripes(out
->pix
.height
);
2013 d_image
->num_cols
= num_stripes(out
->pix
.width
);
2014 if (ipu_rot_mode_is_irt(rot_mode
)) {
2015 s_image
->num_rows
= d_image
->num_cols
;
2016 s_image
->num_cols
= d_image
->num_rows
;
2018 s_image
->num_rows
= d_image
->num_rows
;
2019 s_image
->num_cols
= d_image
->num_cols
;
2022 ctx
->num_tiles
= d_image
->num_cols
* d_image
->num_rows
;
2023 ctx
->rot_mode
= rot_mode
;
2025 ret
= fill_image(ctx
, s_image
, in
, IMAGE_CONVERT_IN
);
2028 ret
= fill_image(ctx
, d_image
, out
, IMAGE_CONVERT_OUT
);
2032 ret
= calc_image_resize_coefficients(ctx
, in
, out
);
2036 calc_out_tile_map(ctx
);
2038 find_seams(ctx
, s_image
, d_image
);
2040 calc_tile_dimensions(ctx
, s_image
);
2041 ret
= calc_tile_offsets(ctx
, s_image
);
2045 calc_tile_dimensions(ctx
, d_image
);
2046 ret
= calc_tile_offsets(ctx
, d_image
);
2050 calc_tile_resize_coefficients(ctx
);
2052 dump_format(ctx
, s_image
);
2053 dump_format(ctx
, d_image
);
2055 ctx
->complete
= complete
;
2056 ctx
->complete_context
= complete_context
;
2059 * Can we use double-buffering for this operation? If there is
2060 * only one tile (the whole image can be converted in a single
2061 * operation) there's no point in using double-buffering. Also,
2062 * the IPU's IDMAC channels allow only a single U and V plane
2063 * offset shared between both buffers, but these offsets change
2064 * for every tile, and therefore would have to be updated for
2065 * each buffer which is not possible. So double-buffering is
2066 * impossible when either the source or destination images are
2067 * a planar format (YUV420, YUV422P, etc.). Further, differently
2068 * sized tiles or different resizing coefficients per tile
2069 * prevent double-buffering as well.
2071 ctx
->double_buffering
= (ctx
->num_tiles
> 1 &&
2072 !s_image
->fmt
->planar
&&
2073 !d_image
->fmt
->planar
);
2074 for (i
= 1; i
< ctx
->num_tiles
; i
++) {
2075 if (ctx
->in
.tile
[i
].width
!= ctx
->in
.tile
[0].width
||
2076 ctx
->in
.tile
[i
].height
!= ctx
->in
.tile
[0].height
||
2077 ctx
->out
.tile
[i
].width
!= ctx
->out
.tile
[0].width
||
2078 ctx
->out
.tile
[i
].height
!= ctx
->out
.tile
[0].height
) {
2079 ctx
->double_buffering
= false;
2083 for (i
= 1; i
< ctx
->in
.num_cols
; i
++) {
2084 if (ctx
->resize_coeffs_h
[i
] != ctx
->resize_coeffs_h
[0]) {
2085 ctx
->double_buffering
= false;
2089 for (i
= 1; i
< ctx
->in
.num_rows
; i
++) {
2090 if (ctx
->resize_coeffs_v
[i
] != ctx
->resize_coeffs_v
[0]) {
2091 ctx
->double_buffering
= false;
2096 if (ipu_rot_mode_is_irt(ctx
->rot_mode
)) {
2097 unsigned long intermediate_size
= d_image
->tile
[0].size
;
2099 for (i
= 1; i
< ctx
->num_tiles
; i
++) {
2100 if (d_image
->tile
[i
].size
> intermediate_size
)
2101 intermediate_size
= d_image
->tile
[i
].size
;
2104 ret
= alloc_dma_buf(priv
, &ctx
->rot_intermediate
[0],
2108 if (ctx
->double_buffering
) {
2109 ret
= alloc_dma_buf(priv
,
2110 &ctx
->rot_intermediate
[1],
2113 goto out_free_dmabuf0
;
2117 spin_lock_irqsave(&chan
->irqlock
, flags
);
2119 get_res
= list_empty(&chan
->ctx_list
);
2121 list_add_tail(&ctx
->list
, &chan
->ctx_list
);
2123 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
2126 ret
= get_ipu_resources(chan
);
2128 goto out_free_dmabuf1
;
2134 free_dma_buf(priv
, &ctx
->rot_intermediate
[1]);
2135 spin_lock_irqsave(&chan
->irqlock
, flags
);
2136 list_del(&ctx
->list
);
2137 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
2139 free_dma_buf(priv
, &ctx
->rot_intermediate
[0]);
2142 return ERR_PTR(ret
);
2144 EXPORT_SYMBOL_GPL(ipu_image_convert_prepare
);
2147 * Carry out a single image conversion run. Only the physaddr's of the input
2148 * and output image buffers are needed. The conversion context must have
2149 * been created previously with ipu_image_convert_prepare().
2151 int ipu_image_convert_queue(struct ipu_image_convert_run
*run
)
2153 struct ipu_image_convert_chan
*chan
;
2154 struct ipu_image_convert_priv
*priv
;
2155 struct ipu_image_convert_ctx
*ctx
;
2156 unsigned long flags
;
2159 if (!run
|| !run
->ctx
|| !run
->in_phys
|| !run
->out_phys
)
2166 dev_dbg(priv
->ipu
->dev
, "%s: task %u: ctx %p run %p\n", __func__
,
2167 chan
->ic_task
, ctx
, run
);
2169 INIT_LIST_HEAD(&run
->list
);
2171 spin_lock_irqsave(&chan
->irqlock
, flags
);
2173 if (ctx
->aborting
) {
2178 list_add_tail(&run
->list
, &chan
->pending_q
);
2180 if (!chan
->current_run
) {
2183 chan
->current_run
= NULL
;
2186 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
2189 EXPORT_SYMBOL_GPL(ipu_image_convert_queue
);
2191 /* Abort any active or pending conversions for this context */
2192 static void __ipu_image_convert_abort(struct ipu_image_convert_ctx
*ctx
)
2194 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
2195 struct ipu_image_convert_priv
*priv
= chan
->priv
;
2196 struct ipu_image_convert_run
*run
, *active_run
, *tmp
;
2197 unsigned long flags
;
2200 spin_lock_irqsave(&chan
->irqlock
, flags
);
2202 /* move all remaining pending runs in this context to done_q */
2203 list_for_each_entry_safe(run
, tmp
, &chan
->pending_q
, list
) {
2204 if (run
->ctx
!= ctx
)
2207 list_move_tail(&run
->list
, &chan
->done_q
);
2210 run_count
= get_run_count(ctx
, &chan
->done_q
);
2211 active_run
= (chan
->current_run
&& chan
->current_run
->ctx
== ctx
) ?
2212 chan
->current_run
: NULL
;
2215 reinit_completion(&ctx
->aborted
);
2217 ctx
->aborting
= true;
2219 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
2221 if (!run_count
&& !active_run
) {
2222 dev_dbg(priv
->ipu
->dev
,
2223 "%s: task %u: no abort needed for ctx %p\n",
2224 __func__
, chan
->ic_task
, ctx
);
2233 dev_dbg(priv
->ipu
->dev
,
2234 "%s: task %u: wait for completion: %d runs\n",
2235 __func__
, chan
->ic_task
, run_count
);
2237 ret
= wait_for_completion_timeout(&ctx
->aborted
,
2238 msecs_to_jiffies(10000));
2240 dev_warn(priv
->ipu
->dev
, "%s: timeout\n", __func__
);
2245 void ipu_image_convert_abort(struct ipu_image_convert_ctx
*ctx
)
2247 __ipu_image_convert_abort(ctx
);
2248 ctx
->aborting
= false;
2250 EXPORT_SYMBOL_GPL(ipu_image_convert_abort
);
2252 /* Unprepare image conversion context */
2253 void ipu_image_convert_unprepare(struct ipu_image_convert_ctx
*ctx
)
2255 struct ipu_image_convert_chan
*chan
= ctx
->chan
;
2256 struct ipu_image_convert_priv
*priv
= chan
->priv
;
2257 unsigned long flags
;
2260 /* make sure no runs are hanging around */
2261 __ipu_image_convert_abort(ctx
);
2263 dev_dbg(priv
->ipu
->dev
, "%s: task %u: removing ctx %p\n", __func__
,
2264 chan
->ic_task
, ctx
);
2266 spin_lock_irqsave(&chan
->irqlock
, flags
);
2268 list_del(&ctx
->list
);
2270 put_res
= list_empty(&chan
->ctx_list
);
2272 spin_unlock_irqrestore(&chan
->irqlock
, flags
);
2275 release_ipu_resources(chan
);
2277 free_dma_buf(priv
, &ctx
->rot_intermediate
[1]);
2278 free_dma_buf(priv
, &ctx
->rot_intermediate
[0]);
2282 EXPORT_SYMBOL_GPL(ipu_image_convert_unprepare
);
2285 * "Canned" asynchronous single image conversion. Allocates and returns
2286 * a new conversion run. On successful return the caller must free the
2287 * run and call ipu_image_convert_unprepare() after conversion completes.
2289 struct ipu_image_convert_run
*
2290 ipu_image_convert(struct ipu_soc
*ipu
, enum ipu_ic_task ic_task
,
2291 struct ipu_image
*in
, struct ipu_image
*out
,
2292 enum ipu_rotate_mode rot_mode
,
2293 ipu_image_convert_cb_t complete
,
2294 void *complete_context
)
2296 struct ipu_image_convert_ctx
*ctx
;
2297 struct ipu_image_convert_run
*run
;
2300 ctx
= ipu_image_convert_prepare(ipu
, ic_task
, in
, out
, rot_mode
,
2301 complete
, complete_context
);
2303 return ERR_CAST(ctx
);
2305 run
= kzalloc(sizeof(*run
), GFP_KERNEL
);
2307 ipu_image_convert_unprepare(ctx
);
2308 return ERR_PTR(-ENOMEM
);
2312 run
->in_phys
= in
->phys0
;
2313 run
->out_phys
= out
->phys0
;
2315 ret
= ipu_image_convert_queue(run
);
2317 ipu_image_convert_unprepare(ctx
);
2319 return ERR_PTR(ret
);
2324 EXPORT_SYMBOL_GPL(ipu_image_convert
);
2326 /* "Canned" synchronous single image conversion */
2327 static void image_convert_sync_complete(struct ipu_image_convert_run
*run
,
2330 struct completion
*comp
= data
;
2335 int ipu_image_convert_sync(struct ipu_soc
*ipu
, enum ipu_ic_task ic_task
,
2336 struct ipu_image
*in
, struct ipu_image
*out
,
2337 enum ipu_rotate_mode rot_mode
)
2339 struct ipu_image_convert_run
*run
;
2340 struct completion comp
;
2343 init_completion(&comp
);
2345 run
= ipu_image_convert(ipu
, ic_task
, in
, out
, rot_mode
,
2346 image_convert_sync_complete
, &comp
);
2348 return PTR_ERR(run
);
2350 ret
= wait_for_completion_timeout(&comp
, msecs_to_jiffies(10000));
2351 ret
= (ret
== 0) ? -ETIMEDOUT
: 0;
2353 ipu_image_convert_unprepare(run
->ctx
);
2358 EXPORT_SYMBOL_GPL(ipu_image_convert_sync
);
2360 int ipu_image_convert_init(struct ipu_soc
*ipu
, struct device
*dev
)
2362 struct ipu_image_convert_priv
*priv
;
2365 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
2369 ipu
->image_convert_priv
= priv
;
2372 for (i
= 0; i
< IC_NUM_TASKS
; i
++) {
2373 struct ipu_image_convert_chan
*chan
= &priv
->chan
[i
];
2377 chan
->dma_ch
= &image_convert_dma_chan
[i
];
2378 chan
->out_eof_irq
= -1;
2379 chan
->rot_out_eof_irq
= -1;
2381 spin_lock_init(&chan
->irqlock
);
2382 INIT_LIST_HEAD(&chan
->ctx_list
);
2383 INIT_LIST_HEAD(&chan
->pending_q
);
2384 INIT_LIST_HEAD(&chan
->done_q
);
2390 void ipu_image_convert_exit(struct ipu_soc
*ipu
)