1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
5 * Copyright (c) 2015 Kontron
6 * Author: Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>
8 * Copyright (c) 2019 Advantech
9 * Author: Amy.Shih <amy.shih@advantech.com.tw>
11 * Supports the following chips:
13 * Chip #vin #fan #pwm #temp #dts chip ID
14 * nct7904d 20 12 4 5 8 0xc5
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/init.h>
20 #include <linux/i2c.h>
21 #include <linux/mutex.h>
22 #include <linux/hwmon.h>
24 #define VENDOR_ID_REG 0x7A /* Any bank */
25 #define NUVOTON_ID 0x50
26 #define CHIP_ID_REG 0x7B /* Any bank */
27 #define NCT7904_ID 0xC5
28 #define DEVICE_ID_REG 0x7C /* Any bank */
30 #define BANK_SEL_REG 0xFF
38 #define FANIN_MAX 12 /* Counted from 1 */
39 #define VSEN_MAX 21 /* VSEN1..14, 3VDD, VBAT, V3VSB,
40 LTD (not a voltage), VSEN17..19 */
41 #define FANCTL_MAX 4 /* Counted from 1 */
42 #define TCPU_MAX 8 /* Counted from 1 */
43 #define TEMP_MAX 4 /* Counted from 1 */
44 #define SMI_STS_MAX 10 /* Counted from 1 */
46 #define VT_ADC_CTRL0_REG 0x20 /* Bank 0 */
47 #define VT_ADC_CTRL1_REG 0x21 /* Bank 0 */
48 #define VT_ADC_CTRL2_REG 0x22 /* Bank 0 */
49 #define FANIN_CTRL0_REG 0x24
50 #define FANIN_CTRL1_REG 0x25
51 #define DTS_T_CTRL0_REG 0x26
52 #define DTS_T_CTRL1_REG 0x27
53 #define VT_ADC_MD_REG 0x2E
55 #define VSEN1_HV_LL_REG 0x02 /* Bank 1; 2 regs (HV/LV) per sensor */
56 #define VSEN1_LV_LL_REG 0x03 /* Bank 1; 2 regs (HV/LV) per sensor */
57 #define VSEN1_HV_HL_REG 0x00 /* Bank 1; 2 regs (HV/LV) per sensor */
58 #define VSEN1_LV_HL_REG 0x01 /* Bank 1; 2 regs (HV/LV) per sensor */
59 #define SMI_STS1_REG 0xC1 /* Bank 0; SMI Status Register */
60 #define SMI_STS3_REG 0xC3 /* Bank 0; SMI Status Register */
61 #define SMI_STS5_REG 0xC5 /* Bank 0; SMI Status Register */
62 #define SMI_STS7_REG 0xC7 /* Bank 0; SMI Status Register */
63 #define SMI_STS8_REG 0xC8 /* Bank 0; SMI Status Register */
65 #define VSEN1_HV_REG 0x40 /* Bank 0; 2 regs (HV/LV) per sensor */
66 #define TEMP_CH1_HV_REG 0x42 /* Bank 0; same as VSEN2_HV */
67 #define LTD_HV_REG 0x62 /* Bank 0; 2 regs in VSEN range */
68 #define LTD_HV_HL_REG 0x44 /* Bank 1; 1 reg for LTD */
69 #define LTD_LV_HL_REG 0x45 /* Bank 1; 1 reg for LTD */
70 #define LTD_HV_LL_REG 0x46 /* Bank 1; 1 reg for LTD */
71 #define LTD_LV_LL_REG 0x47 /* Bank 1; 1 reg for LTD */
72 #define TEMP_CH1_CH_REG 0x05 /* Bank 1; 1 reg for LTD */
73 #define TEMP_CH1_W_REG 0x06 /* Bank 1; 1 reg for LTD */
74 #define TEMP_CH1_WH_REG 0x07 /* Bank 1; 1 reg for LTD */
75 #define TEMP_CH1_C_REG 0x04 /* Bank 1; 1 reg per sensor */
76 #define DTS_T_CPU1_C_REG 0x90 /* Bank 1; 1 reg per sensor */
77 #define DTS_T_CPU1_CH_REG 0x91 /* Bank 1; 1 reg per sensor */
78 #define DTS_T_CPU1_W_REG 0x92 /* Bank 1; 1 reg per sensor */
79 #define DTS_T_CPU1_WH_REG 0x93 /* Bank 1; 1 reg per sensor */
80 #define FANIN1_HV_REG 0x80 /* Bank 0; 2 regs (HV/LV) per sensor */
81 #define FANIN1_HV_HL_REG 0x60 /* Bank 1; 2 regs (HV/LV) per sensor */
82 #define FANIN1_LV_HL_REG 0x61 /* Bank 1; 2 regs (HV/LV) per sensor */
83 #define T_CPU1_HV_REG 0xA0 /* Bank 0; 2 regs (HV/LV) per sensor */
85 #define PRTS_REG 0x03 /* Bank 2 */
86 #define PFE_REG 0x00 /* Bank 2; PECI Function Enable */
87 #define TSI_CTRL_REG 0x50 /* Bank 2; TSI Control Register */
88 #define FANCTL1_FMR_REG 0x00 /* Bank 3; 1 reg per channel */
89 #define FANCTL1_OUT_REG 0x10 /* Bank 3; 1 reg per channel */
91 #define VOLT_MONITOR_MODE 0x0
92 #define THERMAL_DIODE_MODE 0x1
93 #define THERMISTOR_MODE 0x3
95 #define ENABLE_TSI BIT(1)
97 static const unsigned short normal_i2c
[] = {
98 0x2d, 0x2e, I2C_CLIENT_END
101 struct nct7904_data
{
102 struct i2c_client
*client
;
103 struct mutex bank_lock
;
108 u8 fan_mode
[FANCTL_MAX
];
111 u8 temp_mode
; /* 0: TR mode, 1: TD mode */
116 /* Access functions */
117 static int nct7904_bank_lock(struct nct7904_data
*data
, unsigned int bank
)
121 mutex_lock(&data
->bank_lock
);
122 if (data
->bank_sel
== bank
)
124 ret
= i2c_smbus_write_byte_data(data
->client
, BANK_SEL_REG
, bank
);
126 data
->bank_sel
= bank
;
132 static inline void nct7904_bank_release(struct nct7904_data
*data
)
134 mutex_unlock(&data
->bank_lock
);
137 /* Read 1-byte register. Returns unsigned reg or -ERRNO on error. */
138 static int nct7904_read_reg(struct nct7904_data
*data
,
139 unsigned int bank
, unsigned int reg
)
141 struct i2c_client
*client
= data
->client
;
144 ret
= nct7904_bank_lock(data
, bank
);
146 ret
= i2c_smbus_read_byte_data(client
, reg
);
148 nct7904_bank_release(data
);
153 * Read 2-byte register. Returns register in big-endian format or
156 static int nct7904_read_reg16(struct nct7904_data
*data
,
157 unsigned int bank
, unsigned int reg
)
159 struct i2c_client
*client
= data
->client
;
162 ret
= nct7904_bank_lock(data
, bank
);
164 ret
= i2c_smbus_read_byte_data(client
, reg
);
167 ret
= i2c_smbus_read_byte_data(client
, reg
+ 1);
173 nct7904_bank_release(data
);
177 /* Write 1-byte register. Returns 0 or -ERRNO on error. */
178 static int nct7904_write_reg(struct nct7904_data
*data
,
179 unsigned int bank
, unsigned int reg
, u8 val
)
181 struct i2c_client
*client
= data
->client
;
184 ret
= nct7904_bank_lock(data
, bank
);
186 ret
= i2c_smbus_write_byte_data(client
, reg
, val
);
188 nct7904_bank_release(data
);
192 static int nct7904_read_fan(struct device
*dev
, u32 attr
, int channel
,
195 struct nct7904_data
*data
= dev_get_drvdata(dev
);
196 unsigned int cnt
, rpm
;
200 case hwmon_fan_input
:
201 ret
= nct7904_read_reg16(data
, BANK_0
,
202 FANIN1_HV_REG
+ channel
* 2);
205 cnt
= ((ret
& 0xff00) >> 3) | (ret
& 0x1f);
213 ret
= nct7904_read_reg16(data
, BANK_1
,
214 FANIN1_HV_HL_REG
+ channel
* 2);
217 cnt
= ((ret
& 0xff00) >> 3) | (ret
& 0x1f);
224 case hwmon_fan_alarm
:
225 ret
= nct7904_read_reg(data
, BANK_0
,
226 SMI_STS5_REG
+ (channel
>> 3));
229 if (!data
->fan_alarm
[channel
>> 3])
230 data
->fan_alarm
[channel
>> 3] = ret
& 0xff;
232 /* If there is new alarm showing up */
233 data
->fan_alarm
[channel
>> 3] |= (ret
& 0xff);
234 *val
= (data
->fan_alarm
[channel
>> 3] >> (channel
& 0x07)) & 1;
235 /* Needs to clean the alarm if alarm existing */
237 data
->fan_alarm
[channel
>> 3] ^= 1 << (channel
& 0x07);
244 static umode_t
nct7904_fan_is_visible(const void *_data
, u32 attr
, int channel
)
246 const struct nct7904_data
*data
= _data
;
249 case hwmon_fan_input
:
250 case hwmon_fan_alarm
:
251 if (data
->fanin_mask
& (1 << channel
))
255 if (data
->fanin_mask
& (1 << channel
))
265 static u8 nct7904_chan_to_index
[] = {
267 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
271 static int nct7904_read_in(struct device
*dev
, u32 attr
, int channel
,
274 struct nct7904_data
*data
= dev_get_drvdata(dev
);
275 int ret
, volt
, index
;
277 index
= nct7904_chan_to_index
[channel
];
281 ret
= nct7904_read_reg16(data
, BANK_0
,
282 VSEN1_HV_REG
+ index
* 2);
285 volt
= ((ret
& 0xff00) >> 5) | (ret
& 0x7);
287 volt
*= 2; /* 0.002V scale */
289 volt
*= 6; /* 0.006V scale */
293 ret
= nct7904_read_reg16(data
, BANK_1
,
294 VSEN1_HV_LL_REG
+ index
* 4);
297 volt
= ((ret
& 0xff00) >> 5) | (ret
& 0x7);
299 volt
*= 2; /* 0.002V scale */
301 volt
*= 6; /* 0.006V scale */
305 ret
= nct7904_read_reg16(data
, BANK_1
,
306 VSEN1_HV_HL_REG
+ index
* 4);
309 volt
= ((ret
& 0xff00) >> 5) | (ret
& 0x7);
311 volt
*= 2; /* 0.002V scale */
313 volt
*= 6; /* 0.006V scale */
317 ret
= nct7904_read_reg(data
, BANK_0
,
318 SMI_STS1_REG
+ (index
>> 3));
321 if (!data
->vsen_alarm
[index
>> 3])
322 data
->vsen_alarm
[index
>> 3] = ret
& 0xff;
324 /* If there is new alarm showing up */
325 data
->vsen_alarm
[index
>> 3] |= (ret
& 0xff);
326 *val
= (data
->vsen_alarm
[index
>> 3] >> (index
& 0x07)) & 1;
327 /* Needs to clean the alarm if alarm existing */
329 data
->vsen_alarm
[index
>> 3] ^= 1 << (index
& 0x07);
336 static umode_t
nct7904_in_is_visible(const void *_data
, u32 attr
, int channel
)
338 const struct nct7904_data
*data
= _data
;
339 int index
= nct7904_chan_to_index
[channel
];
344 if (channel
> 0 && (data
->vsen_mask
& BIT(index
)))
349 if (channel
> 0 && (data
->vsen_mask
& BIT(index
)))
359 static int nct7904_read_temp(struct device
*dev
, u32 attr
, int channel
,
362 struct nct7904_data
*data
= dev_get_drvdata(dev
);
364 unsigned int reg1
, reg2
, reg3
;
368 case hwmon_temp_input
:
370 ret
= nct7904_read_reg16(data
, BANK_0
, LTD_HV_REG
);
371 else if (channel
< 5)
372 ret
= nct7904_read_reg16(data
, BANK_0
,
373 TEMP_CH1_HV_REG
+ channel
* 4);
375 ret
= nct7904_read_reg16(data
, BANK_0
,
376 T_CPU1_HV_REG
+ (channel
- 5)
380 temp
= ((ret
& 0xff00) >> 5) | (ret
& 0x7);
381 *val
= sign_extend32(temp
, 10) * 125;
383 case hwmon_temp_alarm
:
385 ret
= nct7904_read_reg(data
, BANK_0
,
389 *val
= (ret
>> 1) & 1;
390 } else if (channel
< 4) {
391 ret
= nct7904_read_reg(data
, BANK_0
,
395 *val
= (ret
>> (((channel
* 2) + 1) & 0x07)) & 1;
397 if ((channel
- 5) < 4) {
398 ret
= nct7904_read_reg(data
, BANK_0
,
400 ((channel
- 5) >> 3));
403 *val
= (ret
>> ((channel
- 5) & 0x07)) & 1;
405 ret
= nct7904_read_reg(data
, BANK_0
,
407 ((channel
- 5) >> 3));
410 *val
= (ret
>> (((channel
- 5) & 0x07) - 4))
415 case hwmon_temp_type
:
417 if ((data
->tcpu_mask
>> channel
) & 0x01) {
418 if ((data
->temp_mode
>> channel
) & 0x01)
426 if ((data
->has_dts
>> (channel
- 5)) & 0x01) {
427 if (data
->enable_dts
& ENABLE_TSI
)
437 reg1
= LTD_HV_LL_REG
;
438 reg2
= TEMP_CH1_W_REG
;
439 reg3
= DTS_T_CPU1_W_REG
;
441 case hwmon_temp_max_hyst
:
442 reg1
= LTD_LV_LL_REG
;
443 reg2
= TEMP_CH1_WH_REG
;
444 reg3
= DTS_T_CPU1_WH_REG
;
446 case hwmon_temp_crit
:
447 reg1
= LTD_HV_HL_REG
;
448 reg2
= TEMP_CH1_C_REG
;
449 reg3
= DTS_T_CPU1_C_REG
;
451 case hwmon_temp_crit_hyst
:
452 reg1
= LTD_LV_HL_REG
;
453 reg2
= TEMP_CH1_CH_REG
;
454 reg3
= DTS_T_CPU1_CH_REG
;
461 ret
= nct7904_read_reg(data
, BANK_1
, reg1
);
462 else if (channel
< 5)
463 ret
= nct7904_read_reg(data
, BANK_1
,
466 ret
= nct7904_read_reg(data
, BANK_1
,
467 reg3
+ (channel
- 5) * 4);
476 static umode_t
nct7904_temp_is_visible(const void *_data
, u32 attr
, int channel
)
478 const struct nct7904_data
*data
= _data
;
481 case hwmon_temp_input
:
482 case hwmon_temp_alarm
:
483 case hwmon_temp_type
:
485 if (data
->tcpu_mask
& BIT(channel
))
488 if (data
->has_dts
& BIT(channel
- 5))
493 case hwmon_temp_max_hyst
:
494 case hwmon_temp_crit
:
495 case hwmon_temp_crit_hyst
:
497 if (data
->tcpu_mask
& BIT(channel
))
500 if (data
->has_dts
& BIT(channel
- 5))
511 static int nct7904_read_pwm(struct device
*dev
, u32 attr
, int channel
,
514 struct nct7904_data
*data
= dev_get_drvdata(dev
);
518 case hwmon_pwm_input
:
519 ret
= nct7904_read_reg(data
, BANK_3
, FANCTL1_OUT_REG
+ channel
);
524 case hwmon_pwm_enable
:
525 ret
= nct7904_read_reg(data
, BANK_3
, FANCTL1_FMR_REG
+ channel
);
536 static int nct7904_write_temp(struct device
*dev
, u32 attr
, int channel
,
539 struct nct7904_data
*data
= dev_get_drvdata(dev
);
541 unsigned int reg1
, reg2
, reg3
;
543 val
= clamp_val(val
/ 1000, -128, 127);
547 reg1
= LTD_HV_LL_REG
;
548 reg2
= TEMP_CH1_W_REG
;
549 reg3
= DTS_T_CPU1_W_REG
;
551 case hwmon_temp_max_hyst
:
552 reg1
= LTD_LV_LL_REG
;
553 reg2
= TEMP_CH1_WH_REG
;
554 reg3
= DTS_T_CPU1_WH_REG
;
556 case hwmon_temp_crit
:
557 reg1
= LTD_HV_HL_REG
;
558 reg2
= TEMP_CH1_C_REG
;
559 reg3
= DTS_T_CPU1_C_REG
;
561 case hwmon_temp_crit_hyst
:
562 reg1
= LTD_LV_HL_REG
;
563 reg2
= TEMP_CH1_CH_REG
;
564 reg3
= DTS_T_CPU1_CH_REG
;
570 ret
= nct7904_write_reg(data
, BANK_1
, reg1
, val
);
571 else if (channel
< 5)
572 ret
= nct7904_write_reg(data
, BANK_1
,
573 reg2
+ channel
* 8, val
);
575 ret
= nct7904_write_reg(data
, BANK_1
,
576 reg3
+ (channel
- 5) * 4, val
);
581 static int nct7904_write_fan(struct device
*dev
, u32 attr
, int channel
,
584 struct nct7904_data
*data
= dev_get_drvdata(dev
);
593 val
= clamp_val(DIV_ROUND_CLOSEST(1350000, val
), 1, 0x1fff);
594 tmp
= (val
>> 5) & 0xff;
595 ret
= nct7904_write_reg(data
, BANK_1
,
596 FANIN1_HV_HL_REG
+ channel
* 2, tmp
);
600 ret
= nct7904_write_reg(data
, BANK_1
,
601 FANIN1_LV_HL_REG
+ channel
* 2, tmp
);
608 static int nct7904_write_in(struct device
*dev
, u32 attr
, int channel
,
611 struct nct7904_data
*data
= dev_get_drvdata(dev
);
614 index
= nct7904_chan_to_index
[channel
];
617 val
= val
/ 2; /* 0.002V scale */
619 val
= val
/ 6; /* 0.006V scale */
621 val
= clamp_val(val
, 0, 0x7ff);
625 tmp
= nct7904_read_reg(data
, BANK_1
,
626 VSEN1_LV_LL_REG
+ index
* 4);
631 ret
= nct7904_write_reg(data
, BANK_1
,
632 VSEN1_LV_LL_REG
+ index
* 4, tmp
);
635 tmp
= nct7904_read_reg(data
, BANK_1
,
636 VSEN1_HV_LL_REG
+ index
* 4);
639 tmp
= (val
>> 3) & 0xff;
640 ret
= nct7904_write_reg(data
, BANK_1
,
641 VSEN1_HV_LL_REG
+ index
* 4, tmp
);
644 tmp
= nct7904_read_reg(data
, BANK_1
,
645 VSEN1_LV_HL_REG
+ index
* 4);
650 ret
= nct7904_write_reg(data
, BANK_1
,
651 VSEN1_LV_HL_REG
+ index
* 4, tmp
);
654 tmp
= nct7904_read_reg(data
, BANK_1
,
655 VSEN1_HV_HL_REG
+ index
* 4);
658 tmp
= (val
>> 3) & 0xff;
659 ret
= nct7904_write_reg(data
, BANK_1
,
660 VSEN1_HV_HL_REG
+ index
* 4, tmp
);
667 static int nct7904_write_pwm(struct device
*dev
, u32 attr
, int channel
,
670 struct nct7904_data
*data
= dev_get_drvdata(dev
);
674 case hwmon_pwm_input
:
675 if (val
< 0 || val
> 255)
677 ret
= nct7904_write_reg(data
, BANK_3
, FANCTL1_OUT_REG
+ channel
,
680 case hwmon_pwm_enable
:
681 if (val
< 1 || val
> 2 ||
682 (val
== 2 && !data
->fan_mode
[channel
]))
684 ret
= nct7904_write_reg(data
, BANK_3
, FANCTL1_FMR_REG
+ channel
,
685 val
== 2 ? data
->fan_mode
[channel
] : 0);
692 static umode_t
nct7904_pwm_is_visible(const void *_data
, u32 attr
, int channel
)
695 case hwmon_pwm_input
:
696 case hwmon_pwm_enable
:
703 static int nct7904_read(struct device
*dev
, enum hwmon_sensor_types type
,
704 u32 attr
, int channel
, long *val
)
708 return nct7904_read_in(dev
, attr
, channel
, val
);
710 return nct7904_read_fan(dev
, attr
, channel
, val
);
712 return nct7904_read_pwm(dev
, attr
, channel
, val
);
714 return nct7904_read_temp(dev
, attr
, channel
, val
);
720 static int nct7904_write(struct device
*dev
, enum hwmon_sensor_types type
,
721 u32 attr
, int channel
, long val
)
725 return nct7904_write_in(dev
, attr
, channel
, val
);
727 return nct7904_write_fan(dev
, attr
, channel
, val
);
729 return nct7904_write_pwm(dev
, attr
, channel
, val
);
731 return nct7904_write_temp(dev
, attr
, channel
, val
);
737 static umode_t
nct7904_is_visible(const void *data
,
738 enum hwmon_sensor_types type
,
739 u32 attr
, int channel
)
743 return nct7904_in_is_visible(data
, attr
, channel
);
745 return nct7904_fan_is_visible(data
, attr
, channel
);
747 return nct7904_pwm_is_visible(data
, attr
, channel
);
749 return nct7904_temp_is_visible(data
, attr
, channel
);
755 /* Return 0 if detection is successful, -ENODEV otherwise */
756 static int nct7904_detect(struct i2c_client
*client
,
757 struct i2c_board_info
*info
)
759 struct i2c_adapter
*adapter
= client
->adapter
;
761 if (!i2c_check_functionality(adapter
,
762 I2C_FUNC_SMBUS_READ_BYTE
|
763 I2C_FUNC_SMBUS_WRITE_BYTE_DATA
))
766 /* Determine the chip type. */
767 if (i2c_smbus_read_byte_data(client
, VENDOR_ID_REG
) != NUVOTON_ID
||
768 i2c_smbus_read_byte_data(client
, CHIP_ID_REG
) != NCT7904_ID
||
769 (i2c_smbus_read_byte_data(client
, DEVICE_ID_REG
) & 0xf0) != 0x50 ||
770 (i2c_smbus_read_byte_data(client
, BANK_SEL_REG
) & 0xf8) != 0x00)
773 strlcpy(info
->type
, "nct7904", I2C_NAME_SIZE
);
778 static const struct hwmon_channel_info
*nct7904_info
[] = {
779 HWMON_CHANNEL_INFO(in
,
780 /* dummy, skipped in is_visible */
781 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
783 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
785 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
787 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
789 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
791 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
793 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
795 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
797 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
799 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
801 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
803 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
805 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
807 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
809 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
811 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
813 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
815 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
817 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
819 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
821 HWMON_I_INPUT
| HWMON_I_MIN
| HWMON_I_MAX
|
823 HWMON_CHANNEL_INFO(fan
,
824 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
825 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
826 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
827 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
828 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
829 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
830 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
831 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
832 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
833 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
834 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
,
835 HWMON_F_INPUT
| HWMON_F_MIN
| HWMON_F_ALARM
),
836 HWMON_CHANNEL_INFO(pwm
,
837 HWMON_PWM_INPUT
| HWMON_PWM_ENABLE
,
838 HWMON_PWM_INPUT
| HWMON_PWM_ENABLE
,
839 HWMON_PWM_INPUT
| HWMON_PWM_ENABLE
,
840 HWMON_PWM_INPUT
| HWMON_PWM_ENABLE
),
841 HWMON_CHANNEL_INFO(temp
,
842 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
843 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
845 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
846 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
848 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
849 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
851 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
852 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
854 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
855 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
857 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
858 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
860 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
861 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
863 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
864 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
866 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
867 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
869 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
870 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
872 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
873 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
875 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
876 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
878 HWMON_T_INPUT
| HWMON_T_ALARM
| HWMON_T_MAX
|
879 HWMON_T_MAX_HYST
| HWMON_T_TYPE
| HWMON_T_CRIT
|
884 static const struct hwmon_ops nct7904_hwmon_ops
= {
885 .is_visible
= nct7904_is_visible
,
886 .read
= nct7904_read
,
887 .write
= nct7904_write
,
890 static const struct hwmon_chip_info nct7904_chip_info
= {
891 .ops
= &nct7904_hwmon_ops
,
892 .info
= nct7904_info
,
895 static int nct7904_probe(struct i2c_client
*client
,
896 const struct i2c_device_id
*id
)
898 struct nct7904_data
*data
;
899 struct device
*hwmon_dev
;
900 struct device
*dev
= &client
->dev
;
905 data
= devm_kzalloc(dev
, sizeof(struct nct7904_data
), GFP_KERNEL
);
909 data
->client
= client
;
910 mutex_init(&data
->bank_lock
);
913 /* Setup sensor groups. */
914 /* FANIN attributes */
915 ret
= nct7904_read_reg16(data
, BANK_0
, FANIN_CTRL0_REG
);
918 data
->fanin_mask
= (ret
>> 8) | ((ret
& 0xff) << 8);
923 * Note: voltage sensors overlap with external temperature
924 * sensors. So, if we ever decide to support the latter
925 * we will have to adjust 'vsen_mask' accordingly.
928 ret
= nct7904_read_reg16(data
, BANK_0
, VT_ADC_CTRL0_REG
);
930 mask
= (ret
>> 8) | ((ret
& 0xff) << 8);
931 ret
= nct7904_read_reg(data
, BANK_0
, VT_ADC_CTRL2_REG
);
934 data
->vsen_mask
= mask
;
936 /* CPU_TEMP attributes */
937 ret
= nct7904_read_reg(data
, BANK_0
, VT_ADC_CTRL0_REG
);
941 if ((ret
& 0x6) == 0x6)
942 data
->tcpu_mask
|= 1; /* TR1 */
943 if ((ret
& 0x18) == 0x18)
944 data
->tcpu_mask
|= 2; /* TR2 */
945 if ((ret
& 0x20) == 0x20)
946 data
->tcpu_mask
|= 4; /* TR3 */
947 if ((ret
& 0x80) == 0x80)
948 data
->tcpu_mask
|= 8; /* TR4 */
951 ret
= nct7904_read_reg(data
, BANK_0
, VT_ADC_CTRL2_REG
);
954 if ((ret
& 0x02) == 0x02)
955 data
->tcpu_mask
|= 0x10;
957 /* Multi-Function detecting for Volt and TR/TD */
958 ret
= nct7904_read_reg(data
, BANK_0
, VT_ADC_MD_REG
);
963 for (i
= 0; i
< 4; i
++) {
964 val
= (ret
>> (i
* 2)) & 0x03;
966 if (val
== VOLT_MONITOR_MODE
) {
967 data
->tcpu_mask
&= ~bit
;
968 } else if (val
== THERMAL_DIODE_MODE
&& i
< 2) {
969 data
->temp_mode
|= bit
;
970 data
->vsen_mask
&= ~(0x06 << (i
* 2));
971 } else if (val
== THERMISTOR_MODE
) {
972 data
->vsen_mask
&= ~(0x02 << (i
* 2));
975 data
->tcpu_mask
&= ~bit
;
976 data
->vsen_mask
&= ~(0x06 << (i
* 2));
981 ret
= nct7904_read_reg(data
, BANK_2
, PFE_REG
);
985 data
->enable_dts
= 1; /* Enable DTS & PECI */
987 ret
= nct7904_read_reg(data
, BANK_2
, TSI_CTRL_REG
);
991 data
->enable_dts
= 0x3; /* Enable DTS & TSI */
994 /* Check DTS enable status */
995 if (data
->enable_dts
) {
996 ret
= nct7904_read_reg(data
, BANK_0
, DTS_T_CTRL0_REG
);
999 data
->has_dts
= ret
& 0xF;
1000 if (data
->enable_dts
& ENABLE_TSI
) {
1001 ret
= nct7904_read_reg(data
, BANK_0
, DTS_T_CTRL1_REG
);
1004 data
->has_dts
|= (ret
& 0xF) << 4;
1008 for (i
= 0; i
< FANCTL_MAX
; i
++) {
1009 ret
= nct7904_read_reg(data
, BANK_3
, FANCTL1_FMR_REG
+ i
);
1012 data
->fan_mode
[i
] = ret
;
1015 /* Read all of SMI status register to clear alarms */
1016 for (i
= 0; i
< SMI_STS_MAX
; i
++) {
1017 ret
= nct7904_read_reg(data
, BANK_0
, SMI_STS1_REG
+ i
);
1023 devm_hwmon_device_register_with_info(dev
, client
->name
, data
,
1024 &nct7904_chip_info
, NULL
);
1025 return PTR_ERR_OR_ZERO(hwmon_dev
);
1028 static const struct i2c_device_id nct7904_id
[] = {
1032 MODULE_DEVICE_TABLE(i2c
, nct7904_id
);
1034 static struct i2c_driver nct7904_driver
= {
1035 .class = I2C_CLASS_HWMON
,
1039 .probe
= nct7904_probe
,
1040 .id_table
= nct7904_id
,
1041 .detect
= nct7904_detect
,
1042 .address_list
= normal_i2c
,
1045 module_i2c_driver(nct7904_driver
);
1047 MODULE_AUTHOR("Vadim V. Vlasov <vvlasov@dev.rtsoft.ru>");
1048 MODULE_DESCRIPTION("Hwmon driver for NUVOTON NCT7904");
1049 MODULE_LICENSE("GPL");