1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
4 * Copyright (C) 2004,2005,2009 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C2410 I2C Controller
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/i2c.h>
14 #include <linux/init.h>
15 #include <linux/time.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/clk.h>
23 #include <linux/cpufreq.h>
24 #include <linux/slab.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
38 #define S3C2410_IICCON 0x00
39 #define S3C2410_IICSTAT 0x04
40 #define S3C2410_IICADD 0x08
41 #define S3C2410_IICDS 0x0C
42 #define S3C2440_IICLC 0x10
44 #define S3C2410_IICCON_ACKEN (1 << 7)
45 #define S3C2410_IICCON_TXDIV_16 (0 << 6)
46 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
47 #define S3C2410_IICCON_IRQEN (1 << 5)
48 #define S3C2410_IICCON_IRQPEND (1 << 4)
49 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
50 #define S3C2410_IICCON_SCALEMASK (0xf)
52 #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
53 #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
54 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
55 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
56 #define S3C2410_IICSTAT_MODEMASK (3 << 6)
58 #define S3C2410_IICSTAT_START (1 << 5)
59 #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
60 #define S3C2410_IICSTAT_TXRXEN (1 << 4)
61 #define S3C2410_IICSTAT_ARBITR (1 << 3)
62 #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
63 #define S3C2410_IICSTAT_ADDR0 (1 << 1)
64 #define S3C2410_IICSTAT_LASTBIT (1 << 0)
66 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
67 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
68 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
69 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
70 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
72 #define S3C2410_IICLC_FILTER_ON (1 << 2)
74 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
75 #define QUIRK_S3C2440 (1 << 0)
76 #define QUIRK_HDMIPHY (1 << 1)
77 #define QUIRK_NO_GPIO (1 << 2)
78 #define QUIRK_POLL (1 << 3)
80 /* Max time to wait for bus to become idle after a xfer (in us) */
81 #define S3C2410_IDLE_TIMEOUT 5000
83 /* Exynos5 Sysreg offset */
84 #define EXYNOS5_SYS_I2C_CFG 0x0234
86 /* i2c controller state */
87 enum s3c24xx_i2c_state
{
96 wait_queue_head_t wait
;
97 kernel_ulong_t quirks
;
100 unsigned int msg_num
;
101 unsigned int msg_idx
;
102 unsigned int msg_ptr
;
104 unsigned int tx_setup
;
107 enum s3c24xx_i2c_state state
;
108 unsigned long clkrate
;
113 struct i2c_adapter adap
;
115 struct s3c2410_platform_i2c
*pdata
;
116 struct gpio_desc
*gpios
[2];
117 struct pinctrl
*pctrl
;
118 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
119 struct notifier_block freq_transition
;
121 struct regmap
*sysreg
;
122 unsigned int sys_i2c_cfg
;
125 static const struct platform_device_id s3c24xx_driver_ids
[] = {
127 .name
= "s3c2410-i2c",
130 .name
= "s3c2440-i2c",
131 .driver_data
= QUIRK_S3C2440
,
133 .name
= "s3c2440-hdmiphy-i2c",
134 .driver_data
= QUIRK_S3C2440
| QUIRK_HDMIPHY
| QUIRK_NO_GPIO
,
137 MODULE_DEVICE_TABLE(platform
, s3c24xx_driver_ids
);
139 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c
*i2c
, unsigned long iicstat
);
142 static const struct of_device_id s3c24xx_i2c_match
[] = {
143 { .compatible
= "samsung,s3c2410-i2c", .data
= (void *)0 },
144 { .compatible
= "samsung,s3c2440-i2c", .data
= (void *)QUIRK_S3C2440
},
145 { .compatible
= "samsung,s3c2440-hdmiphy-i2c",
146 .data
= (void *)(QUIRK_S3C2440
| QUIRK_HDMIPHY
| QUIRK_NO_GPIO
) },
147 { .compatible
= "samsung,exynos5-sata-phy-i2c",
148 .data
= (void *)(QUIRK_S3C2440
| QUIRK_POLL
| QUIRK_NO_GPIO
) },
151 MODULE_DEVICE_TABLE(of
, s3c24xx_i2c_match
);
155 * Get controller type either from device tree or platform device variant.
157 static inline kernel_ulong_t
s3c24xx_get_device_quirks(struct platform_device
*pdev
)
159 if (pdev
->dev
.of_node
) {
160 const struct of_device_id
*match
;
162 match
= of_match_node(s3c24xx_i2c_match
, pdev
->dev
.of_node
);
163 return (kernel_ulong_t
)match
->data
;
166 return platform_get_device_id(pdev
)->driver_data
;
170 * Complete the message and wake up the caller, using the given return code,
171 * or zero to mean ok.
173 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c
*i2c
, int ret
)
175 dev_dbg(i2c
->dev
, "master_complete %d\n", ret
);
184 if (!(i2c
->quirks
& QUIRK_POLL
))
188 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c
*i2c
)
192 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
193 writel(tmp
& ~S3C2410_IICCON_ACKEN
, i2c
->regs
+ S3C2410_IICCON
);
196 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c
*i2c
)
200 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
201 writel(tmp
| S3C2410_IICCON_ACKEN
, i2c
->regs
+ S3C2410_IICCON
);
204 /* irq enable/disable functions */
205 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c
*i2c
)
209 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
210 writel(tmp
& ~S3C2410_IICCON_IRQEN
, i2c
->regs
+ S3C2410_IICCON
);
213 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c
*i2c
)
217 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
218 writel(tmp
| S3C2410_IICCON_IRQEN
, i2c
->regs
+ S3C2410_IICCON
);
221 static bool is_ack(struct s3c24xx_i2c
*i2c
)
225 for (tries
= 50; tries
; --tries
) {
226 if (readl(i2c
->regs
+ S3C2410_IICCON
)
227 & S3C2410_IICCON_IRQPEND
) {
228 if (!(readl(i2c
->regs
+ S3C2410_IICSTAT
)
229 & S3C2410_IICSTAT_LASTBIT
))
232 usleep_range(1000, 2000);
234 dev_err(i2c
->dev
, "ack was not received\n");
239 * put the start of a message onto the bus
241 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c
*i2c
,
244 unsigned int addr
= (msg
->addr
& 0x7f) << 1;
246 unsigned long iiccon
;
249 stat
|= S3C2410_IICSTAT_TXRXEN
;
251 if (msg
->flags
& I2C_M_RD
) {
252 stat
|= S3C2410_IICSTAT_MASTER_RX
;
255 stat
|= S3C2410_IICSTAT_MASTER_TX
;
257 if (msg
->flags
& I2C_M_REV_DIR_ADDR
)
260 /* todo - check for whether ack wanted or not */
261 s3c24xx_i2c_enable_ack(i2c
);
263 iiccon
= readl(i2c
->regs
+ S3C2410_IICCON
);
264 writel(stat
, i2c
->regs
+ S3C2410_IICSTAT
);
266 dev_dbg(i2c
->dev
, "START: %08lx to IICSTAT, %02x to DS\n", stat
, addr
);
267 writeb(addr
, i2c
->regs
+ S3C2410_IICDS
);
270 * delay here to ensure the data byte has gotten onto the bus
271 * before the transaction is started
273 ndelay(i2c
->tx_setup
);
275 dev_dbg(i2c
->dev
, "iiccon, %08lx\n", iiccon
);
276 writel(iiccon
, i2c
->regs
+ S3C2410_IICCON
);
278 stat
|= S3C2410_IICSTAT_START
;
279 writel(stat
, i2c
->regs
+ S3C2410_IICSTAT
);
281 if (i2c
->quirks
& QUIRK_POLL
) {
282 while ((i2c
->msg_num
!= 0) && is_ack(i2c
)) {
283 i2c_s3c_irq_nextbyte(i2c
, stat
);
284 stat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
286 if (stat
& S3C2410_IICSTAT_ARBITR
)
287 dev_err(i2c
->dev
, "deal with arbitration loss\n");
292 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c
*i2c
, int ret
)
294 unsigned long iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
296 dev_dbg(i2c
->dev
, "STOP\n");
299 * The datasheet says that the STOP sequence should be:
300 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
301 * 2) I2CCON.4 = 0 - Clear IRQPEND
302 * 3) Wait until the stop condition takes effect.
303 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
305 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
307 * However, after much experimentation, it appears that:
308 * a) normal buses automatically clear BUSY and transition from
309 * Master->Slave when they complete generating a STOP condition.
310 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
311 * after starting the STOP generation here.
312 * b) HDMIPHY bus does neither, so there is no way to do step 3.
313 * There is no indication when this bus has finished generating
316 * In fact, we have found that as soon as the IRQPEND bit is cleared in
317 * step 2, the HDMIPHY bus generates the STOP condition, and then
318 * immediately starts transferring another data byte, even though the
319 * bus is supposedly stopped. This is presumably because the bus is
320 * still in "Master" mode, and its BUSY bit is still set.
322 * To avoid these extra post-STOP transactions on HDMI phy devices, we
323 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
324 * instead of first generating a proper STOP condition. This should
325 * float SDA & SCK terminating the transfer. Subsequent transfers
326 * start with a proper START condition, and proceed normally.
328 * The HDMIPHY bus is an internal bus that always has exactly two
329 * devices, the host as Master and the HDMIPHY device as the slave.
330 * Skipping the STOP condition has been tested on this bus and works.
332 if (i2c
->quirks
& QUIRK_HDMIPHY
) {
333 /* Stop driving the I2C pins */
334 iicstat
&= ~S3C2410_IICSTAT_TXRXEN
;
336 /* stop the transfer */
337 iicstat
&= ~S3C2410_IICSTAT_START
;
339 writel(iicstat
, i2c
->regs
+ S3C2410_IICSTAT
);
341 i2c
->state
= STATE_STOP
;
343 s3c24xx_i2c_master_complete(i2c
, ret
);
344 s3c24xx_i2c_disable_irq(i2c
);
348 * helper functions to determine the current state in the set of
349 * messages we are sending
353 * returns TRUE if the current message is the last in the set
355 static inline int is_lastmsg(struct s3c24xx_i2c
*i2c
)
357 return i2c
->msg_idx
>= (i2c
->msg_num
- 1);
361 * returns TRUE if we this is the last byte in the current message
363 static inline int is_msglast(struct s3c24xx_i2c
*i2c
)
366 * msg->len is always 1 for the first byte of smbus block read.
367 * Actual length will be read from slave. More bytes will be
368 * read according to the length then.
370 if (i2c
->msg
->flags
& I2C_M_RECV_LEN
&& i2c
->msg
->len
== 1)
373 return i2c
->msg_ptr
== i2c
->msg
->len
-1;
377 * returns TRUE if we reached the end of the current message
379 static inline int is_msgend(struct s3c24xx_i2c
*i2c
)
381 return i2c
->msg_ptr
>= i2c
->msg
->len
;
385 * process an interrupt and work out what to do
387 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c
*i2c
, unsigned long iicstat
)
393 switch (i2c
->state
) {
396 dev_err(i2c
->dev
, "%s: called in STATE_IDLE\n", __func__
);
400 dev_err(i2c
->dev
, "%s: called in STATE_STOP\n", __func__
);
401 s3c24xx_i2c_disable_irq(i2c
);
406 * last thing we did was send a start condition on the
407 * bus, or started a new i2c message
409 if (iicstat
& S3C2410_IICSTAT_LASTBIT
&&
410 !(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
)) {
411 /* ack was not received... */
412 dev_dbg(i2c
->dev
, "ack was not received\n");
413 s3c24xx_i2c_stop(i2c
, -ENXIO
);
417 if (i2c
->msg
->flags
& I2C_M_RD
)
418 i2c
->state
= STATE_READ
;
420 i2c
->state
= STATE_WRITE
;
423 * Terminate the transfer if there is nothing to do
424 * as this is used by the i2c probe to find devices.
426 if (is_lastmsg(i2c
) && i2c
->msg
->len
== 0) {
427 s3c24xx_i2c_stop(i2c
, 0);
431 if (i2c
->state
== STATE_READ
)
435 * fall through to the write state, as we will need to
436 * send a byte as well
441 * we are writing data to the device... check for the
442 * end of the message, and if so, work out what to do
444 if (!(i2c
->msg
->flags
& I2C_M_IGNORE_NAK
)) {
445 if (iicstat
& S3C2410_IICSTAT_LASTBIT
) {
446 dev_dbg(i2c
->dev
, "WRITE: No Ack\n");
448 s3c24xx_i2c_stop(i2c
, -ECONNREFUSED
);
455 if (!is_msgend(i2c
)) {
456 byte
= i2c
->msg
->buf
[i2c
->msg_ptr
++];
457 writeb(byte
, i2c
->regs
+ S3C2410_IICDS
);
460 * delay after writing the byte to allow the
461 * data setup time on the bus, as writing the
462 * data to the register causes the first bit
463 * to appear on SDA, and SCL will change as
464 * soon as the interrupt is acknowledged
466 ndelay(i2c
->tx_setup
);
468 } else if (!is_lastmsg(i2c
)) {
469 /* we need to go to the next i2c message */
471 dev_dbg(i2c
->dev
, "WRITE: Next Message\n");
477 /* check to see if we need to do another message */
478 if (i2c
->msg
->flags
& I2C_M_NOSTART
) {
480 if (i2c
->msg
->flags
& I2C_M_RD
) {
482 * cannot do this, the controller
483 * forces us to send a new START
484 * when we change direction
486 s3c24xx_i2c_stop(i2c
, -EINVAL
);
491 /* send the new start */
492 s3c24xx_i2c_message_start(i2c
, i2c
->msg
);
493 i2c
->state
= STATE_START
;
498 s3c24xx_i2c_stop(i2c
, 0);
504 * we have a byte of data in the data register, do
505 * something with it, and then work out whether we are
506 * going to do any more read/write
508 byte
= readb(i2c
->regs
+ S3C2410_IICDS
);
509 i2c
->msg
->buf
[i2c
->msg_ptr
++] = byte
;
511 /* Add actual length to read for smbus block read */
512 if (i2c
->msg
->flags
& I2C_M_RECV_LEN
&& i2c
->msg
->len
== 1)
513 i2c
->msg
->len
+= byte
;
515 if (is_msglast(i2c
)) {
516 /* last byte of buffer */
519 s3c24xx_i2c_disable_ack(i2c
);
521 } else if (is_msgend(i2c
)) {
523 * ok, we've read the entire buffer, see if there
524 * is anything else we need to do
526 if (is_lastmsg(i2c
)) {
527 /* last message, send stop and complete */
528 dev_dbg(i2c
->dev
, "READ: Send Stop\n");
530 s3c24xx_i2c_stop(i2c
, 0);
532 /* go to the next transfer */
533 dev_dbg(i2c
->dev
, "READ: Next Transfer\n");
544 /* acknowlegde the IRQ and get back on with the work */
547 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
548 tmp
&= ~S3C2410_IICCON_IRQPEND
;
549 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
555 * top level IRQ servicing routine
557 static irqreturn_t
s3c24xx_i2c_irq(int irqno
, void *dev_id
)
559 struct s3c24xx_i2c
*i2c
= dev_id
;
560 unsigned long status
;
563 status
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
565 if (status
& S3C2410_IICSTAT_ARBITR
) {
566 /* deal with arbitration loss */
567 dev_err(i2c
->dev
, "deal with arbitration loss\n");
570 if (i2c
->state
== STATE_IDLE
) {
571 dev_dbg(i2c
->dev
, "IRQ: error i2c->state == IDLE\n");
573 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
574 tmp
&= ~S3C2410_IICCON_IRQPEND
;
575 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
580 * pretty much this leaves us with the fact that we've
581 * transmitted or received whatever byte we last sent
583 i2c_s3c_irq_nextbyte(i2c
, status
);
590 * Disable the bus so that we won't get any interrupts from now on, or try
591 * to drive any lines. This is the default state when we don't have
592 * anything to send/receive.
594 * If there is an event on the bus, or we have a pre-existing event at
595 * kernel boot time, we may not notice the event and the I2C controller
596 * will lock the bus with the I2C clock line low indefinitely.
598 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c
*i2c
)
602 /* Stop driving the I2C pins */
603 tmp
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
604 tmp
&= ~S3C2410_IICSTAT_TXRXEN
;
605 writel(tmp
, i2c
->regs
+ S3C2410_IICSTAT
);
607 /* We don't expect any interrupts now, and don't want send acks */
608 tmp
= readl(i2c
->regs
+ S3C2410_IICCON
);
609 tmp
&= ~(S3C2410_IICCON_IRQEN
| S3C2410_IICCON_IRQPEND
|
610 S3C2410_IICCON_ACKEN
);
611 writel(tmp
, i2c
->regs
+ S3C2410_IICCON
);
616 * get the i2c bus for a master transaction
618 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c
*i2c
)
620 unsigned long iicstat
;
623 while (timeout
-- > 0) {
624 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
626 if (!(iicstat
& S3C2410_IICSTAT_BUSBUSY
))
636 * wait for the i2c bus to become idle.
638 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c
*i2c
)
640 unsigned long iicstat
;
645 /* ensure the stop has been through the bus */
647 dev_dbg(i2c
->dev
, "waiting for bus idle\n");
649 start
= now
= ktime_get();
652 * Most of the time, the bus is already idle within a few usec of the
653 * end of a transaction. However, really slow i2c devices can stretch
654 * the clock, delaying STOP generation.
656 * On slower SoCs this typically happens within a very small number of
657 * instructions so busy wait briefly to avoid scheduling overhead.
660 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
661 while ((iicstat
& S3C2410_IICSTAT_START
) && --spins
) {
663 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
667 * If we do get an appreciable delay as a compromise between idle
668 * detection latency for the normal, fast case, and system load in the
669 * slow device case, use an exponential back off in the polling loop,
670 * up to 1/10th of the total timeout, then continue to poll at a
671 * constant rate up to the timeout.
674 while ((iicstat
& S3C2410_IICSTAT_START
) &&
675 ktime_us_delta(now
, start
) < S3C2410_IDLE_TIMEOUT
) {
676 usleep_range(delay
, 2 * delay
);
677 if (delay
< S3C2410_IDLE_TIMEOUT
/ 10)
680 iicstat
= readl(i2c
->regs
+ S3C2410_IICSTAT
);
683 if (iicstat
& S3C2410_IICSTAT_START
)
684 dev_warn(i2c
->dev
, "timeout waiting for bus idle\n");
688 * this starts an i2c transfer
690 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c
*i2c
,
691 struct i2c_msg
*msgs
, int num
)
693 unsigned long timeout
;
696 ret
= s3c24xx_i2c_set_master(i2c
);
698 dev_err(i2c
->dev
, "cannot get bus (error %d)\n", ret
);
707 i2c
->state
= STATE_START
;
709 s3c24xx_i2c_enable_irq(i2c
);
710 s3c24xx_i2c_message_start(i2c
, msgs
);
712 if (i2c
->quirks
& QUIRK_POLL
) {
716 dev_dbg(i2c
->dev
, "incomplete xfer (%d)\n", ret
);
721 timeout
= wait_event_timeout(i2c
->wait
, i2c
->msg_num
== 0, HZ
* 5);
726 * Having these next two as dev_err() makes life very
727 * noisy when doing an i2cdetect
730 dev_dbg(i2c
->dev
, "timeout\n");
732 dev_dbg(i2c
->dev
, "incomplete xfer (%d)\n", ret
);
734 /* For QUIRK_HDMIPHY, bus is already disabled */
735 if (i2c
->quirks
& QUIRK_HDMIPHY
)
738 s3c24xx_i2c_wait_idle(i2c
);
740 s3c24xx_i2c_disable_bus(i2c
);
743 i2c
->state
= STATE_IDLE
;
749 * first port of call from the i2c bus code when an message needs
750 * transferring across the i2c bus.
752 static int s3c24xx_i2c_xfer(struct i2c_adapter
*adap
,
753 struct i2c_msg
*msgs
, int num
)
755 struct s3c24xx_i2c
*i2c
= (struct s3c24xx_i2c
*)adap
->algo_data
;
759 ret
= clk_enable(i2c
->clk
);
763 for (retry
= 0; retry
< adap
->retries
; retry
++) {
765 ret
= s3c24xx_i2c_doxfer(i2c
, msgs
, num
);
767 if (ret
!= -EAGAIN
) {
768 clk_disable(i2c
->clk
);
772 dev_dbg(i2c
->dev
, "Retrying transmission (%d)\n", retry
);
777 clk_disable(i2c
->clk
);
781 /* declare our i2c functionality */
782 static u32
s3c24xx_i2c_func(struct i2c_adapter
*adap
)
784 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
| I2C_FUNC_NOSTART
|
785 I2C_FUNC_PROTOCOL_MANGLING
;
788 /* i2c bus registration info */
789 static const struct i2c_algorithm s3c24xx_i2c_algorithm
= {
790 .master_xfer
= s3c24xx_i2c_xfer
,
791 .functionality
= s3c24xx_i2c_func
,
795 * return the divisor settings for a given frequency
797 static int s3c24xx_i2c_calcdivisor(unsigned long clkin
, unsigned int wanted
,
798 unsigned int *div1
, unsigned int *divs
)
800 unsigned int calc_divs
= clkin
/ wanted
;
801 unsigned int calc_div1
;
803 if (calc_divs
> (16*16))
808 calc_divs
+= calc_div1
-1;
809 calc_divs
/= calc_div1
;
819 return clkin
/ (calc_divs
* calc_div1
);
823 * work out a divisor for the user requested frequency setting,
824 * either by the requested frequency, or scanning the acceptable
825 * range of frequencies until something is found
827 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c
*i2c
, unsigned int *got
)
829 struct s3c2410_platform_i2c
*pdata
= i2c
->pdata
;
830 unsigned long clkin
= clk_get_rate(i2c
->clk
);
831 unsigned int divs
, div1
;
832 unsigned long target_frequency
;
836 i2c
->clkrate
= clkin
;
837 clkin
/= 1000; /* clkin now in KHz */
839 dev_dbg(i2c
->dev
, "pdata desired frequency %lu\n", pdata
->frequency
);
841 target_frequency
= pdata
->frequency
? pdata
->frequency
: 100000;
843 target_frequency
/= 1000; /* Target frequency now in KHz */
845 freq
= s3c24xx_i2c_calcdivisor(clkin
, target_frequency
, &div1
, &divs
);
847 if (freq
> target_frequency
) {
849 "Unable to achieve desired frequency %luKHz." \
850 " Lowest achievable %dKHz\n", target_frequency
, freq
);
856 iiccon
= readl(i2c
->regs
+ S3C2410_IICCON
);
857 iiccon
&= ~(S3C2410_IICCON_SCALEMASK
| S3C2410_IICCON_TXDIV_512
);
861 iiccon
|= S3C2410_IICCON_TXDIV_512
;
863 if (i2c
->quirks
& QUIRK_POLL
)
864 iiccon
|= S3C2410_IICCON_SCALE(2);
866 writel(iiccon
, i2c
->regs
+ S3C2410_IICCON
);
868 if (i2c
->quirks
& QUIRK_S3C2440
) {
869 unsigned long sda_delay
;
871 if (pdata
->sda_delay
) {
872 sda_delay
= clkin
* pdata
->sda_delay
;
873 sda_delay
= DIV_ROUND_UP(sda_delay
, 1000000);
874 sda_delay
= DIV_ROUND_UP(sda_delay
, 5);
877 sda_delay
|= S3C2410_IICLC_FILTER_ON
;
881 dev_dbg(i2c
->dev
, "IICLC=%08lx\n", sda_delay
);
882 writel(sda_delay
, i2c
->regs
+ S3C2440_IICLC
);
888 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
890 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
892 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block
*nb
,
893 unsigned long val
, void *data
)
895 struct s3c24xx_i2c
*i2c
= freq_to_i2c(nb
);
900 delta_f
= clk_get_rate(i2c
->clk
) - i2c
->clkrate
;
902 /* if we're post-change and the input clock has slowed down
903 * or at pre-change and the clock is about to speed up, then
904 * adjust our clock rate. <0 is slow, >0 speedup.
907 if ((val
== CPUFREQ_POSTCHANGE
&& delta_f
< 0) ||
908 (val
== CPUFREQ_PRECHANGE
&& delta_f
> 0)) {
909 i2c_lock_bus(&i2c
->adap
, I2C_LOCK_ROOT_ADAPTER
);
910 ret
= s3c24xx_i2c_clockrate(i2c
, &got
);
911 i2c_unlock_bus(&i2c
->adap
, I2C_LOCK_ROOT_ADAPTER
);
914 dev_err(i2c
->dev
, "cannot find frequency (%d)\n", ret
);
916 dev_info(i2c
->dev
, "setting freq %d\n", got
);
922 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c
*i2c
)
924 i2c
->freq_transition
.notifier_call
= s3c24xx_i2c_cpufreq_transition
;
926 return cpufreq_register_notifier(&i2c
->freq_transition
,
927 CPUFREQ_TRANSITION_NOTIFIER
);
930 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c
*i2c
)
932 cpufreq_unregister_notifier(&i2c
->freq_transition
,
933 CPUFREQ_TRANSITION_NOTIFIER
);
937 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c
*i2c
)
942 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c
*i2c
)
948 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c
*i2c
)
952 if (i2c
->quirks
& QUIRK_NO_GPIO
)
955 for (i
= 0; i
< 2; i
++) {
956 i2c
->gpios
[i
] = devm_gpiod_get_index(i2c
->dev
, NULL
,
958 if (IS_ERR(i2c
->gpios
[i
])) {
959 dev_err(i2c
->dev
, "i2c gpio invalid at index %d\n", i
);
967 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c
*i2c
)
974 * initialise the controller, set the IO lines and frequency
976 static int s3c24xx_i2c_init(struct s3c24xx_i2c
*i2c
)
978 struct s3c2410_platform_i2c
*pdata
;
981 /* get the plafrom data */
985 /* write slave address */
987 writeb(pdata
->slave_addr
, i2c
->regs
+ S3C2410_IICADD
);
989 dev_info(i2c
->dev
, "slave address 0x%02x\n", pdata
->slave_addr
);
991 writel(0, i2c
->regs
+ S3C2410_IICCON
);
992 writel(0, i2c
->regs
+ S3C2410_IICSTAT
);
994 /* we need to work out the divisors for the clock... */
996 if (s3c24xx_i2c_clockrate(i2c
, &freq
) != 0) {
997 dev_err(i2c
->dev
, "cannot meet bus frequency required\n");
1001 /* todo - check that the i2c lines aren't being dragged anywhere */
1003 dev_info(i2c
->dev
, "bus frequency set to %d KHz\n", freq
);
1004 dev_dbg(i2c
->dev
, "S3C2410_IICCON=0x%02x\n",
1005 readl(i2c
->regs
+ S3C2410_IICCON
));
1012 * Parse the device tree node and retreive the platform data.
1015 s3c24xx_i2c_parse_dt(struct device_node
*np
, struct s3c24xx_i2c
*i2c
)
1017 struct s3c2410_platform_i2c
*pdata
= i2c
->pdata
;
1023 pdata
->bus_num
= -1; /* i2c bus number is dynamically assigned */
1024 of_property_read_u32(np
, "samsung,i2c-sda-delay", &pdata
->sda_delay
);
1025 of_property_read_u32(np
, "samsung,i2c-slave-addr", &pdata
->slave_addr
);
1026 of_property_read_u32(np
, "samsung,i2c-max-bus-freq",
1027 (u32
*)&pdata
->frequency
);
1029 * Exynos5's legacy i2c controller and new high speed i2c
1030 * controller have muxed interrupt sources. By default the
1031 * interrupts for 4-channel HS-I2C controller are enabled.
1032 * If nodes for first four channels of legacy i2c controller
1033 * are available then re-configure the interrupts via the
1036 id
= of_alias_get_id(np
, "i2c");
1037 i2c
->sysreg
= syscon_regmap_lookup_by_phandle(np
,
1038 "samsung,sysreg-phandle");
1039 if (IS_ERR(i2c
->sysreg
))
1042 regmap_update_bits(i2c
->sysreg
, EXYNOS5_SYS_I2C_CFG
, BIT(id
), 0);
1046 s3c24xx_i2c_parse_dt(struct device_node
*np
, struct s3c24xx_i2c
*i2c
) { }
1049 static int s3c24xx_i2c_probe(struct platform_device
*pdev
)
1051 struct s3c24xx_i2c
*i2c
;
1052 struct s3c2410_platform_i2c
*pdata
= NULL
;
1053 struct resource
*res
;
1056 if (!pdev
->dev
.of_node
) {
1057 pdata
= dev_get_platdata(&pdev
->dev
);
1059 dev_err(&pdev
->dev
, "no platform data\n");
1064 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c24xx_i2c
), GFP_KERNEL
);
1068 i2c
->pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1072 i2c
->quirks
= s3c24xx_get_device_quirks(pdev
);
1073 i2c
->sysreg
= ERR_PTR(-ENOENT
);
1075 memcpy(i2c
->pdata
, pdata
, sizeof(*pdata
));
1077 s3c24xx_i2c_parse_dt(pdev
->dev
.of_node
, i2c
);
1079 strlcpy(i2c
->adap
.name
, "s3c2410-i2c", sizeof(i2c
->adap
.name
));
1080 i2c
->adap
.owner
= THIS_MODULE
;
1081 i2c
->adap
.algo
= &s3c24xx_i2c_algorithm
;
1082 i2c
->adap
.retries
= 2;
1083 i2c
->adap
.class = I2C_CLASS_DEPRECATED
;
1086 init_waitqueue_head(&i2c
->wait
);
1088 /* find the clock and enable it */
1089 i2c
->dev
= &pdev
->dev
;
1090 i2c
->clk
= devm_clk_get(&pdev
->dev
, "i2c");
1091 if (IS_ERR(i2c
->clk
)) {
1092 dev_err(&pdev
->dev
, "cannot get clock\n");
1096 dev_dbg(&pdev
->dev
, "clock source %p\n", i2c
->clk
);
1098 /* map the registers */
1099 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1100 i2c
->regs
= devm_ioremap_resource(&pdev
->dev
, res
);
1102 if (IS_ERR(i2c
->regs
))
1103 return PTR_ERR(i2c
->regs
);
1105 dev_dbg(&pdev
->dev
, "registers %p (%p)\n",
1108 /* setup info block for the i2c core */
1109 i2c
->adap
.algo_data
= i2c
;
1110 i2c
->adap
.dev
.parent
= &pdev
->dev
;
1111 i2c
->pctrl
= devm_pinctrl_get_select_default(i2c
->dev
);
1113 /* inititalise the i2c gpio lines */
1114 if (i2c
->pdata
->cfg_gpio
)
1115 i2c
->pdata
->cfg_gpio(to_platform_device(i2c
->dev
));
1116 else if (IS_ERR(i2c
->pctrl
) && s3c24xx_i2c_parse_dt_gpio(i2c
))
1119 /* initialise the i2c controller */
1120 ret
= clk_prepare_enable(i2c
->clk
);
1122 dev_err(&pdev
->dev
, "I2C clock enable failed\n");
1126 ret
= s3c24xx_i2c_init(i2c
);
1127 clk_disable(i2c
->clk
);
1129 dev_err(&pdev
->dev
, "I2C controller init failed\n");
1130 clk_unprepare(i2c
->clk
);
1135 * find the IRQ for this unit (note, this relies on the init call to
1136 * ensure no current IRQs pending
1138 if (!(i2c
->quirks
& QUIRK_POLL
)) {
1139 i2c
->irq
= ret
= platform_get_irq(pdev
, 0);
1141 dev_err(&pdev
->dev
, "cannot find IRQ\n");
1142 clk_unprepare(i2c
->clk
);
1146 ret
= devm_request_irq(&pdev
->dev
, i2c
->irq
, s3c24xx_i2c_irq
,
1147 0, dev_name(&pdev
->dev
), i2c
);
1149 dev_err(&pdev
->dev
, "cannot claim IRQ %d\n", i2c
->irq
);
1150 clk_unprepare(i2c
->clk
);
1155 ret
= s3c24xx_i2c_register_cpufreq(i2c
);
1157 dev_err(&pdev
->dev
, "failed to register cpufreq notifier\n");
1158 clk_unprepare(i2c
->clk
);
1163 * Note, previous versions of the driver used i2c_add_adapter()
1164 * to add the bus at any number. We now pass the bus number via
1165 * the platform data, so if unset it will now default to always
1168 i2c
->adap
.nr
= i2c
->pdata
->bus_num
;
1169 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
1171 platform_set_drvdata(pdev
, i2c
);
1173 pm_runtime_enable(&pdev
->dev
);
1175 ret
= i2c_add_numbered_adapter(&i2c
->adap
);
1177 pm_runtime_disable(&pdev
->dev
);
1178 s3c24xx_i2c_deregister_cpufreq(i2c
);
1179 clk_unprepare(i2c
->clk
);
1183 dev_info(&pdev
->dev
, "%s: S3C I2C adapter\n", dev_name(&i2c
->adap
.dev
));
1187 static int s3c24xx_i2c_remove(struct platform_device
*pdev
)
1189 struct s3c24xx_i2c
*i2c
= platform_get_drvdata(pdev
);
1191 clk_unprepare(i2c
->clk
);
1193 pm_runtime_disable(&pdev
->dev
);
1195 s3c24xx_i2c_deregister_cpufreq(i2c
);
1197 i2c_del_adapter(&i2c
->adap
);
1202 #ifdef CONFIG_PM_SLEEP
1203 static int s3c24xx_i2c_suspend_noirq(struct device
*dev
)
1205 struct s3c24xx_i2c
*i2c
= dev_get_drvdata(dev
);
1207 i2c_mark_adapter_suspended(&i2c
->adap
);
1209 if (!IS_ERR(i2c
->sysreg
))
1210 regmap_read(i2c
->sysreg
, EXYNOS5_SYS_I2C_CFG
, &i2c
->sys_i2c_cfg
);
1215 static int s3c24xx_i2c_resume_noirq(struct device
*dev
)
1217 struct s3c24xx_i2c
*i2c
= dev_get_drvdata(dev
);
1220 if (!IS_ERR(i2c
->sysreg
))
1221 regmap_write(i2c
->sysreg
, EXYNOS5_SYS_I2C_CFG
, i2c
->sys_i2c_cfg
);
1223 ret
= clk_enable(i2c
->clk
);
1226 s3c24xx_i2c_init(i2c
);
1227 clk_disable(i2c
->clk
);
1228 i2c_mark_adapter_resumed(&i2c
->adap
);
1235 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops
= {
1236 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq
,
1237 s3c24xx_i2c_resume_noirq
)
1240 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1242 #define S3C24XX_DEV_PM_OPS NULL
1245 static struct platform_driver s3c24xx_i2c_driver
= {
1246 .probe
= s3c24xx_i2c_probe
,
1247 .remove
= s3c24xx_i2c_remove
,
1248 .id_table
= s3c24xx_driver_ids
,
1251 .pm
= S3C24XX_DEV_PM_OPS
,
1252 .of_match_table
= of_match_ptr(s3c24xx_i2c_match
),
1256 static int __init
i2c_adap_s3c_init(void)
1258 return platform_driver_register(&s3c24xx_i2c_driver
);
1260 subsys_initcall(i2c_adap_s3c_init
);
1262 static void __exit
i2c_adap_s3c_exit(void)
1264 platform_driver_unregister(&s3c24xx_i2c_driver
);
1266 module_exit(i2c_adap_s3c_exit
);
1268 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1269 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1270 MODULE_LICENSE("GPL");