2 * TI DaVinci (TMS320DM644x) I2C driver.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
7 * --------------------------------------------------------
9 * SPDX-License-Identifier: GPL-2.0+
11 * NOTE: This driver should be converted to driver model before June 2017.
12 * Please see doc/driver-model/i2c-howto.txt for instructions.
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/i2c_defs.h>
21 #include "davinci_i2c.h"
24 /* Information about i2c controller */
28 struct i2c_regs
*regs
;
32 #define CHECK_NACK() \
34 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
35 REG(&(i2c_base->i2c_con)) = 0;\
40 static int _wait_for_bus(struct i2c_regs
*i2c_base
)
44 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
46 for (timeout
= 0; timeout
< 10; timeout
++) {
47 stat
= REG(&(i2c_base
->i2c_stat
));
48 if (!((stat
) & I2C_STAT_BB
)) {
49 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
53 REG(&(i2c_base
->i2c_stat
)) = stat
;
57 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
61 static int _poll_i2c_irq(struct i2c_regs
*i2c_base
, int mask
)
65 for (timeout
= 0; timeout
< 10; timeout
++) {
67 stat
= REG(&(i2c_base
->i2c_stat
));
72 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
73 return stat
| I2C_TIMEOUT
;
76 static void _flush_rx(struct i2c_regs
*i2c_base
)
79 if (!(REG(&(i2c_base
->i2c_stat
)) & I2C_STAT_RRDY
))
82 REG(&(i2c_base
->i2c_drr
));
83 REG(&(i2c_base
->i2c_stat
)) = I2C_STAT_RRDY
;
88 static uint
_davinci_i2c_setspeed(struct i2c_regs
*i2c_base
,
95 div
= (CONFIG_SYS_HZ_CLOCK
/ ((psc
+ 1) * speed
)) - 10;
96 REG(&(i2c_base
->i2c_psc
)) = psc
; /* 27MHz / (2 + 1) = 9MHz */
97 REG(&(i2c_base
->i2c_scll
)) = (div
* 50) / 100; /* 50% Duty */
98 REG(&(i2c_base
->i2c_sclh
)) = div
- REG(&(i2c_base
->i2c_scll
));
103 static void _davinci_i2c_init(struct i2c_regs
*i2c_base
,
104 uint speed
, int slaveadd
)
106 if (REG(&(i2c_base
->i2c_con
)) & I2C_CON_EN
) {
107 REG(&(i2c_base
->i2c_con
)) = 0;
111 _davinci_i2c_setspeed(i2c_base
, speed
);
113 REG(&(i2c_base
->i2c_oa
)) = slaveadd
;
114 REG(&(i2c_base
->i2c_cnt
)) = 0;
116 /* Interrupts must be enabled or I2C module won't work */
117 REG(&(i2c_base
->i2c_ie
)) = I2C_IE_SCD_IE
| I2C_IE_XRDY_IE
|
118 I2C_IE_RRDY_IE
| I2C_IE_ARDY_IE
| I2C_IE_NACK_IE
;
120 /* Now enable I2C controller (get it out of reset) */
121 REG(&(i2c_base
->i2c_con
)) = I2C_CON_EN
;
126 static int _davinci_i2c_read(struct i2c_regs
*i2c_base
, uint8_t chip
,
127 uint32_t addr
, int alen
, uint8_t *buf
, int len
)
132 if ((alen
< 0) || (alen
> 2)) {
133 printf("%s(): bogus address length %x\n", __func__
, alen
);
137 if (_wait_for_bus(i2c_base
))
141 /* Start address phase */
142 tmp
= I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_TRX
;
143 REG(&(i2c_base
->i2c_cnt
)) = alen
;
144 REG(&(i2c_base
->i2c_sa
)) = chip
;
145 REG(&(i2c_base
->i2c_con
)) = tmp
;
147 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_XRDY
| I2C_STAT_NACK
);
153 /* Send address MSByte */
154 if (tmp
& I2C_STAT_XRDY
) {
155 REG(&(i2c_base
->i2c_dxr
)) = (addr
>> 8) & 0xff;
157 REG(&(i2c_base
->i2c_con
)) = 0;
161 tmp
= _poll_i2c_irq(i2c_base
,
162 I2C_STAT_XRDY
| I2C_STAT_NACK
);
165 /* No break, fall through */
167 /* Send address LSByte */
168 if (tmp
& I2C_STAT_XRDY
) {
169 REG(&(i2c_base
->i2c_dxr
)) = addr
& 0xff;
171 REG(&(i2c_base
->i2c_con
)) = 0;
175 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_XRDY
|
176 I2C_STAT_NACK
| I2C_STAT_ARDY
);
180 if (!(tmp
& I2C_STAT_ARDY
)) {
181 REG(&(i2c_base
->i2c_con
)) = 0;
187 /* Address phase is over, now read 'len' bytes and stop */
188 tmp
= I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_STP
;
189 REG(&(i2c_base
->i2c_cnt
)) = len
& 0xffff;
190 REG(&(i2c_base
->i2c_sa
)) = chip
;
191 REG(&(i2c_base
->i2c_con
)) = tmp
;
193 for (i
= 0; i
< len
; i
++) {
194 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_RRDY
| I2C_STAT_NACK
|
199 if (tmp
& I2C_STAT_RRDY
) {
200 buf
[i
] = REG(&(i2c_base
->i2c_drr
));
202 REG(&(i2c_base
->i2c_con
)) = 0;
207 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_SCD
| I2C_STAT_NACK
);
211 if (!(tmp
& I2C_STAT_SCD
)) {
212 REG(&(i2c_base
->i2c_con
)) = 0;
217 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
218 REG(&(i2c_base
->i2c_cnt
)) = 0;
219 REG(&(i2c_base
->i2c_con
)) = 0;
224 static int _davinci_i2c_write(struct i2c_regs
*i2c_base
, uint8_t chip
,
225 uint32_t addr
, int alen
, uint8_t *buf
, int len
)
230 if ((alen
< 0) || (alen
> 2)) {
231 printf("%s(): bogus address length %x\n", __func__
, alen
);
235 printf("%s(): bogus length %x\n", __func__
, len
);
239 if (_wait_for_bus(i2c_base
))
242 /* Start address phase */
243 tmp
= I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
|
244 I2C_CON_TRX
| I2C_CON_STP
;
245 REG(&(i2c_base
->i2c_cnt
)) = (alen
== 0) ?
246 len
& 0xffff : (len
& 0xffff) + alen
;
247 REG(&(i2c_base
->i2c_sa
)) = chip
;
248 REG(&(i2c_base
->i2c_con
)) = tmp
;
252 /* Send address MSByte */
253 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_XRDY
| I2C_STAT_NACK
);
257 if (tmp
& I2C_STAT_XRDY
) {
258 REG(&(i2c_base
->i2c_dxr
)) = (addr
>> 8) & 0xff;
260 REG(&(i2c_base
->i2c_con
)) = 0;
263 /* No break, fall through */
265 /* Send address LSByte */
266 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_XRDY
| I2C_STAT_NACK
);
270 if (tmp
& I2C_STAT_XRDY
) {
271 REG(&(i2c_base
->i2c_dxr
)) = addr
& 0xff;
273 REG(&(i2c_base
->i2c_con
)) = 0;
278 for (i
= 0; i
< len
; i
++) {
279 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_XRDY
| I2C_STAT_NACK
);
283 if (tmp
& I2C_STAT_XRDY
)
284 REG(&(i2c_base
->i2c_dxr
)) = buf
[i
];
289 tmp
= _poll_i2c_irq(i2c_base
, I2C_STAT_SCD
| I2C_STAT_NACK
);
293 if (!(tmp
& I2C_STAT_SCD
)) {
294 REG(&(i2c_base
->i2c_con
)) = 0;
299 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
300 REG(&(i2c_base
->i2c_cnt
)) = 0;
301 REG(&(i2c_base
->i2c_con
)) = 0;
306 static int _davinci_i2c_probe_chip(struct i2c_regs
*i2c_base
, uint8_t chip
)
310 if (chip
== REG(&(i2c_base
->i2c_oa
)))
313 REG(&(i2c_base
->i2c_con
)) = 0;
314 if (_wait_for_bus(i2c_base
))
317 /* try to read one byte from current (or only) address */
318 REG(&(i2c_base
->i2c_cnt
)) = 1;
319 REG(&(i2c_base
->i2c_sa
)) = chip
;
320 REG(&(i2c_base
->i2c_con
)) = (I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
|
324 if (!(REG(&(i2c_base
->i2c_stat
)) & I2C_STAT_NACK
)) {
327 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
329 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
330 REG(&(i2c_base
->i2c_con
)) |= I2C_CON_STP
;
332 if (_wait_for_bus(i2c_base
))
337 REG(&(i2c_base
->i2c_stat
)) = 0xffff;
338 REG(&(i2c_base
->i2c_cnt
)) = 0;
342 #ifndef CONFIG_DM_I2C
343 static struct i2c_regs
*davinci_get_base(struct i2c_adapter
*adap
)
345 switch (adap
->hwadapnr
) {
346 #if CONFIG_SYS_I2C_BUS_MAX >= 3
348 return (struct i2c_regs
*)I2C2_BASE
;
350 #if CONFIG_SYS_I2C_BUS_MAX >= 2
352 return (struct i2c_regs
*)I2C1_BASE
;
355 return (struct i2c_regs
*)I2C_BASE
;
358 printf("wrong hwadapnr: %d\n", adap
->hwadapnr
);
364 static uint
davinci_i2c_setspeed(struct i2c_adapter
*adap
, uint speed
)
366 struct i2c_regs
*i2c_base
= davinci_get_base(adap
);
370 ret
= _davinci_i2c_setspeed(i2c_base
, speed
);
375 static void davinci_i2c_init(struct i2c_adapter
*adap
, int speed
,
378 struct i2c_regs
*i2c_base
= davinci_get_base(adap
);
381 _davinci_i2c_init(i2c_base
, speed
, slaveadd
);
386 static int davinci_i2c_read(struct i2c_adapter
*adap
, uint8_t chip
,
387 uint32_t addr
, int alen
, uint8_t *buf
, int len
)
389 struct i2c_regs
*i2c_base
= davinci_get_base(adap
);
390 return _davinci_i2c_read(i2c_base
, chip
, addr
, alen
, buf
, len
);
393 static int davinci_i2c_write(struct i2c_adapter
*adap
, uint8_t chip
,
394 uint32_t addr
, int alen
, uint8_t *buf
, int len
)
396 struct i2c_regs
*i2c_base
= davinci_get_base(adap
);
398 return _davinci_i2c_write(i2c_base
, chip
, addr
, alen
, buf
, len
);
401 static int davinci_i2c_probe_chip(struct i2c_adapter
*adap
, uint8_t chip
)
403 struct i2c_regs
*i2c_base
= davinci_get_base(adap
);
405 return _davinci_i2c_probe_chip(i2c_base
, chip
);
408 U_BOOT_I2C_ADAP_COMPLETE(davinci_0
, davinci_i2c_init
, davinci_i2c_probe_chip
,
409 davinci_i2c_read
, davinci_i2c_write
,
410 davinci_i2c_setspeed
,
411 CONFIG_SYS_DAVINCI_I2C_SPEED
,
412 CONFIG_SYS_DAVINCI_I2C_SLAVE
,
415 #if CONFIG_SYS_I2C_BUS_MAX >= 2
416 U_BOOT_I2C_ADAP_COMPLETE(davinci_1
, davinci_i2c_init
, davinci_i2c_probe_chip
,
417 davinci_i2c_read
, davinci_i2c_write
,
418 davinci_i2c_setspeed
,
419 CONFIG_SYS_DAVINCI_I2C_SPEED1
,
420 CONFIG_SYS_DAVINCI_I2C_SLAVE1
,
424 #if CONFIG_SYS_I2C_BUS_MAX >= 3
425 U_BOOT_I2C_ADAP_COMPLETE(davinci_2
, davinci_i2c_init
, davinci_i2c_probe_chip
,
426 davinci_i2c_read
, davinci_i2c_write
,
427 davinci_i2c_setspeed
,
428 CONFIG_SYS_DAVINCI_I2C_SPEED2
,
429 CONFIG_SYS_DAVINCI_I2C_SLAVE2
,
433 #else /* CONFIG_DM_I2C */
435 static int davinci_i2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
,
438 struct i2c_bus
*i2c_bus
= dev_get_priv(bus
);
441 debug("i2c_xfer: %d messages\n", nmsgs
);
442 for (; nmsgs
> 0; nmsgs
--, msg
++) {
443 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
444 if (msg
->flags
& I2C_M_RD
) {
445 ret
= _davinci_i2c_read(i2c_bus
->regs
, msg
->addr
,
446 0, 0, msg
->buf
, msg
->len
);
448 ret
= _davinci_i2c_write(i2c_bus
->regs
, msg
->addr
,
449 0, 0, msg
->buf
, msg
->len
);
452 debug("i2c_write: error sending\n");
460 static int davinci_i2c_set_speed(struct udevice
*dev
, uint speed
)
462 struct i2c_bus
*i2c_bus
= dev_get_priv(dev
);
464 i2c_bus
->speed
= speed
;
465 return _davinci_i2c_setspeed(i2c_bus
->regs
, speed
);
468 static int davinci_i2c_probe(struct udevice
*dev
)
470 struct i2c_bus
*i2c_bus
= dev_get_priv(dev
);
472 i2c_bus
->id
= dev
->seq
;
473 i2c_bus
->regs
= (struct i2c_regs
*)devfdt_get_addr(dev
);
475 i2c_bus
->speed
= 100000;
476 _davinci_i2c_init(i2c_bus
->regs
, i2c_bus
->speed
, 0);
481 static int davinci_i2c_probe_chip(struct udevice
*bus
, uint chip_addr
,
484 struct i2c_bus
*i2c_bus
= dev_get_priv(bus
);
486 return _davinci_i2c_probe_chip(i2c_bus
->regs
, chip_addr
);
489 static const struct dm_i2c_ops davinci_i2c_ops
= {
490 .xfer
= davinci_i2c_xfer
,
491 .probe_chip
= davinci_i2c_probe_chip
,
492 .set_bus_speed
= davinci_i2c_set_speed
,
495 static const struct udevice_id davinci_i2c_ids
[] = {
496 { .compatible
= "ti,davinci-i2c"},
497 { .compatible
= "ti,keystone-i2c"},
501 U_BOOT_DRIVER(i2c_davinci
) = {
502 .name
= "i2c_davinci",
504 .of_match
= davinci_i2c_ids
,
505 .probe
= davinci_i2c_probe
,
506 .priv_auto_alloc_size
= sizeof(struct i2c_bus
),
507 .ops
= &davinci_i2c_ops
,
510 #endif /* CONFIG_DM_I2C */