drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <pci.h>
  13 #include <reset.h>
  14 #include <asm/io.h>
  15 #include "designware_i2c.h"
  16 #include <dm/device_compat.h>
  17 #include <linux/err.h>
  18
  19 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  20 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  21 {
  22         u32 ena = enable ? IC_ENABLE_0B : 0;
  23
  24         writel(ena, &i2c_base->ic_enable);
  25
  26         return 0;
  27 }
  28 #else
  29 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  30 {
  31         u32 ena = enable ? IC_ENABLE_0B : 0;
  32         int timeout = 100;
  33
  34         do {
  35                 writel(ena, &i2c_base->ic_enable);
  36                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  37                         return 0;
  38
  39                 /*
  40                  * Wait 10 times the signaling period of the highest I2C
  41                  * transfer supported by the driver (for 400KHz this is
  42                  * 25us) as described in the DesignWare I2C databook.
  43                  */
  44                 udelay(25);
  45         } while (timeout--);
  46         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  47
  48         return -ETIMEDOUT;
  49 }
  50 #endif
  51
  52 /* High and low times in different speed modes (in ns) */
  53 enum {
  54         /* SDA Hold Time */
  55         DEFAULT_SDA_HOLD_TIME           = 300,
  56 };
  57
  58 /**
  59  * calc_counts() - Convert a period to a number of IC clk cycles
  60  *
  61  * @ic_clk: Input clock in Hz
  62  * @period_ns: Period to represent, in ns
  63  * @return calculated count
  64  */
  65 static uint calc_counts(uint ic_clk, uint period_ns)
  66 {
  67         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  68 }
  69
  70 /**
  71  * struct i2c_mode_info - Information about an I2C speed mode
  72  *
  73  * Each speed mode has its own characteristics. This struct holds these to aid
  74  * calculations in dw_i2c_calc_timing().
  75  *
  76  * @speed: Speed in Hz
  77  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  78  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  79  * @def_rise_time_ns: Default rise time in ns
  80  * @def_fall_time_ns: Default fall time in ns
  81  */
  82 struct i2c_mode_info {
  83         int speed;
  84         int min_scl_hightime_ns;
  85         int min_scl_lowtime_ns;
  86         int def_rise_time_ns;
  87         int def_fall_time_ns;
  88 };
  89
  90 static const struct i2c_mode_info info_for_mode[] = {
  91         [IC_SPEED_MODE_STANDARD] = {
  92                 I2C_SPEED_STANDARD_RATE,
  93                 MIN_SS_SCL_HIGHTIME,
  94                 MIN_SS_SCL_LOWTIME,
  95                 1000,
  96                 300,
  97         },
  98         [IC_SPEED_MODE_FAST] = {
  99                 I2C_SPEED_FAST_RATE,
 100                 MIN_FS_SCL_HIGHTIME,
 101                 MIN_FS_SCL_LOWTIME,
 102                 300,
 103                 300,
 104         },
 105         [IC_SPEED_MODE_FAST_PLUS] = {
 106                 I2C_SPEED_FAST_PLUS_RATE,
 107                 MIN_FP_SCL_HIGHTIME,
 108                 MIN_FP_SCL_LOWTIME,
 109                 260,
 110                 500,
 111         },
 112         [IC_SPEED_MODE_HIGH] = {
 113                 I2C_SPEED_HIGH_RATE,
 114                 MIN_HS_SCL_HIGHTIME,
 115                 MIN_HS_SCL_LOWTIME,
 116                 120,
 117                 120,
 118         },
 119 };
 120
 121 /**
 122  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 123  *
 124  * @priv: Bus private information (NULL if not using driver model)
 125  * @mode: Speed mode to use
 126  * @ic_clk: IC clock speed in Hz
 127  * @spk_cnt: Spike-suppression count
 128  * @config: Returns value to use
 129  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 130  */
 131 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 132                               int ic_clk, int spk_cnt,
 133                               struct dw_i2c_speed_config *config)
 134 {
 135         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 136         int hcnt, lcnt, period_cnt, diff, tot;
 137         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 138         const struct i2c_mode_info *info;
 139
 140         /*
 141          * Find the period, rise, fall, min tlow, and min thigh in terms of
 142          * counts of the IC clock
 143          */
 144         info = &info_for_mode[mode];
 145         period_cnt = ic_clk / info->speed;
 146         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 147                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 148         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 149                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 150         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 151         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 152         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 153         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 154
 155         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 156               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 157               spk_cnt);
 158
 159         /*
 160          * Back-solve for hcnt and lcnt according to the following equations:
 161          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 162          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 163          */
 164         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 165         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 166
 167         if (hcnt < 0 || lcnt < 0) {
 168                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 169                 return -EINVAL;
 170         }
 171
 172         /*
 173          * Now add things back up to ensure the period is hit. If it is off,
 174          * split the difference and bias to lcnt for remainder
 175          */
 176         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 177
 178         if (tot < period_cnt) {
 179                 diff = (period_cnt - tot) / 2;
 180                 hcnt += diff;
 181                 lcnt += diff;
 182                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 183                 lcnt += period_cnt - tot;
 184         }
 185
 186         config->scl_lcnt = lcnt;
 187         config->scl_hcnt = hcnt;
 188
 189         /* Use internal default unless other value is specified */
 190         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 191                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 192         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 193
 194         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 195               config->sda_hold);
 196
 197         return 0;
 198 }
 199
 200 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
 201                           struct dw_i2c_speed_config *config)
 202 {
 203         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 204         struct i2c_regs *regs = priv->regs;
 205         enum i2c_speed_mode i2c_spd;
 206         u32 comp_param1;
 207         int spk_cnt;
 208         int ret;
 209
 210         comp_param1 = readl(&regs->comp_param1);
 211
 212         if (priv)
 213                 scl_sda_cfg = priv->scl_sda_cfg;
 214         /* Allow high speed if there is no config, or the config allows it */
 215         if (speed >= I2C_SPEED_HIGH_RATE)
 216                 i2c_spd = IC_SPEED_MODE_HIGH;
 217         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 218                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 219         else if (speed >= I2C_SPEED_FAST_RATE)
 220                 i2c_spd = IC_SPEED_MODE_FAST;
 221         else
 222                 i2c_spd = IC_SPEED_MODE_STANDARD;
 223
 224         /* Check is high speed possible and fall back to fast mode if not */
 225         if (i2c_spd == IC_SPEED_MODE_HIGH) {
 226                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 227                                 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
 228                         i2c_spd = IC_SPEED_MODE_FAST;
 229         }
 230
 231         /* Get the proper spike-suppression count based on target speed */
 232         if (!priv || !priv->has_spk_cnt)
 233                 spk_cnt = 0;
 234         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 235                 spk_cnt = readl(&regs->hs_spklen);
 236         else
 237                 spk_cnt = readl(&regs->fs_spklen);
 238         if (scl_sda_cfg) {
 239                 config->sda_hold = scl_sda_cfg->sda_hold;
 240                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 241                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 242                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 243                 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
 244                         config->scl_hcnt = scl_sda_cfg->hs_hcnt;
 245                         config->scl_lcnt = scl_sda_cfg->hs_lcnt;
 246                 } else {
 247                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 248                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 249                 }
 250         } else {
 251                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 252                                          config);
 253                 if (ret)
 254                         return log_msg_ret("gen_confg", ret);
 255         }
 256         config->speed_mode = i2c_spd;
 257
 258         return 0;
 259 }
 260
 261 /*
 262  * _dw_i2c_set_bus_speed - Set the i2c speed
 263  * @speed:      required i2c speed
 264  *
 265  * Set the i2c speed.
 266  */
 267 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 268                                  unsigned int speed, unsigned int bus_clk)
 269 {
 270         struct dw_i2c_speed_config config;
 271         unsigned int cntl;
 272         unsigned int ena;
 273         int ret;
 274
 275         ret = calc_bus_speed(priv, speed, bus_clk, &config);
 276         if (ret)
 277                 return ret;
 278
 279         /* Get enable setting for restore later */
 280         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 281
 282         /* to set speed cltr must be disabled */
 283         dw_i2c_enable(i2c_base, false);
 284
 285         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 286
 287         switch (config.speed_mode) {
 288         case IC_SPEED_MODE_HIGH:
 289                 cntl |= IC_CON_SPD_HS;
 290                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 291                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 292                 break;
 293         case IC_SPEED_MODE_STANDARD:
 294                 cntl |= IC_CON_SPD_SS;
 295                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 296                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 297                 break;
 298         case IC_SPEED_MODE_FAST_PLUS:
 299         case IC_SPEED_MODE_FAST:
 300         default:
 301                 cntl |= IC_CON_SPD_FS;
 302                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 303                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 304                 break;
 305         }
 306
 307         writel(cntl, &i2c_base->ic_con);
 308
 309         /* Configure SDA Hold Time if required */
 310         if (config.sda_hold)
 311                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 312
 313         /* Restore back i2c now speed set */
 314         if (ena == IC_ENABLE_0B)
 315                 dw_i2c_enable(i2c_base, true);
 316
 317         return 0;
 318 }
 319
 320 /*
 321  * i2c_setaddress - Sets the target slave address
 322  * @i2c_addr:   target i2c address
 323  *
 324  * Sets the target slave address.
 325  */
 326 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 327 {
 328         /* Disable i2c */
 329         dw_i2c_enable(i2c_base, false);
 330
 331         writel(i2c_addr, &i2c_base->ic_tar);
 332
 333         /* Enable i2c */
 334         dw_i2c_enable(i2c_base, true);
 335 }
 336
 337 /*
 338  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 339  *
 340  * Flushes the i2c RX FIFO
 341  */
 342 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 343 {
 344         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 345                 readl(&i2c_base->ic_cmd_data);
 346 }
 347
 348 /*
 349  * i2c_wait_for_bb - Waits for bus busy
 350  *
 351  * Waits for bus busy
 352  */
 353 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 354 {
 355         unsigned long start_time_bb = get_timer(0);
 356
 357         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 358                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 359
 360                 /* Evaluate timeout */
 361                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 362                         return 1;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 369                          int alen)
 370 {
 371         if (i2c_wait_for_bb(i2c_base))
 372                 return 1;
 373
 374         i2c_setaddress(i2c_base, chip);
 375         while (alen) {
 376                 alen--;
 377                 /* high byte address going out first */
 378                 writel((addr >> (alen * 8)) & 0xff,
 379                        &i2c_base->ic_cmd_data);
 380         }
 381         return 0;
 382 }
 383
 384 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 385 {
 386         ulong start_stop_det = get_timer(0);
 387
 388         while (1) {
 389                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 390                         readl(&i2c_base->ic_clr_stop_det);
 391                         break;
 392                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 393                         break;
 394                 }
 395         }
 396
 397         if (i2c_wait_for_bb(i2c_base)) {
 398                 printf("Timed out waiting for bus\n");
 399                 return 1;
 400         }
 401
 402         i2c_flush_rxfifo(i2c_base);
 403
 404         return 0;
 405 }
 406
 407 /*
 408  * i2c_read - Read from i2c memory
 409  * @chip:       target i2c address
 410  * @addr:       address to read from
 411  * @alen:
 412  * @buffer:     buffer for read data
 413  * @len:        no of bytes to be read
 414  *
 415  * Read from i2c memory.
 416  */
 417 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 418                          int alen, u8 *buffer, int len)
 419 {
 420         unsigned long start_time_rx;
 421         unsigned int active = 0;
 422
 423 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 424         /*
 425          * EEPROM chips that implement "address overflow" are ones
 426          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 427          * address and the extra bits end up in the "chip address"
 428          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 429          * four 256 byte chips.
 430          *
 431          * Note that we consider the length of the address field to
 432          * still be one byte because the extra address bits are
 433          * hidden in the chip address.
 434          */
 435         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 436         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 437
 438         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 439               addr);
 440 #endif
 441
 442         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 443                 return 1;
 444
 445         start_time_rx = get_timer(0);
 446         while (len) {
 447                 if (!active) {
 448                         /*
 449                          * Avoid writing to ic_cmd_data multiple times
 450                          * in case this loop spins too quickly and the
 451                          * ic_status RFNE bit isn't set after the first
 452                          * write. Subsequent writes to ic_cmd_data can
 453                          * trigger spurious i2c transfer.
 454                          */
 455                         if (len == 1)
 456                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 457                         else
 458                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 459                         active = 1;
 460                 }
 461
 462                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 463                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 464                         len--;
 465                         start_time_rx = get_timer(0);
 466                         active = 0;
 467                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 468                         return 1;
 469                 }
 470         }
 471
 472         return i2c_xfer_finish(i2c_base);
 473 }
 474
 475 /*
 476  * i2c_write - Write to i2c memory
 477  * @chip:       target i2c address
 478  * @addr:       address to read from
 479  * @alen:
 480  * @buffer:     buffer for read data
 481  * @len:        no of bytes to be read
 482  *
 483  * Write to i2c memory.
 484  */
 485 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 486                           int alen, u8 *buffer, int len)
 487 {
 488         int nb = len;
 489         unsigned long start_time_tx;
 490
 491 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 492         /*
 493          * EEPROM chips that implement "address overflow" are ones
 494          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 495          * address and the extra bits end up in the "chip address"
 496          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 497          * four 256 byte chips.
 498          *
 499          * Note that we consider the length of the address field to
 500          * still be one byte because the extra address bits are
 501          * hidden in the chip address.
 502          */
 503         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 504         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 505
 506         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 507               addr);
 508 #endif
 509
 510         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 511                 return 1;
 512
 513         start_time_tx = get_timer(0);
 514         while (len) {
 515                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 516                         if (--len == 0) {
 517                                 writel(*buffer | IC_STOP,
 518                                        &i2c_base->ic_cmd_data);
 519                         } else {
 520                                 writel(*buffer, &i2c_base->ic_cmd_data);
 521                         }
 522                         buffer++;
 523                         start_time_tx = get_timer(0);
 524
 525                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 526                                 printf("Timed out. i2c write Failed\n");
 527                                 return 1;
 528                 }
 529         }
 530
 531         return i2c_xfer_finish(i2c_base);
 532 }
 533
 534 /*
 535  * __dw_i2c_init - Init function
 536  * @speed:      required i2c speed
 537  * @slaveaddr:  slave address for the device
 538  *
 539  * Initialization function.
 540  */
 541 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 542 {
 543         int ret;
 544
 545         /* Disable i2c */
 546         ret = dw_i2c_enable(i2c_base, false);
 547         if (ret)
 548                 return ret;
 549
 550         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 551                &i2c_base->ic_con);
 552         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 553         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 554         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 555 #ifndef CONFIG_DM_I2C
 556         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 557         writel(slaveaddr, &i2c_base->ic_sar);
 558 #endif
 559
 560         /* Enable i2c */
 561         ret = dw_i2c_enable(i2c_base, true);
 562         if (ret)
 563                 return ret;
 564
 565         return 0;
 566 }
 567
 568 #ifndef CONFIG_DM_I2C
 569 /*
 570  * The legacy I2C functions. These need to get removed once
 571  * all users of this driver are converted to DM.
 572  */
 573 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 574 {
 575         switch (adap->hwadapnr) {
 576 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 577         case 3:
 578                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 579 #endif
 580 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 581         case 2:
 582                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 583 #endif
 584 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 585         case 1:
 586                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 587 #endif
 588         case 0:
 589                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 590         default:
 591                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 592         }
 593
 594         return NULL;
 595 }
 596
 597 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 598                                          unsigned int speed)
 599 {
 600         adap->speed = speed;
 601         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 602 }
 603
 604 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 605 {
 606         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 607 }
 608
 609 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 610                        int alen, u8 *buffer, int len)
 611 {
 612         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 613 }
 614
 615 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 616                         int alen, u8 *buffer, int len)
 617 {
 618         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 619 }
 620
 621 /* dw_i2c_probe - Probe the i2c chip */
 622 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 623 {
 624         struct i2c_regs *i2c_base = i2c_get_base(adap);
 625         u32 tmp;
 626         int ret;
 627
 628         /*
 629          * Try to read the first location of the chip.
 630          */
 631         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 632         if (ret)
 633                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 634
 635         return ret;
 636 }
 637
 638 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 639                          dw_i2c_write, dw_i2c_set_bus_speed,
 640                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 641
 642 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 643 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 644                          dw_i2c_write, dw_i2c_set_bus_speed,
 645                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 646 #endif
 647
 648 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 649 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 650                          dw_i2c_write, dw_i2c_set_bus_speed,
 651                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 652 #endif
 653
 654 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 655 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 656                          dw_i2c_write, dw_i2c_set_bus_speed,
 657                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 658 #endif
 659
 660 #else /* CONFIG_DM_I2C */
 661 /* The DM I2C functions */
 662
 663 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 664                                int nmsgs)
 665 {
 666         struct dw_i2c *i2c = dev_get_priv(bus);
 667         int ret;
 668
 669         debug("i2c_xfer: %d messages\n", nmsgs);
 670         for (; nmsgs > 0; nmsgs--, msg++) {
 671                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 672                 if (msg->flags & I2C_M_RD) {
 673                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 674                                             msg->buf, msg->len);
 675                 } else {
 676                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 677                                              msg->buf, msg->len);
 678                 }
 679                 if (ret) {
 680                         debug("i2c_write: error sending\n");
 681                         return -EREMOTEIO;
 682                 }
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 689 {
 690         struct dw_i2c *i2c = dev_get_priv(bus);
 691         ulong rate;
 692
 693 #if CONFIG_IS_ENABLED(CLK)
 694         rate = clk_get_rate(&i2c->clk);
 695         if (IS_ERR_VALUE(rate))
 696                 return -EINVAL;
 697 #else
 698         rate = IC_CLK;
 699 #endif
 700         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 701 }
 702
 703 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 704                                      uint chip_flags)
 705 {
 706         struct dw_i2c *i2c = dev_get_priv(bus);
 707         struct i2c_regs *i2c_base = i2c->regs;
 708         u32 tmp;
 709         int ret;
 710
 711         /* Try to read the first location of the chip */
 712         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 713         if (ret)
 714                 __dw_i2c_init(i2c_base, 0, 0);
 715
 716         return ret;
 717 }
 718
 719 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 720 {
 721         struct dw_i2c *priv = dev_get_priv(bus);
 722         int ret;
 723
 724         if (!priv->regs)
 725                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 726         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 727         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 728         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 729
 730         ret = reset_get_bulk(bus, &priv->resets);
 731         if (ret)
 732                 dev_warn(bus, "Can't get reset: %d\n", ret);
 733         else
 734                 reset_deassert_bulk(&priv->resets);
 735
 736 #if CONFIG_IS_ENABLED(CLK)
 737         ret = clk_get_by_index(bus, 0, &priv->clk);
 738         if (ret)
 739                 return ret;
 740
 741         ret = clk_enable(&priv->clk);
 742         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 743                 clk_free(&priv->clk);
 744                 dev_err(bus, "failed to enable clock\n");
 745                 return ret;
 746         }
 747 #endif
 748
 749         return 0;
 750 }
 751
 752 int designware_i2c_probe(struct udevice *bus)
 753 {
 754         struct dw_i2c *priv = dev_get_priv(bus);
 755
 756         return __dw_i2c_init(priv->regs, 0, 0);
 757 }
 758
 759 int designware_i2c_remove(struct udevice *dev)
 760 {
 761         struct dw_i2c *priv = dev_get_priv(dev);
 762
 763 #if CONFIG_IS_ENABLED(CLK)
 764         clk_disable(&priv->clk);
 765         clk_free(&priv->clk);
 766 #endif
 767
 768         return reset_release_bulk(&priv->resets);
 769 }
 770
 771 const struct dm_i2c_ops designware_i2c_ops = {
 772         .xfer           = designware_i2c_xfer,
 773         .probe_chip     = designware_i2c_probe_chip,
 774         .set_bus_speed  = designware_i2c_set_bus_speed,
 775 };
 776
 777 static const struct udevice_id designware_i2c_ids[] = {
 778         { .compatible = "snps,designware-i2c" },
 779         { }
 780 };
 781
 782 U_BOOT_DRIVER(i2c_designware) = {
 783         .name   = "i2c_designware",
 784         .id     = UCLASS_I2C,
 785         .of_match = designware_i2c_ids,
 786         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 787         .probe  = designware_i2c_probe,
 788         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 789         .remove = designware_i2c_remove,
 790         .flags  = DM_FLAG_OS_PREPARE,
 791         .ops    = &designware_i2c_ops,
 792 };
 793
 794 #endif /* CONFIG_DM_I2C */