1 // SPDX-License-Identifier: GPL-2.0+
4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com.
16 #include <linux/delay.h>
17 #include "designware_i2c.h"
18 #include <dm/device_compat.h>
19 #include <linux/err.h>
22 * This assigned unique hex value is constant and is derived from the two ASCII
23 * letters 'DW' followed by a 16-bit unsigned number
25 #define DW_I2C_COMP_TYPE 0x44570140
27 static int dw_i2c_enable(struct i2c_regs
*i2c_base
, bool enable
)
29 u32 ena
= enable
? IC_ENABLE_0B
: 0;
33 writel(ena
, &i2c_base
->ic_enable
);
34 if ((readl(&i2c_base
->ic_enable_status
) & IC_ENABLE_0B
) == ena
)
38 * Wait 10 times the signaling period of the highest I2C
39 * transfer supported by the driver (for 400KHz this is
40 * 25us) as described in the DesignWare I2C databook.
44 printf("timeout in %sabling I2C adapter\n", enable
? "en" : "dis");
49 /* High and low times in different speed modes (in ns) */
52 DEFAULT_SDA_HOLD_TIME
= 300,
56 * calc_counts() - Convert a period to a number of IC clk cycles
58 * @ic_clk: Input clock in Hz
59 * @period_ns: Period to represent, in ns
60 * Return: calculated count
62 static uint
calc_counts(uint ic_clk
, uint period_ns
)
64 return DIV_ROUND_UP(ic_clk
/ 1000 * period_ns
, NANO_TO_KILO
);
68 * struct i2c_mode_info - Information about an I2C speed mode
70 * Each speed mode has its own characteristics. This struct holds these to aid
71 * calculations in dw_i2c_calc_timing().
74 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
75 * @min_scl_hightime_ns: Minimum value for SCL high period in ns
76 * @def_rise_time_ns: Default rise time in ns
77 * @def_fall_time_ns: Default fall time in ns
79 struct i2c_mode_info
{
81 int min_scl_hightime_ns
;
82 int min_scl_lowtime_ns
;
87 static const struct i2c_mode_info info_for_mode
[] = {
88 [IC_SPEED_MODE_STANDARD
] = {
89 I2C_SPEED_STANDARD_RATE
,
95 [IC_SPEED_MODE_FAST
] = {
102 [IC_SPEED_MODE_FAST_PLUS
] = {
103 I2C_SPEED_FAST_PLUS_RATE
,
109 [IC_SPEED_MODE_HIGH
] = {
119 * dw_i2c_calc_timing() - Calculate the timings to use for a bus
121 * @priv: Bus private information (NULL if not using driver model)
122 * @mode: Speed mode to use
123 * @ic_clk: IC clock speed in Hz
124 * @spk_cnt: Spike-suppression count
125 * @config: Returns value to use
126 * Return: 0 if OK, -EINVAL if the calculation failed due to invalid data
128 static int dw_i2c_calc_timing(struct dw_i2c
*priv
, enum i2c_speed_mode mode
,
129 int ic_clk
, int spk_cnt
,
130 struct dw_i2c_speed_config
*config
)
132 int fall_cnt
, rise_cnt
, min_tlow_cnt
, min_thigh_cnt
;
133 int hcnt
, lcnt
, period_cnt
, diff
, tot
;
134 int sda_hold_time_ns
, scl_rise_time_ns
, scl_fall_time_ns
;
135 const struct i2c_mode_info
*info
;
138 * Find the period, rise, fall, min tlow, and min thigh in terms of
139 * counts of the IC clock
141 info
= &info_for_mode
[mode
];
142 period_cnt
= ic_clk
/ info
->speed
;
143 scl_rise_time_ns
= priv
&& priv
->scl_rise_time_ns
?
144 priv
->scl_rise_time_ns
: info
->def_rise_time_ns
;
145 scl_fall_time_ns
= priv
&& priv
->scl_fall_time_ns
?
146 priv
->scl_fall_time_ns
: info
->def_fall_time_ns
;
147 rise_cnt
= calc_counts(ic_clk
, scl_rise_time_ns
);
148 fall_cnt
= calc_counts(ic_clk
, scl_fall_time_ns
);
149 min_tlow_cnt
= calc_counts(ic_clk
, info
->min_scl_lowtime_ns
);
150 min_thigh_cnt
= calc_counts(ic_clk
, info
->min_scl_hightime_ns
);
152 debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n",
153 mode
, ic_clk
, info
->speed
, period_cnt
, rise_cnt
, fall_cnt
,
154 min_tlow_cnt
, min_thigh_cnt
, spk_cnt
);
157 * Back-solve for hcnt and lcnt according to the following equations:
158 * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
159 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
161 hcnt
= min_thigh_cnt
- fall_cnt
- 7 - spk_cnt
;
162 lcnt
= min_tlow_cnt
- rise_cnt
+ fall_cnt
- 1;
164 if (hcnt
< 0 || lcnt
< 0) {
165 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt
, lcnt
);
166 return log_msg_ret("counts", -EINVAL
);
170 * Now add things back up to ensure the period is hit. If it is off,
171 * split the difference and bias to lcnt for remainder
173 tot
= hcnt
+ lcnt
+ 7 + spk_cnt
+ rise_cnt
+ 1;
175 if (tot
< period_cnt
) {
176 diff
= (period_cnt
- tot
) / 2;
179 tot
= hcnt
+ lcnt
+ 7 + spk_cnt
+ rise_cnt
+ 1;
180 lcnt
+= period_cnt
- tot
;
183 config
->scl_lcnt
= lcnt
;
184 config
->scl_hcnt
= hcnt
;
186 /* Use internal default unless other value is specified */
187 sda_hold_time_ns
= priv
&& priv
->sda_hold_time_ns
?
188 priv
->sda_hold_time_ns
: DEFAULT_SDA_HOLD_TIME
;
189 config
->sda_hold
= calc_counts(ic_clk
, sda_hold_time_ns
);
191 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt
, lcnt
,
198 * calc_bus_speed() - Calculate the config to use for a particular i2c speed
200 * @priv: Private information for the driver (NULL if not using driver model)
201 * @i2c_base: Registers for the I2C controller
202 * @speed: Required i2c speed in Hz
203 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
204 * @config: Returns the config to use for this speed
205 * Return: 0 if OK, -ve on error
207 static int calc_bus_speed(struct dw_i2c
*priv
, struct i2c_regs
*regs
, int speed
,
208 ulong bus_clk
, struct dw_i2c_speed_config
*config
)
210 const struct dw_scl_sda_cfg
*scl_sda_cfg
= NULL
;
211 enum i2c_speed_mode i2c_spd
;
216 scl_sda_cfg
= priv
->scl_sda_cfg
;
217 /* Allow high speed if there is no config, or the config allows it */
218 if (speed
>= I2C_SPEED_HIGH_RATE
)
219 i2c_spd
= IC_SPEED_MODE_HIGH
;
220 else if (speed
>= I2C_SPEED_FAST_PLUS_RATE
)
221 i2c_spd
= IC_SPEED_MODE_FAST_PLUS
;
222 else if (speed
>= I2C_SPEED_FAST_RATE
)
223 i2c_spd
= IC_SPEED_MODE_FAST
;
225 i2c_spd
= IC_SPEED_MODE_STANDARD
;
227 /* Check is high speed possible and fall back to fast mode if not */
228 if (i2c_spd
== IC_SPEED_MODE_HIGH
) {
231 comp_param1
= readl(®s
->comp_param1
);
232 if ((comp_param1
& DW_IC_COMP_PARAM_1_SPEED_MODE_MASK
)
233 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH
)
234 i2c_spd
= IC_SPEED_MODE_FAST
;
237 /* Get the proper spike-suppression count based on target speed */
238 if (!priv
|| !priv
->has_spk_cnt
)
240 else if (i2c_spd
>= IC_SPEED_MODE_HIGH
)
241 spk_cnt
= readl(®s
->hs_spklen
);
243 spk_cnt
= readl(®s
->fs_spklen
);
245 config
->sda_hold
= scl_sda_cfg
->sda_hold
;
246 if (i2c_spd
== IC_SPEED_MODE_STANDARD
) {
247 config
->scl_hcnt
= scl_sda_cfg
->ss_hcnt
;
248 config
->scl_lcnt
= scl_sda_cfg
->ss_lcnt
;
249 } else if (i2c_spd
== IC_SPEED_MODE_HIGH
) {
250 config
->scl_hcnt
= scl_sda_cfg
->hs_hcnt
;
251 config
->scl_lcnt
= scl_sda_cfg
->hs_lcnt
;
253 config
->scl_hcnt
= scl_sda_cfg
->fs_hcnt
;
254 config
->scl_lcnt
= scl_sda_cfg
->fs_lcnt
;
257 ret
= dw_i2c_calc_timing(priv
, i2c_spd
, bus_clk
, spk_cnt
,
260 return log_msg_ret("gen_confg", ret
);
262 config
->speed_mode
= i2c_spd
;
268 * _dw_i2c_set_bus_speed() - Set the i2c speed
270 * @priv: Private information for the driver (NULL if not using driver model)
271 * @i2c_base: Registers for the I2C controller
272 * @speed: Required i2c speed in Hz
273 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK)
274 * Return: 0 if OK, -ve on error
276 static int _dw_i2c_set_bus_speed(struct dw_i2c
*priv
, struct i2c_regs
*i2c_base
,
277 unsigned int speed
, unsigned int bus_clk
)
279 struct dw_i2c_speed_config config
;
284 ret
= calc_bus_speed(priv
, i2c_base
, speed
, bus_clk
, &config
);
288 /* Get enable setting for restore later */
289 ena
= readl(&i2c_base
->ic_enable
) & IC_ENABLE_0B
;
291 /* to set speed cltr must be disabled */
292 dw_i2c_enable(i2c_base
, false);
294 cntl
= (readl(&i2c_base
->ic_con
) & (~IC_CON_SPD_MSK
));
296 switch (config
.speed_mode
) {
297 case IC_SPEED_MODE_HIGH
:
298 cntl
|= IC_CON_SPD_HS
;
299 writel(config
.scl_hcnt
, &i2c_base
->ic_hs_scl_hcnt
);
300 writel(config
.scl_lcnt
, &i2c_base
->ic_hs_scl_lcnt
);
302 case IC_SPEED_MODE_STANDARD
:
303 cntl
|= IC_CON_SPD_SS
;
304 writel(config
.scl_hcnt
, &i2c_base
->ic_ss_scl_hcnt
);
305 writel(config
.scl_lcnt
, &i2c_base
->ic_ss_scl_lcnt
);
307 case IC_SPEED_MODE_FAST_PLUS
:
308 case IC_SPEED_MODE_FAST
:
310 cntl
|= IC_CON_SPD_FS
;
311 writel(config
.scl_hcnt
, &i2c_base
->ic_fs_scl_hcnt
);
312 writel(config
.scl_lcnt
, &i2c_base
->ic_fs_scl_lcnt
);
316 writel(cntl
, &i2c_base
->ic_con
);
318 /* Configure SDA Hold Time if required */
320 writel(config
.sda_hold
, &i2c_base
->ic_sda_hold
);
322 /* Restore back i2c now speed set */
323 if (ena
== IC_ENABLE_0B
)
324 dw_i2c_enable(i2c_base
, true);
326 priv
->config
= config
;
331 int dw_i2c_gen_speed_config(const struct udevice
*dev
, int speed_hz
,
332 struct dw_i2c_speed_config
*config
)
334 struct dw_i2c
*priv
= dev_get_priv(dev
);
338 #if CONFIG_IS_ENABLED(CLK)
339 rate
= clk_get_rate(&priv
->clk
);
340 if (IS_ERR_VALUE(rate
))
341 return log_msg_ret("clk", -EINVAL
);
346 ret
= calc_bus_speed(priv
, priv
->regs
, speed_hz
, rate
, config
);
348 printf("%s: ret=%d\n", __func__
, ret
);
350 return log_msg_ret("calc_bus_speed", ret
);
356 * i2c_setaddress - Sets the target slave address
357 * @i2c_addr: target i2c address
359 * Sets the target slave address.
361 static void i2c_setaddress(struct i2c_regs
*i2c_base
, unsigned int i2c_addr
)
364 dw_i2c_enable(i2c_base
, false);
366 writel(i2c_addr
, &i2c_base
->ic_tar
);
369 dw_i2c_enable(i2c_base
, true);
373 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
375 * Flushes the i2c RX FIFO
377 static void i2c_flush_rxfifo(struct i2c_regs
*i2c_base
)
379 while (readl(&i2c_base
->ic_status
) & IC_STATUS_RFNE
)
380 readl(&i2c_base
->ic_cmd_data
);
384 * i2c_wait_for_bb - Waits for bus busy
388 static int i2c_wait_for_bb(struct i2c_regs
*i2c_base
)
390 unsigned long start_time_bb
= get_timer(0);
392 while ((readl(&i2c_base
->ic_status
) & IC_STATUS_MA
) ||
393 !(readl(&i2c_base
->ic_status
) & IC_STATUS_TFE
)) {
395 /* Evaluate timeout */
396 if (get_timer(start_time_bb
) > (unsigned long)(I2C_BYTE_TO_BB
))
403 static int i2c_xfer_init(struct i2c_regs
*i2c_base
, uchar chip
, uint addr
,
406 if (i2c_wait_for_bb(i2c_base
))
409 i2c_setaddress(i2c_base
, chip
);
412 /* high byte address going out first */
413 writel((addr
>> (alen
* 8)) & 0xff,
414 &i2c_base
->ic_cmd_data
);
419 static int i2c_xfer_finish(struct i2c_regs
*i2c_base
)
421 ulong start_stop_det
= get_timer(0);
424 if ((readl(&i2c_base
->ic_raw_intr_stat
) & IC_STOP_DET
)) {
425 readl(&i2c_base
->ic_clr_stop_det
);
427 } else if (get_timer(start_stop_det
) > I2C_STOPDET_TO
) {
432 if (i2c_wait_for_bb(i2c_base
)) {
433 printf("Timed out waiting for bus\n");
437 i2c_flush_rxfifo(i2c_base
);
443 * i2c_read - Read from i2c memory
444 * @chip: target i2c address
445 * @addr: address to read from
447 * @buffer: buffer for read data
448 * @len: no of bytes to be read
450 * Read from i2c memory.
452 static int __dw_i2c_read(struct i2c_regs
*i2c_base
, u8 dev
, uint addr
,
453 int alen
, u8
*buffer
, int len
)
455 unsigned long start_time_rx
;
456 unsigned int active
= 0;
458 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
460 * EEPROM chips that implement "address overflow" are ones
461 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
462 * address and the extra bits end up in the "chip address"
463 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
464 * four 256 byte chips.
466 * Note that we consider the length of the address field to
467 * still be one byte because the extra address bits are
468 * hidden in the chip address.
470 dev
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
471 addr
&= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
<< (alen
* 8));
473 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__
, dev
,
477 if (i2c_xfer_init(i2c_base
, dev
, addr
, alen
))
480 start_time_rx
= get_timer(0);
484 * Avoid writing to ic_cmd_data multiple times
485 * in case this loop spins too quickly and the
486 * ic_status RFNE bit isn't set after the first
487 * write. Subsequent writes to ic_cmd_data can
488 * trigger spurious i2c transfer.
491 writel(IC_CMD
| IC_STOP
, &i2c_base
->ic_cmd_data
);
493 writel(IC_CMD
, &i2c_base
->ic_cmd_data
);
497 if (readl(&i2c_base
->ic_status
) & IC_STATUS_RFNE
) {
498 *buffer
++ = (uchar
)readl(&i2c_base
->ic_cmd_data
);
500 start_time_rx
= get_timer(0);
502 } else if (get_timer(start_time_rx
) > I2C_BYTE_TO
) {
507 return i2c_xfer_finish(i2c_base
);
511 * i2c_write - Write to i2c memory
512 * @chip: target i2c address
513 * @addr: address to read from
515 * @buffer: buffer for read data
516 * @len: no of bytes to be read
518 * Write to i2c memory.
520 static int __dw_i2c_write(struct i2c_regs
*i2c_base
, u8 dev
, uint addr
,
521 int alen
, u8
*buffer
, int len
)
524 unsigned long start_time_tx
;
526 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
528 * EEPROM chips that implement "address overflow" are ones
529 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
530 * address and the extra bits end up in the "chip address"
531 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
532 * four 256 byte chips.
534 * Note that we consider the length of the address field to
535 * still be one byte because the extra address bits are
536 * hidden in the chip address.
538 dev
|= ((addr
>> (alen
* 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
539 addr
&= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
<< (alen
* 8));
541 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__
, dev
,
545 if (i2c_xfer_init(i2c_base
, dev
, addr
, alen
))
548 start_time_tx
= get_timer(0);
550 if (readl(&i2c_base
->ic_status
) & IC_STATUS_TFNF
) {
552 writel(*buffer
| IC_STOP
,
553 &i2c_base
->ic_cmd_data
);
555 writel(*buffer
, &i2c_base
->ic_cmd_data
);
558 start_time_tx
= get_timer(0);
560 } else if (get_timer(start_time_tx
) > (nb
* I2C_BYTE_TO
)) {
561 printf("Timed out. i2c write Failed\n");
566 return i2c_xfer_finish(i2c_base
);
570 * __dw_i2c_init - Init function
571 * @speed: required i2c speed
572 * @slaveaddr: slave address for the device
574 * Initialization function.
576 static int __dw_i2c_init(struct i2c_regs
*i2c_base
, int speed
, int slaveaddr
)
581 ret
= dw_i2c_enable(i2c_base
, false);
585 writel(IC_CON_SD
| IC_CON_RE
| IC_CON_SPD_FS
| IC_CON_MM
,
587 writel(IC_RX_TL
, &i2c_base
->ic_rx_tl
);
588 writel(IC_TX_TL
, &i2c_base
->ic_tx_tl
);
589 writel(IC_STOP_DET
, &i2c_base
->ic_intr_mask
);
590 #if !CONFIG_IS_ENABLED(DM_I2C)
591 _dw_i2c_set_bus_speed(NULL
, i2c_base
, speed
, IC_CLK
);
592 writel(slaveaddr
, &i2c_base
->ic_sar
);
596 ret
= dw_i2c_enable(i2c_base
, true);
603 #if !CONFIG_IS_ENABLED(DM_I2C)
605 * The legacy I2C functions. These need to get removed once
606 * all users of this driver are converted to DM.
608 static struct i2c_regs
*i2c_get_base(struct i2c_adapter
*adap
)
610 switch (adap
->hwadapnr
) {
611 #if CONFIG_SYS_I2C_BUS_MAX >= 4
613 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE3
;
615 #if CONFIG_SYS_I2C_BUS_MAX >= 3
617 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE2
;
619 #if CONFIG_SYS_I2C_BUS_MAX >= 2
621 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE1
;
624 return (struct i2c_regs
*)CONFIG_SYS_I2C_BASE
;
626 printf("Wrong I2C-adapter number %d\n", adap
->hwadapnr
);
632 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter
*adap
,
636 return _dw_i2c_set_bus_speed(NULL
, i2c_get_base(adap
), speed
, IC_CLK
);
639 static void dw_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
641 __dw_i2c_init(i2c_get_base(adap
), speed
, slaveaddr
);
644 static int dw_i2c_read(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
645 int alen
, u8
*buffer
, int len
)
647 return __dw_i2c_read(i2c_get_base(adap
), dev
, addr
, alen
, buffer
, len
);
650 static int dw_i2c_write(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
651 int alen
, u8
*buffer
, int len
)
653 return __dw_i2c_write(i2c_get_base(adap
), dev
, addr
, alen
, buffer
, len
);
656 /* dw_i2c_probe - Probe the i2c chip */
657 static int dw_i2c_probe(struct i2c_adapter
*adap
, u8 dev
)
659 struct i2c_regs
*i2c_base
= i2c_get_base(adap
);
664 * Try to read the first location of the chip.
666 ret
= __dw_i2c_read(i2c_base
, dev
, 0, 1, (uchar
*)&tmp
, 1);
668 dw_i2c_init(adap
, adap
->speed
, adap
->slaveaddr
);
673 U_BOOT_I2C_ADAP_COMPLETE(dw_0
, dw_i2c_init
, dw_i2c_probe
, dw_i2c_read
,
674 dw_i2c_write
, dw_i2c_set_bus_speed
,
675 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
, 0)
677 #else /* CONFIG_DM_I2C */
678 /* The DM I2C functions */
680 static int designware_i2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
,
683 struct dw_i2c
*i2c
= dev_get_priv(bus
);
686 debug("i2c_xfer: %d messages\n", nmsgs
);
687 for (; nmsgs
> 0; nmsgs
--, msg
++) {
688 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
689 if (msg
->flags
& I2C_M_RD
) {
690 ret
= __dw_i2c_read(i2c
->regs
, msg
->addr
, 0, 0,
693 ret
= __dw_i2c_write(i2c
->regs
, msg
->addr
, 0, 0,
697 debug("i2c_write: error sending\n");
705 static int designware_i2c_set_bus_speed(struct udevice
*bus
, unsigned int speed
)
707 struct dw_i2c
*i2c
= dev_get_priv(bus
);
710 #if CONFIG_IS_ENABLED(CLK)
711 rate
= clk_get_rate(&i2c
->clk
);
712 if (IS_ERR_VALUE(rate
))
713 return log_ret(-EINVAL
);
717 return _dw_i2c_set_bus_speed(i2c
, i2c
->regs
, speed
, rate
);
720 static int designware_i2c_probe_chip(struct udevice
*bus
, uint chip_addr
,
723 struct dw_i2c
*i2c
= dev_get_priv(bus
);
724 struct i2c_regs
*i2c_base
= i2c
->regs
;
728 /* Try to read the first location of the chip */
729 ret
= __dw_i2c_read(i2c_base
, chip_addr
, 0, 1, (uchar
*)&tmp
, 1);
731 __dw_i2c_init(i2c_base
, 0, 0);
736 int designware_i2c_of_to_plat(struct udevice
*bus
)
738 struct dw_i2c
*priv
= dev_get_priv(bus
);
742 priv
->regs
= dev_read_addr_ptr(bus
);
743 dev_read_u32(bus
, "i2c-scl-rising-time-ns", &priv
->scl_rise_time_ns
);
744 dev_read_u32(bus
, "i2c-scl-falling-time-ns", &priv
->scl_fall_time_ns
);
745 dev_read_u32(bus
, "i2c-sda-hold-time-ns", &priv
->sda_hold_time_ns
);
747 ret
= reset_get_bulk(bus
, &priv
->resets
);
749 if (ret
!= -ENOTSUPP
)
750 dev_warn(bus
, "Can't get reset: %d\n", ret
);
752 reset_deassert_bulk(&priv
->resets
);
755 #if CONFIG_IS_ENABLED(CLK)
756 ret
= clk_get_by_index(bus
, 0, &priv
->clk
);
760 ret
= clk_enable(&priv
->clk
);
761 if (ret
&& ret
!= -ENOSYS
&& ret
!= -ENOTSUPP
) {
762 clk_free(&priv
->clk
);
763 dev_err(bus
, "failed to enable clock\n");
771 int designware_i2c_probe(struct udevice
*bus
)
773 struct dw_i2c
*priv
= dev_get_priv(bus
);
776 comp_type
= readl(&priv
->regs
->comp_type
);
777 if (comp_type
!= DW_I2C_COMP_TYPE
) {
778 log_err("I2C bus %s has unknown type %#x\n", bus
->name
,
783 log_debug("I2C bus %s version %#x\n", bus
->name
,
784 readl(&priv
->regs
->comp_version
));
786 return __dw_i2c_init(priv
->regs
, 0, 0);
789 int designware_i2c_remove(struct udevice
*dev
)
791 struct dw_i2c
*priv
= dev_get_priv(dev
);
793 #if CONFIG_IS_ENABLED(CLK)
794 clk_disable(&priv
->clk
);
795 clk_free(&priv
->clk
);
798 return reset_release_bulk(&priv
->resets
);
801 const struct dm_i2c_ops designware_i2c_ops
= {
802 .xfer
= designware_i2c_xfer
,
803 .probe_chip
= designware_i2c_probe_chip
,
804 .set_bus_speed
= designware_i2c_set_bus_speed
,
807 static const struct udevice_id designware_i2c_ids
[] = {
808 { .compatible
= "snps,designware-i2c" },
812 U_BOOT_DRIVER(i2c_designware
) = {
813 .name
= "i2c_designware",
815 .of_match
= designware_i2c_ids
,
816 .of_to_plat
= designware_i2c_of_to_plat
,
817 .probe
= designware_i2c_probe
,
818 .priv_auto
= sizeof(struct dw_i2c
),
819 .remove
= designware_i2c_remove
,
820 .flags
= DM_FLAG_OS_PREPARE
,
821 .ops
= &designware_i2c_ops
,
824 #endif /* CONFIG_DM_I2C */