2 * Copyright (c) 2016, Google Inc
5 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clk.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/pinmux.h>
16 #include "s3c24x0_i2c.h"
18 DECLARE_GLOBAL_DATA_PTR
;
20 /* HSI2C-specific register description */
22 /* I2C_CTL Register bits */
23 #define HSI2C_FUNC_MODE_I2C (1u << 0)
24 #define HSI2C_MASTER (1u << 3)
25 #define HSI2C_RXCHON (1u << 6) /* Write/Send */
26 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */
27 #define HSI2C_SW_RST (1u << 31)
29 /* I2C_FIFO_CTL Register bits */
30 #define HSI2C_RXFIFO_EN (1u << 0)
31 #define HSI2C_TXFIFO_EN (1u << 1)
32 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
33 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
35 /* I2C_TRAILING_CTL Register bits */
36 #define HSI2C_TRAILING_COUNT (0xff)
38 /* I2C_INT_EN Register bits */
39 #define HSI2C_TX_UNDERRUN_EN (1u << 2)
40 #define HSI2C_TX_OVERRUN_EN (1u << 3)
41 #define HSI2C_RX_UNDERRUN_EN (1u << 4)
42 #define HSI2C_RX_OVERRUN_EN (1u << 5)
43 #define HSI2C_INT_TRAILING_EN (1u << 6)
44 #define HSI2C_INT_I2C_EN (1u << 9)
46 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
47 HSI2C_TX_OVERRUN_EN |\
48 HSI2C_RX_UNDERRUN_EN |\
49 HSI2C_RX_OVERRUN_EN |\
50 HSI2C_INT_TRAILING_EN)
52 /* I2C_CONF Register bits */
53 #define HSI2C_AUTO_MODE (1u << 31)
54 #define HSI2C_10BIT_ADDR_MODE (1u << 30)
55 #define HSI2C_HS_MODE (1u << 29)
57 /* I2C_AUTO_CONF Register bits */
58 #define HSI2C_READ_WRITE (1u << 16)
59 #define HSI2C_STOP_AFTER_TRANS (1u << 17)
60 #define HSI2C_MASTER_RUN (1u << 31)
62 /* I2C_TIMEOUT Register bits */
63 #define HSI2C_TIMEOUT_EN (1u << 31)
65 /* I2C_TRANS_STATUS register bits */
66 #define HSI2C_MASTER_BUSY (1u << 17)
67 #define HSI2C_SLAVE_BUSY (1u << 16)
68 #define HSI2C_TIMEOUT_AUTO (1u << 4)
69 #define HSI2C_NO_DEV (1u << 3)
70 #define HSI2C_NO_DEV_ACK (1u << 2)
71 #define HSI2C_TRANS_ABORT (1u << 1)
72 #define HSI2C_TRANS_SUCCESS (1u << 0)
73 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
74 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
76 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
79 /* I2C_FIFO_STAT Register bits */
80 #define HSI2C_RX_FIFO_EMPTY (1u << 24)
81 #define HSI2C_RX_FIFO_FULL (1u << 23)
82 #define HSI2C_TX_FIFO_EMPTY (1u << 8)
83 #define HSI2C_TX_FIFO_FULL (1u << 7)
84 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
85 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
87 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
89 #define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
92 * Wait for transfer completion.
94 * This function reads the interrupt status register waiting for the INT_I2C
95 * bit to be set, which indicates copletion of a transaction.
97 * @param i2c: pointer to the appropriate register bank
99 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
100 * the status bits do not get set in time, or an approrpiate error
101 * value in case of transfer errors.
103 static int hsi2c_wait_for_trx(struct exynos5_hsi2c
*i2c
)
105 int i
= HSI2C_TIMEOUT_US
;
108 u32 int_status
= readl(&i2c
->usi_int_stat
);
110 if (int_status
& HSI2C_INT_I2C_EN
) {
111 u32 trans_status
= readl(&i2c
->usi_trans_status
);
113 /* Deassert pending interrupt. */
114 writel(int_status
, &i2c
->usi_int_stat
);
116 if (trans_status
& HSI2C_NO_DEV_ACK
) {
117 debug("%s: no ACK from device\n", __func__
);
120 if (trans_status
& HSI2C_NO_DEV
) {
121 debug("%s: no device\n", __func__
);
124 if (trans_status
& HSI2C_TRANS_ABORT
) {
125 debug("%s: arbitration lost\n", __func__
);
128 if (trans_status
& HSI2C_TIMEOUT_AUTO
) {
129 debug("%s: device timed out\n", __func__
);
136 debug("%s: transaction timeout!\n", __func__
);
140 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus
*i2c_bus
)
142 struct exynos5_hsi2c
*hsregs
= i2c_bus
->hsregs
;
144 unsigned int op_clk
= i2c_bus
->clock_frequency
;
145 unsigned int i
= 0, utemp0
= 0, utemp1
= 0;
146 unsigned int t_ftl_cycle
;
148 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
149 clkin
= get_i2c_clk();
154 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
155 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
156 * uTemp1 = (TSCLK_L + TSCLK_H + 2)
157 * uTemp2 = TSCLK_L + TSCLK_H
159 t_ftl_cycle
= (readl(&hsregs
->usi_conf
) >> 16) & 0x7;
160 utemp0
= (clkin
/ op_clk
) - 8 - 2 * t_ftl_cycle
;
162 /* CLK_DIV max is 256 */
163 for (i
= 0; i
< 256; i
++) {
164 utemp1
= utemp0
/ (i
+ 1);
165 if ((utemp1
< 512) && (utemp1
> 4)) {
166 i2c_bus
->clk_cycle
= utemp1
- 2;
167 i2c_bus
->clk_div
= i
;
174 static void hsi2c_ch_init(struct s3c24x0_i2c_bus
*i2c_bus
)
176 struct exynos5_hsi2c
*hsregs
= i2c_bus
->hsregs
;
177 unsigned int t_sr_release
;
178 unsigned int n_clkdiv
;
179 unsigned int t_start_su
, t_start_hd
;
180 unsigned int t_stop_su
;
181 unsigned int t_data_su
, t_data_hd
;
182 unsigned int t_scl_l
, t_scl_h
;
188 n_clkdiv
= i2c_bus
->clk_div
;
189 t_scl_l
= i2c_bus
->clk_cycle
/ 2;
190 t_scl_h
= i2c_bus
->clk_cycle
/ 2;
191 t_start_su
= t_scl_l
;
192 t_start_hd
= t_scl_l
;
194 t_data_su
= t_scl_l
/ 2;
195 t_data_hd
= t_scl_l
/ 2;
196 t_sr_release
= i2c_bus
->clk_cycle
;
198 i2c_timing_s1
= t_start_su
<< 24 | t_start_hd
<< 16 | t_stop_su
<< 8;
199 i2c_timing_s2
= t_data_su
<< 24 | t_scl_l
<< 8 | t_scl_h
<< 0;
200 i2c_timing_s3
= n_clkdiv
<< 16 | t_sr_release
<< 0;
201 i2c_timing_sla
= t_data_hd
<< 0;
203 writel(HSI2C_TRAILING_COUNT
, &hsregs
->usi_trailing_ctl
);
205 /* Clear to enable Timeout */
206 clrsetbits_le32(&hsregs
->usi_timeout
, HSI2C_TIMEOUT_EN
, 0);
209 writel(readl(&hsregs
->usi_conf
) | HSI2C_AUTO_MODE
, &hsregs
->usi_conf
);
211 /* Enable completion conditions' reporting. */
212 writel(HSI2C_INT_I2C_EN
, &hsregs
->usi_int_en
);
215 writel(HSI2C_RXFIFO_EN
| HSI2C_TXFIFO_EN
, &hsregs
->usi_fifo_ctl
);
217 /* Currently operating in Fast speed mode. */
218 writel(i2c_timing_s1
, &hsregs
->usi_timing_fs1
);
219 writel(i2c_timing_s2
, &hsregs
->usi_timing_fs2
);
220 writel(i2c_timing_s3
, &hsregs
->usi_timing_fs3
);
221 writel(i2c_timing_sla
, &hsregs
->usi_timing_sla
);
224 /* SW reset for the high speed bus */
225 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus
*i2c_bus
)
227 struct exynos5_hsi2c
*i2c
= i2c_bus
->hsregs
;
230 /* Set and clear the bit for reset */
231 i2c_ctl
= readl(&i2c
->usi_ctl
);
232 i2c_ctl
|= HSI2C_SW_RST
;
233 writel(i2c_ctl
, &i2c
->usi_ctl
);
235 i2c_ctl
= readl(&i2c
->usi_ctl
);
236 i2c_ctl
&= ~HSI2C_SW_RST
;
237 writel(i2c_ctl
, &i2c
->usi_ctl
);
239 /* Initialize the configure registers */
240 hsi2c_ch_init(i2c_bus
);
244 * Poll the appropriate bit of the fifo status register until the interface is
245 * ready to process the next byte or timeout expires.
247 * In addition to the FIFO status register this function also polls the
248 * interrupt status register to be able to detect unexpected transaction
251 * When FIFO is ready to process the next byte, this function returns I2C_OK.
252 * If in course of polling the INT_I2C assertion is detected, the function
253 * returns I2C_NOK. If timeout happens before any of the above conditions is
254 * met - the function returns I2C_NOK_TOUT;
256 * @param i2c: pointer to the appropriate i2c register bank.
257 * @param rx_transfer: set to True if the receive transaction is in progress.
258 * @return: as described above.
260 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c
*i2c
, bool rx_transfer
)
262 u32 fifo_bit
= rx_transfer
? HSI2C_RX_FIFO_EMPTY
: HSI2C_TX_FIFO_FULL
;
263 int i
= HSI2C_TIMEOUT_US
;
265 while (readl(&i2c
->usi_fifo_stat
) & fifo_bit
) {
266 if (readl(&i2c
->usi_int_stat
) & HSI2C_INT_I2C_EN
) {
268 * There is a chance that assertion of
269 * HSI2C_INT_I2C_EN and deassertion of
270 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
271 * give FIFO status priority and check it one more
272 * time before reporting interrupt. The interrupt will
273 * be reported next time this function is called.
276 !(readl(&i2c
->usi_fifo_stat
) & fifo_bit
))
281 debug("%s: FIFO polling timeout!\n", __func__
);
290 * Preapre hsi2c transaction, either read or write.
292 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
295 * @param i2c: pointer to the appropriate i2c register bank.
296 * @param chip: slave address on the i2c bus (with read/write bit exlcuded)
297 * @param len: number of bytes expected to be sent or received
298 * @param rx_transfer: set to true for receive transactions
299 * @param: issue_stop: set to true if i2c stop condition should be generated
300 * after this transaction.
301 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
304 static int hsi2c_prepare_transaction(struct exynos5_hsi2c
*i2c
,
312 conf
= len
| HSI2C_MASTER_RUN
;
315 conf
|= HSI2C_STOP_AFTER_TRANS
;
317 /* Clear to enable Timeout */
318 writel(readl(&i2c
->usi_timeout
) & ~HSI2C_TIMEOUT_EN
, &i2c
->usi_timeout
);
320 /* Set slave address */
321 writel(HSI2C_SLV_ADDR_MAS(chip
), &i2c
->i2c_addr
);
324 /* i2c master, read transaction */
325 writel((HSI2C_RXCHON
| HSI2C_FUNC_MODE_I2C
| HSI2C_MASTER
),
328 /* read up to len bytes, stop after transaction is finished */
329 writel(conf
| HSI2C_READ_WRITE
, &i2c
->usi_auto_conf
);
331 /* i2c master, write transaction */
332 writel((HSI2C_TXCHON
| HSI2C_FUNC_MODE_I2C
| HSI2C_MASTER
),
335 /* write up to len bytes, stop after transaction is finished */
336 writel(conf
, &i2c
->usi_auto_conf
);
339 /* Reset all pending interrupt status bits we care about, if any */
340 writel(HSI2C_INT_I2C_EN
, &i2c
->usi_int_stat
);
346 * Wait while i2c bus is settling down (mostly stop gets completed).
348 static int hsi2c_wait_while_busy(struct exynos5_hsi2c
*i2c
)
350 int i
= HSI2C_TIMEOUT_US
;
352 while (readl(&i2c
->usi_trans_status
) & HSI2C_MASTER_BUSY
) {
354 debug("%s: bus busy\n", __func__
);
362 static int hsi2c_write(struct exynos5_hsi2c
*i2c
,
364 unsigned char addr
[],
366 unsigned char data
[],
373 /* Writes of zero length not supported in auto mode. */
374 debug("%s: zero length writes not supported\n", __func__
);
378 rv
= hsi2c_prepare_transaction
379 (i2c
, chip
, len
+ alen
, false, issue_stop
);
383 /* Move address, if any, and the data, if any, into the FIFO. */
384 for (i
= 0; i
< alen
; i
++) {
385 rv
= hsi2c_poll_fifo(i2c
, false);
387 debug("%s: address write failed\n", __func__
);
390 writel(addr
[i
], &i2c
->usi_txdata
);
393 for (i
= 0; i
< len
; i
++) {
394 rv
= hsi2c_poll_fifo(i2c
, false);
396 debug("%s: data write failed\n", __func__
);
399 writel(data
[i
], &i2c
->usi_txdata
);
402 rv
= hsi2c_wait_for_trx(i2c
);
406 int tmp_ret
= hsi2c_wait_while_busy(i2c
);
411 writel(HSI2C_FUNC_MODE_I2C
, &i2c
->usi_ctl
); /* done */
415 static int hsi2c_read(struct exynos5_hsi2c
*i2c
,
417 unsigned char addr
[],
419 unsigned char data
[],
423 bool drop_data
= false;
426 /* Reads of zero length not supported in auto mode. */
427 debug("%s: zero length read adjusted\n", __func__
);
433 /* Internal register adress needs to be written first. */
434 rv
= hsi2c_write(i2c
, chip
, addr
, alen
, NULL
, 0, false);
439 rv
= hsi2c_prepare_transaction(i2c
, chip
, len
, true, true);
444 for (i
= 0; i
< len
; i
++) {
445 rv
= hsi2c_poll_fifo(i2c
, true);
450 data
[i
] = readl(&i2c
->usi_rxdata
);
453 rv
= hsi2c_wait_for_trx(i2c
);
456 tmp_ret
= hsi2c_wait_while_busy(i2c
);
460 writel(HSI2C_FUNC_MODE_I2C
, &i2c
->usi_ctl
); /* done */
464 static int exynos_hs_i2c_xfer(struct udevice
*dev
, struct i2c_msg
*msg
,
467 struct s3c24x0_i2c_bus
*i2c_bus
= dev_get_priv(dev
);
468 struct exynos5_hsi2c
*hsregs
= i2c_bus
->hsregs
;
471 for (; nmsgs
> 0; nmsgs
--, msg
++) {
472 if (msg
->flags
& I2C_M_RD
) {
473 ret
= hsi2c_read(hsregs
, msg
->addr
, 0, 0, msg
->buf
,
476 ret
= hsi2c_write(hsregs
, msg
->addr
, 0, 0, msg
->buf
,
480 exynos5_i2c_reset(i2c_bus
);
488 static int s3c24x0_i2c_set_bus_speed(struct udevice
*dev
, unsigned int speed
)
490 struct s3c24x0_i2c_bus
*i2c_bus
= dev_get_priv(dev
);
492 i2c_bus
->clock_frequency
= speed
;
494 if (hsi2c_get_clk_details(i2c_bus
))
496 hsi2c_ch_init(i2c_bus
);
501 static int s3c24x0_i2c_probe(struct udevice
*dev
, uint chip
, uint chip_flags
)
503 struct s3c24x0_i2c_bus
*i2c_bus
= dev_get_priv(dev
);
510 * What is needed is to send the chip address and verify that the
511 * address was <ACK>ed (i.e. there was a chip at that address which
512 * drove the data line low).
514 ret
= hsi2c_read(i2c_bus
->hsregs
, chip
, 0, 0, buf
, 1);
516 return ret
!= I2C_OK
;
519 static int s3c_i2c_ofdata_to_platdata(struct udevice
*dev
)
521 const void *blob
= gd
->fdt_blob
;
522 struct s3c24x0_i2c_bus
*i2c_bus
= dev_get_priv(dev
);
525 node
= dev_of_offset(dev
);
527 i2c_bus
->hsregs
= (struct exynos5_hsi2c
*)devfdt_get_addr(dev
);
529 i2c_bus
->id
= pinmux_decode_periph_id(blob
, node
);
531 i2c_bus
->clock_frequency
= fdtdec_get_int(blob
, node
,
532 "clock-frequency", 100000);
533 i2c_bus
->node
= node
;
534 i2c_bus
->bus_num
= dev
->seq
;
536 exynos_pinmux_config(i2c_bus
->id
, PINMUX_FLAG_HS_MODE
);
538 i2c_bus
->active
= true;
543 static const struct dm_i2c_ops exynos_hs_i2c_ops
= {
544 .xfer
= exynos_hs_i2c_xfer
,
545 .probe_chip
= s3c24x0_i2c_probe
,
546 .set_bus_speed
= s3c24x0_i2c_set_bus_speed
,
549 static const struct udevice_id exynos_hs_i2c_ids
[] = {
550 { .compatible
= "samsung,exynos5-hsi2c" },
554 U_BOOT_DRIVER(hs_i2c
) = {
555 .name
= "i2c_s3c_hs",
557 .of_match
= exynos_hs_i2c_ids
,
558 .ofdata_to_platdata
= s3c_i2c_ofdata_to_platdata
,
559 .priv_auto_alloc_size
= sizeof(struct s3c24x0_i2c_bus
),
560 .ops
= &exynos_hs_i2c_ops
,