2 * Copyright 2006,2009 Freescale Semiconductor, Inc.
4 * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Changes for multibus/multiadapter I2C support.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * Version 2 as published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <i2c.h> /* Functional interface */
26 #include <asm/fsl_i2c.h> /* HW definitions */
28 /* The maximum number of microseconds we will wait until another master has
29 * released the bus. If not defined in the board header file, then use a
32 #ifndef CONFIG_I2C_MBB_TIMEOUT
33 #define CONFIG_I2C_MBB_TIMEOUT 100000
36 /* The maximum number of microseconds we will wait for a read or write
37 * operation to complete. If not defined in the board header file, then use a
40 #ifndef CONFIG_I2C_TIMEOUT
41 #define CONFIG_I2C_TIMEOUT 10000
44 #define I2C_READ_BIT 1
45 #define I2C_WRITE_BIT 0
47 DECLARE_GLOBAL_DATA_PTR
;
49 static const struct fsl_i2c
*i2c_dev
[4] = {
50 (struct fsl_i2c
*)(CONFIG_SYS_IMMR
+ CONFIG_SYS_FSL_I2C_OFFSET
),
51 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
52 (struct fsl_i2c
*)(CONFIG_SYS_IMMR
+ CONFIG_SYS_FSL_I2C2_OFFSET
),
54 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
55 (struct fsl_i2c
*)(CONFIG_SYS_IMMR
+ CONFIG_SYS_FSL_I2C3_OFFSET
),
57 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
58 (struct fsl_i2c
*)(CONFIG_SYS_IMMR
+ CONFIG_SYS_FSL_I2C4_OFFSET
)
62 /* I2C speed map for a DFSR value of 1 */
65 * Map I2C frequency dividers to FDR and DFSR values
67 * This structure is used to define the elements of a table that maps I2C
68 * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
69 * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
70 * Sampling Rate (DFSR) registers.
72 * The actual table should be defined in the board file, and it must be called
73 * fsl_i2c_speed_map[].
75 * The last entry of the table must have a value of {-1, X}, where X is same
76 * FDR/DFSR values as the second-to-last entry. This guarantees that any
77 * search through the array will always find a match.
79 * The values of the divider must be in increasing numerical order, i.e.
80 * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
82 * For this table, the values are based on a value of 1 for the DFSR
83 * register. See the application note AN2919 "Determining the I2C Frequency
84 * Divider Ratio for SCL"
86 * ColdFire I2C frequency dividers for FDR values are different from
87 * PowerPC. The protocol to use the I2C module is still the same.
88 * A different table is defined and are based on MCF5xxx user manual.
92 unsigned short divider
;
94 } fsl_i2c_speed_map
[] = {
96 {20, 32}, {22, 33}, {24, 34}, {26, 35},
97 {28, 0}, {28, 36}, {30, 1}, {32, 37},
98 {34, 2}, {36, 38}, {40, 3}, {40, 39},
99 {44, 4}, {48, 5}, {48, 40}, {56, 6},
100 {56, 41}, {64, 42}, {68, 7}, {72, 43},
101 {80, 8}, {80, 44}, {88, 9}, {96, 41},
102 {104, 10}, {112, 42}, {128, 11}, {128, 43},
103 {144, 12}, {160, 13}, {160, 48}, {192, 14},
104 {192, 49}, {224, 50}, {240, 15}, {256, 51},
105 {288, 16}, {320, 17}, {320, 52}, {384, 18},
106 {384, 53}, {448, 54}, {480, 19}, {512, 55},
107 {576, 20}, {640, 21}, {640, 56}, {768, 22},
108 {768, 57}, {960, 23}, {896, 58}, {1024, 59},
109 {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
110 {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
111 {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
117 * Set the I2C bus speed for a given I2C device
119 * @param dev: the I2C device
120 * @i2c_clk: I2C bus clock frequency
121 * @speed: the desired speed of the bus
123 * The I2C device must be stopped before calling this function.
125 * The return value is the actual bus speed that is set.
127 static unsigned int set_i2c_bus_speed(const struct fsl_i2c
*dev
,
128 unsigned int i2c_clk
, unsigned int speed
)
130 unsigned short divider
= min(i2c_clk
/ speed
, (unsigned short) -1);
133 * We want to choose an FDR/DFSR that generates an I2C bus speed that
134 * is equal to or lower than the requested speed. That means that we
135 * want the first divider that is equal to or greater than the
136 * calculated divider.
139 u8 dfsr
, fdr
= 0x31; /* Default if no FDR found */
140 /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
141 unsigned short a
, b
, ga
, gb
;
142 unsigned long c_div
, est_div
;
144 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
145 dfsr
= CONFIG_FSL_I2C_CUSTOM_DFSR
;
147 /* Condition 1: dfsr <= 50/T */
148 dfsr
= (5 * (i2c_clk
/ 1000)) / 100000;
150 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
151 fdr
= CONFIG_FSL_I2C_CUSTOM_FDR
;
152 speed
= i2c_clk
/ divider
; /* Fake something */
154 debug("Requested speed:%d, i2c_clk:%d\n", speed
, i2c_clk
);
159 for (ga
= 0x4, a
= 10; a
<= 30; ga
++, a
+= 2) {
160 for (gb
= 0; gb
< 8; gb
++) {
162 c_div
= b
* (a
+ ((3*dfsr
)/b
)*2);
163 if ((c_div
> divider
) && (c_div
< est_div
)) {
164 unsigned short bin_gb
, bin_ga
;
168 bin_ga
= (ga
& 0x3) | ((ga
& 0x4) << 3);
169 fdr
= bin_gb
| bin_ga
;
170 speed
= i2c_clk
/ est_div
;
171 debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, "
172 "a:%d, b:%d, speed:%d\n",
173 fdr
, est_div
, ga
, gb
, a
, b
, speed
);
174 /* Condition 2 not accounted for */
175 debug("Tr <= %d ns\n",
176 (b
- 3 * dfsr
) * 1000000 /
185 debug("divider:%d, est_div:%ld, DFSR:%d\n", divider
, est_div
, dfsr
);
186 debug("FDR:0x%.2x, speed:%d\n", fdr
, speed
);
188 writeb(dfsr
, &dev
->dfsrr
); /* set default filter */
189 writeb(fdr
, &dev
->fdr
); /* set bus speed */
193 for (i
= 0; i
< ARRAY_SIZE(fsl_i2c_speed_map
); i
++)
194 if (fsl_i2c_speed_map
[i
].divider
>= divider
) {
197 fdr
= fsl_i2c_speed_map
[i
].fdr
;
198 speed
= i2c_clk
/ fsl_i2c_speed_map
[i
].divider
;
199 writeb(fdr
, &dev
->fdr
); /* set bus speed */
207 static unsigned int get_i2c_clock(int bus
)
210 return gd
->arch
.i2c2_clk
; /* I2C2 clock */
212 return gd
->arch
.i2c1_clk
; /* I2C1 clock */
215 static int fsl_i2c_fixup(const struct fsl_i2c
*dev
)
217 const unsigned long long timeout
= usec2ticks(CONFIG_I2C_MBB_TIMEOUT
);
218 unsigned long long timeval
= 0;
220 unsigned int flags
= 0;
222 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
223 unsigned int svr
= get_svr();
224 if ((SVR_SOC_VER(svr
) == SVR_8548
&& IS_SVR_REV(svr
, 3, 1)) ||
225 (SVR_REV(svr
) <= CONFIG_SYS_FSL_A004447_SVR_REV
))
229 writeb(I2C_CR_MEN
| I2C_CR_MSTA
, &dev
->cr
);
231 timeval
= get_ticks();
232 while (!(readb(&dev
->sr
) & I2C_SR_MBB
)) {
233 if ((get_ticks() - timeval
) > timeout
)
237 if (readb(&dev
->sr
) & I2C_SR_MAL
) {
238 /* SDA is stuck low */
241 writeb(I2C_CR_MSTA
| flags
, &dev
->cr
);
242 writeb(I2C_CR_MEN
| I2C_CR_MSTA
| flags
, &dev
->cr
);
247 timeval
= get_ticks();
248 while (!(readb(&dev
->sr
) & I2C_SR_MIF
)) {
249 if ((get_ticks() - timeval
) > timeout
)
255 writeb(I2C_CR_MEN
| flags
, &dev
->cr
);
262 static void fsl_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveadd
)
264 const struct fsl_i2c
*dev
;
265 const unsigned long long timeout
= usec2ticks(CONFIG_I2C_MBB_TIMEOUT
);
266 unsigned long long timeval
;
268 #ifdef CONFIG_SYS_I2C_INIT_BOARD
269 /* Call board specific i2c bus reset routine before accessing the
270 * environment, which might be in a chip on that bus. For details
271 * about this problem see doc/I2C_Edge_Conditions.
275 dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
277 writeb(0, &dev
->cr
); /* stop I2C controller */
278 udelay(5); /* let it shutdown in peace */
279 set_i2c_bus_speed(dev
, get_i2c_clock(adap
->hwadapnr
), speed
);
280 writeb(slaveadd
<< 1, &dev
->adr
);/* write slave address */
281 writeb(0x0, &dev
->sr
); /* clear status register */
282 writeb(I2C_CR_MEN
, &dev
->cr
); /* start I2C controller */
284 timeval
= get_ticks();
285 while (readb(&dev
->sr
) & I2C_SR_MBB
) {
286 if ((get_ticks() - timeval
) < timeout
)
289 if (fsl_i2c_fixup(dev
))
290 debug("i2c_init: BUS#%d failed to init\n",
296 #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
297 /* Call board specific i2c bus reset routine AFTER the bus has been
298 * initialized. Use either this callpoint or i2c_init_board;
299 * which is called before i2c_init operations.
300 * For details about this problem see doc/I2C_Edge_Conditions.
302 i2c_board_late_init();
307 i2c_wait4bus(struct i2c_adapter
*adap
)
309 struct fsl_i2c
*dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
310 unsigned long long timeval
= get_ticks();
311 const unsigned long long timeout
= usec2ticks(CONFIG_I2C_MBB_TIMEOUT
);
313 while (readb(&dev
->sr
) & I2C_SR_MBB
) {
314 if ((get_ticks() - timeval
) > timeout
)
321 static __inline__
int
322 i2c_wait(struct i2c_adapter
*adap
, int write
)
325 unsigned long long timeval
= get_ticks();
326 const unsigned long long timeout
= usec2ticks(CONFIG_I2C_TIMEOUT
);
327 struct fsl_i2c
*dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
330 csr
= readb(&dev
->sr
);
331 if (!(csr
& I2C_SR_MIF
))
333 /* Read again to allow register to stabilise */
334 csr
= readb(&dev
->sr
);
336 writeb(0x0, &dev
->sr
);
338 if (csr
& I2C_SR_MAL
) {
339 debug("i2c_wait: MAL\n");
343 if (!(csr
& I2C_SR_MCF
)) {
344 debug("i2c_wait: unfinished\n");
348 if (write
== I2C_WRITE_BIT
&& (csr
& I2C_SR_RXAK
)) {
349 debug("i2c_wait: No RXACK\n");
354 } while ((get_ticks() - timeval
) < timeout
);
356 debug("i2c_wait: timed out\n");
360 static __inline__
int
361 i2c_write_addr(struct i2c_adapter
*adap
, u8 dev
, u8 dir
, int rsta
)
363 struct fsl_i2c
*device
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
365 writeb(I2C_CR_MEN
| I2C_CR_MSTA
| I2C_CR_MTX
366 | (rsta
? I2C_CR_RSTA
: 0),
369 writeb((dev
<< 1) | dir
, &device
->dr
);
371 if (i2c_wait(adap
, I2C_WRITE_BIT
) < 0)
377 static __inline__
int
378 __i2c_write(struct i2c_adapter
*adap
, u8
*data
, int length
)
380 struct fsl_i2c
*dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
383 for (i
= 0; i
< length
; i
++) {
384 writeb(data
[i
], &dev
->dr
);
386 if (i2c_wait(adap
, I2C_WRITE_BIT
) < 0)
393 static __inline__
int
394 __i2c_read(struct i2c_adapter
*adap
, u8
*data
, int length
)
396 struct fsl_i2c
*dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
399 writeb(I2C_CR_MEN
| I2C_CR_MSTA
| ((length
== 1) ? I2C_CR_TXAK
: 0),
405 for (i
= 0; i
< length
; i
++) {
406 if (i2c_wait(adap
, I2C_READ_BIT
) < 0)
409 /* Generate ack on last next to last byte */
411 writeb(I2C_CR_MEN
| I2C_CR_MSTA
| I2C_CR_TXAK
,
414 /* Do not generate stop on last byte */
416 writeb(I2C_CR_MEN
| I2C_CR_MSTA
| I2C_CR_MTX
,
419 data
[i
] = readb(&dev
->dr
);
426 fsl_i2c_read(struct i2c_adapter
*adap
, u8 dev
, uint addr
, int alen
, u8
*data
,
429 struct fsl_i2c
*device
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
430 int i
= -1; /* signal error */
434 if (i2c_wait4bus(adap
) < 0)
437 /* To handle the need of I2C devices that require to write few bytes
438 * (more than 4 bytes of address as in the case of else part)
439 * of data before reading, Negative equivalent of length(bytes to write)
440 * is passed, but used the +ve part of len for writing data
443 /* Generate a START and send the Address and
444 * the Tx Bytes to the slave.
445 * "START: Address: Write bytes data[len]"
446 * IF part supports writing any number of bytes in contrast
447 * to the else part, which supports writing address offset
448 * of upto 4 bytes only.
449 * bytes that need to be written are passed in
450 * "data", which will eventually keep the data READ,
451 * after writing the len bytes out of it
453 if (i2c_write_addr(adap
, dev
, I2C_WRITE_BIT
, 0) != 0)
454 i
= __i2c_write(adap
, data
, len
);
459 if (length
&& i2c_write_addr(adap
, dev
, I2C_READ_BIT
, 1) != 0)
460 i
= __i2c_read(adap
, data
, length
);
462 if ((!length
|| alen
> 0) &&
463 i2c_write_addr(adap
, dev
, I2C_WRITE_BIT
, 0) != 0 &&
464 __i2c_write(adap
, &a
[4 - alen
], alen
) == alen
)
465 i
= 0; /* No error so far */
468 i2c_write_addr(adap
, dev
, I2C_READ_BIT
, alen
? 1 : 0) != 0)
469 i
= __i2c_read(adap
, data
, length
);
472 writeb(I2C_CR_MEN
, &device
->cr
);
474 if (i2c_wait4bus(adap
)) /* Wait until STOP */
475 debug("i2c_read: wait4bus timed out\n");
484 fsl_i2c_write(struct i2c_adapter
*adap
, u8 dev
, uint addr
, int alen
,
485 u8
*data
, int length
)
487 struct fsl_i2c
*device
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
488 int i
= -1; /* signal error */
491 if (i2c_wait4bus(adap
) < 0)
494 if (i2c_write_addr(adap
, dev
, I2C_WRITE_BIT
, 0) != 0 &&
495 __i2c_write(adap
, &a
[4 - alen
], alen
) == alen
) {
496 i
= __i2c_write(adap
, data
, length
);
499 writeb(I2C_CR_MEN
, &device
->cr
);
500 if (i2c_wait4bus(adap
)) /* Wait until STOP */
501 debug("i2c_write: wait4bus timed out\n");
510 fsl_i2c_probe(struct i2c_adapter
*adap
, uchar chip
)
512 struct fsl_i2c
*dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
513 /* For unknow reason the controller will ACK when
514 * probing for a slave with the same address, so skip
517 if (chip
== (readb(&dev
->adr
) >> 1))
520 return fsl_i2c_read(adap
, chip
, 0, 0, NULL
, 0);
523 static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter
*adap
,
526 struct fsl_i2c
*dev
= (struct fsl_i2c
*)i2c_dev
[adap
->hwadapnr
];
528 writeb(0, &dev
->cr
); /* stop controller */
529 set_i2c_bus_speed(dev
, get_i2c_clock(adap
->hwadapnr
), speed
);
530 writeb(I2C_CR_MEN
, &dev
->cr
); /* start controller */
536 * Register fsl i2c adapters
538 U_BOOT_I2C_ADAP_COMPLETE(fsl_0
, fsl_i2c_init
, fsl_i2c_probe
, fsl_i2c_read
,
539 fsl_i2c_write
, fsl_i2c_set_bus_speed
,
540 CONFIG_SYS_FSL_I2C_SPEED
, CONFIG_SYS_FSL_I2C_SLAVE
,
542 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
543 U_BOOT_I2C_ADAP_COMPLETE(fsl_1
, fsl_i2c_init
, fsl_i2c_probe
, fsl_i2c_read
,
544 fsl_i2c_write
, fsl_i2c_set_bus_speed
,
545 CONFIG_SYS_FSL_I2C2_SPEED
, CONFIG_SYS_FSL_I2C2_SLAVE
,
548 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
549 U_BOOT_I2C_ADAP_COMPLETE(fsl_2
, fsl_i2c_init
, fsl_i2c_probe
, fsl_i2c_read
,
550 fsl_i2c_write
, fsl_i2c_set_bus_speed
,
551 CONFIG_SYS_FSL_I2C3_SPEED
, CONFIG_SYS_FSL_I2C3_SLAVE
,
554 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
555 U_BOOT_I2C_ADAP_COMPLETE(fsl_3
, fsl_i2c_init
, fsl_i2c_probe
, fsl_i2c_read
,
556 fsl_i2c_write
, fsl_i2c_set_bus_speed
,
557 CONFIG_SYS_FSL_I2C4_SPEED
, CONFIG_SYS_FSL_I2C4_SLAVE
,