drivers/i2c/fsl_i2c.c

   1 /*
   2  * Copyright 2006,2009 Freescale Semiconductor, Inc.
   3  *
   4  * 2012, Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  * Changes for multibus/multiadapter I2C support.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <command.h>
  12 #include <i2c.h>                /* Functional interface */
  13 #include <asm/io.h>
  14 #include <asm/fsl_i2c.h>        /* HW definitions */
  15 #include <dm.h>
  16 #include <mapmem.h>
  17
  18 /* The maximum number of microseconds we will wait until another master has
  19  * released the bus.  If not defined in the board header file, then use a
  20  * generic value.
  21  */
  22 #ifndef CONFIG_I2C_MBB_TIMEOUT
  23 #define CONFIG_I2C_MBB_TIMEOUT  100000
  24 #endif
  25
  26 /* The maximum number of microseconds we will wait for a read or write
  27  * operation to complete.  If not defined in the board header file, then use a
  28  * generic value.
  29  */
  30 #ifndef CONFIG_I2C_TIMEOUT
  31 #define CONFIG_I2C_TIMEOUT      100000
  32 #endif
  33
  34 #define I2C_READ_BIT  1
  35 #define I2C_WRITE_BIT 0
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifndef CONFIG_DM_I2C
  40 static const struct fsl_i2c_base *i2c_base[4] = {
  41         (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C_OFFSET),
  42 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
  43         (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C2_OFFSET),
  44 #endif
  45 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
  46         (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C3_OFFSET),
  47 #endif
  48 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
  49         (struct fsl_i2c_base *)(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_I2C4_OFFSET)
  50 #endif
  51 };
  52 #endif
  53
  54 /* I2C speed map for a DFSR value of 1 */
  55
  56 #ifdef __M68K__
  57 /*
  58  * Map I2C frequency dividers to FDR and DFSR values
  59  *
  60  * This structure is used to define the elements of a table that maps I2C
  61  * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be
  62  * programmed into the Frequency Divider Ratio (FDR) and Digital Filter
  63  * Sampling Rate (DFSR) registers.
  64  *
  65  * The actual table should be defined in the board file, and it must be called
  66  * fsl_i2c_speed_map[].
  67  *
  68  * The last entry of the table must have a value of {-1, X}, where X is same
  69  * FDR/DFSR values as the second-to-last entry.  This guarantees that any
  70  * search through the array will always find a match.
  71  *
  72  * The values of the divider must be in increasing numerical order, i.e.
  73  * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider.
  74  *
  75  * For this table, the values are based on a value of 1 for the DFSR
  76  * register.  See the application note AN2919 "Determining the I2C Frequency
  77  * Divider Ratio for SCL"
  78  *
  79  * ColdFire I2C frequency dividers for FDR values are different from
  80  * PowerPC. The protocol to use the I2C module is still the same.
  81  * A different table is defined and are based on MCF5xxx user manual.
  82  *
  83  */
  84 static const struct {
  85         unsigned short divider;
  86         u8 fdr;
  87 } fsl_i2c_speed_map[] = {
  88         {20, 32}, {22, 33}, {24, 34}, {26, 35},
  89         {28, 0}, {28, 36}, {30, 1}, {32, 37},
  90         {34, 2}, {36, 38}, {40, 3}, {40, 39},
  91         {44, 4}, {48, 5}, {48, 40}, {56, 6},
  92         {56, 41}, {64, 42}, {68, 7}, {72, 43},
  93         {80, 8}, {80, 44}, {88, 9}, {96, 41},
  94         {104, 10}, {112, 42}, {128, 11}, {128, 43},
  95         {144, 12}, {160, 13}, {160, 48}, {192, 14},
  96         {192, 49}, {224, 50}, {240, 15}, {256, 51},
  97         {288, 16}, {320, 17}, {320, 52}, {384, 18},
  98         {384, 53}, {448, 54}, {480, 19}, {512, 55},
  99         {576, 20}, {640, 21}, {640, 56}, {768, 22},
 100         {768, 57}, {960, 23}, {896, 58}, {1024, 59},
 101         {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26},
 102         {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63},
 103         {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31},
 104         {-1, 31}
 105 };
 106 #endif
 107
 108 /**
 109  * Set the I2C bus speed for a given I2C device
 110  *
 111  * @param base: the I2C device registers
 112  * @i2c_clk: I2C bus clock frequency
 113  * @speed: the desired speed of the bus
 114  *
 115  * The I2C device must be stopped before calling this function.
 116  *
 117  * The return value is the actual bus speed that is set.
 118  */
 119 static uint set_i2c_bus_speed(const struct fsl_i2c_base *base,
 120                               uint i2c_clk, uint speed)
 121 {
 122         ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX);
 123
 124         /*
 125          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 126          * is equal to or lower than the requested speed.  That means that we
 127          * want the first divider that is equal to or greater than the
 128          * calculated divider.
 129          */
 130 #ifdef __PPC__
 131         u8 dfsr, fdr = 0x31; /* Default if no FDR found */
 132         /* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */
 133         ushort a, b, ga, gb;
 134         ulong c_div, est_div;
 135
 136 #ifdef CONFIG_FSL_I2C_CUSTOM_DFSR
 137         dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR;
 138 #else
 139         /* Condition 1: dfsr <= 50/T */
 140         dfsr = (5 * (i2c_clk / 1000)) / 100000;
 141 #endif
 142 #ifdef CONFIG_FSL_I2C_CUSTOM_FDR
 143         fdr = CONFIG_FSL_I2C_CUSTOM_FDR;
 144         speed = i2c_clk / divider; /* Fake something */
 145 #else
 146         debug("Requested speed:%d, i2c_clk:%d\n", speed, i2c_clk);
 147         if (!dfsr)
 148                 dfsr = 1;
 149
 150         est_div = ~0;
 151         for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) {
 152                 for (gb = 0; gb < 8; gb++) {
 153                         b = 16 << gb;
 154                         c_div = b * (a + ((3 * dfsr) / b) * 2);
 155                         if (c_div > divider && c_div < est_div) {
 156                                 ushort bin_gb, bin_ga;
 157
 158                                 est_div = c_div;
 159                                 bin_gb = gb << 2;
 160                                 bin_ga = (ga & 0x3) | ((ga & 0x4) << 3);
 161                                 fdr = bin_gb | bin_ga;
 162                                 speed = i2c_clk / est_div;
 163
 164                                 debug("FDR: 0x%.2x, ", fdr);
 165                                 debug("div: %ld, ", est_div);
 166                                 debug("ga: 0x%x, gb: 0x%x, ", ga, gb);
 167                                 debug("a: %d, b: %d, speed: %d\n", a, b, speed);
 168
 169                                 /* Condition 2 not accounted for */
 170                                 debug("Tr <= %d ns\n",
 171                                       (b - 3 * dfsr) * 1000000 /
 172                                       (i2c_clk / 1000));
 173                         }
 174                 }
 175                 if (a == 20)
 176                         a += 2;
 177                 if (a == 24)
 178                         a += 4;
 179         }
 180         debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr);
 181         debug("FDR: 0x%.2x, speed: %d\n", fdr, speed);
 182 #endif
 183         writeb(dfsr, &base->dfsrr);     /* set default filter */
 184         writeb(fdr, &base->fdr);        /* set bus speed */
 185 #else
 186         uint i;
 187
 188         for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++)
 189                 if (fsl_i2c_speed_map[i].divider >= divider) {
 190                         u8 fdr;
 191
 192                         fdr = fsl_i2c_speed_map[i].fdr;
 193                         speed = i2c_clk / fsl_i2c_speed_map[i].divider;
 194                         writeb(fdr, &base->fdr);        /* set bus speed */
 195
 196                         break;
 197                 }
 198 #endif
 199         return speed;
 200 }
 201
 202 #ifndef CONFIG_DM_I2C
 203 static uint get_i2c_clock(int bus)
 204 {
 205         if (bus)
 206                 return gd->arch.i2c2_clk;       /* I2C2 clock */
 207         else
 208                 return gd->arch.i2c1_clk;       /* I2C1 clock */
 209 }
 210 #endif
 211
 212 static int fsl_i2c_fixup(const struct fsl_i2c_base *base)
 213 {
 214         const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 215         unsigned long long timeval = 0;
 216         int ret = -1;
 217         uint flags = 0;
 218
 219 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 220         uint svr = get_svr();
 221
 222         if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
 223             (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
 224                 flags = I2C_CR_BIT6;
 225 #endif
 226
 227         writeb(I2C_CR_MEN | I2C_CR_MSTA, &base->cr);
 228
 229         timeval = get_ticks();
 230         while (!(readb(&base->sr) & I2C_SR_MBB)) {
 231                 if ((get_ticks() - timeval) > timeout)
 232                         goto err;
 233         }
 234
 235         if (readb(&base->sr) & I2C_SR_MAL) {
 236                 /* SDA is stuck low */
 237                 writeb(0, &base->cr);
 238                 udelay(100);
 239                 writeb(I2C_CR_MSTA | flags, &base->cr);
 240                 writeb(I2C_CR_MEN | I2C_CR_MSTA | flags, &base->cr);
 241         }
 242
 243         readb(&base->dr);
 244
 245         timeval = get_ticks();
 246         while (!(readb(&base->sr) & I2C_SR_MIF)) {
 247                 if ((get_ticks() - timeval) > timeout)
 248                         goto err;
 249         }
 250         ret = 0;
 251
 252 err:
 253         writeb(I2C_CR_MEN | flags, &base->cr);
 254         writeb(0, &base->sr);
 255         udelay(100);
 256
 257         return ret;
 258 }
 259
 260 static void __i2c_init(const struct fsl_i2c_base *base, int speed, int
 261                        slaveadd, int i2c_clk, int busnum)
 262 {
 263         const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 264         unsigned long long timeval;
 265
 266 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 267         /* Call board specific i2c bus reset routine before accessing the
 268          * environment, which might be in a chip on that bus. For details
 269          * about this problem see doc/I2C_Edge_Conditions.
 270          */
 271         i2c_init_board();
 272 #endif
 273         writeb(0, &base->cr);           /* stop I2C controller */
 274         udelay(5);                      /* let it shutdown in peace */
 275         set_i2c_bus_speed(base, i2c_clk, speed);
 276         writeb(slaveadd << 1, &base->adr);/* write slave address */
 277         writeb(0x0, &base->sr);         /* clear status register */
 278         writeb(I2C_CR_MEN, &base->cr);  /* start I2C controller */
 279
 280         timeval = get_ticks();
 281         while (readb(&base->sr) & I2C_SR_MBB) {
 282                 if ((get_ticks() - timeval) < timeout)
 283                         continue;
 284
 285                 if (fsl_i2c_fixup(base))
 286                         debug("i2c_init: BUS#%d failed to init\n",
 287                               busnum);
 288
 289                 break;
 290         }
 291 }
 292
 293 static int i2c_wait4bus(const struct fsl_i2c_base *base)
 294 {
 295         unsigned long long timeval = get_ticks();
 296         const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT);
 297
 298         while (readb(&base->sr) & I2C_SR_MBB) {
 299                 if ((get_ticks() - timeval) > timeout)
 300                         return -1;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static int i2c_wait(const struct fsl_i2c_base *base, int write)
 307 {
 308         u32 csr;
 309         unsigned long long timeval = get_ticks();
 310         const unsigned long long timeout = usec2ticks(CONFIG_I2C_TIMEOUT);
 311
 312         do {
 313                 csr = readb(&base->sr);
 314                 if (!(csr & I2C_SR_MIF))
 315                         continue;
 316                 /* Read again to allow register to stabilise */
 317                 csr = readb(&base->sr);
 318
 319                 writeb(0x0, &base->sr);
 320
 321                 if (csr & I2C_SR_MAL) {
 322                         debug("%s: MAL\n", __func__);
 323                         return -1;
 324                 }
 325
 326                 if (!(csr & I2C_SR_MCF))        {
 327                         debug("%s: unfinished\n", __func__);
 328                         return -1;
 329                 }
 330
 331                 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
 332                         debug("%s: No RXACK\n", __func__);
 333                         return -1;
 334                 }
 335
 336                 return 0;
 337         } while ((get_ticks() - timeval) < timeout);
 338
 339         debug("%s: timed out\n", __func__);
 340         return -1;
 341 }
 342
 343 static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev,
 344                           u8 dir, int rsta)
 345 {
 346         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 347                | (rsta ? I2C_CR_RSTA : 0),
 348                &base->cr);
 349
 350         writeb((dev << 1) | dir, &base->dr);
 351
 352         if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 353                 return 0;
 354
 355         return 1;
 356 }
 357
 358 static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data,
 359                             int length)
 360 {
 361         int i;
 362
 363         for (i = 0; i < length; i++) {
 364                 writeb(data[i], &base->dr);
 365
 366                 if (i2c_wait(base, I2C_WRITE_BIT) < 0)
 367                         break;
 368         }
 369
 370         return i;
 371 }
 372
 373 static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data,
 374                            int length)
 375 {
 376         int i;
 377
 378         writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
 379                &base->cr);
 380
 381         /* dummy read */
 382         readb(&base->dr);
 383
 384         for (i = 0; i < length; i++) {
 385                 if (i2c_wait(base, I2C_READ_BIT) < 0)
 386                         break;
 387
 388                 /* Generate ack on last next to last byte */
 389                 if (i == length - 2)
 390                         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
 391                                &base->cr);
 392
 393                 /* Do not generate stop on last byte */
 394                 if (i == length - 1)
 395                         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
 396                                &base->cr);
 397
 398                 data[i] = readb(&base->dr);
 399         }
 400
 401         return i;
 402 }
 403
 404 static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset,
 405                       int olen, u8 *data, int dlen)
 406 {
 407         int ret = -1; /* signal error */
 408
 409         if (i2c_wait4bus(base) < 0)
 410                 return -1;
 411
 412         /* Some drivers use offset lengths in excess of 4 bytes. These drivers
 413          * adhere to the following convention:
 414          * - the offset length is passed as negative (that is, the absolute
 415          *   value of olen is the actual offset length)
 416          * - the offset itself is passed in data, which is overwritten by the
 417          *   subsequent read operation
 418          */
 419         if (olen < 0) {
 420                 if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0)
 421                         ret = __i2c_write_data(base, data, -olen);
 422
 423                 if (ret != -olen)
 424                         return -1;
 425
 426                 if (dlen && i2c_write_addr(base, chip_addr,
 427                                            I2C_READ_BIT, 1) != 0)
 428                         ret = __i2c_read_data(base, data, dlen);
 429         } else {
 430                 if ((!dlen || olen > 0) &&
 431                     i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0  &&
 432                     __i2c_write_data(base, offset, olen) == olen)
 433                         ret = 0; /* No error so far */
 434
 435                 if (dlen && i2c_write_addr(base, chip_addr, I2C_READ_BIT,
 436                                            olen ? 1 : 0) != 0)
 437                         ret = __i2c_read_data(base, data, dlen);
 438         }
 439
 440         writeb(I2C_CR_MEN, &base->cr);
 441
 442         if (i2c_wait4bus(base)) /* Wait until STOP */
 443                 debug("i2c_read: wait4bus timed out\n");
 444
 445         if (ret == dlen)
 446                 return 0;
 447
 448         return -1;
 449 }
 450
 451 static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr,
 452                        u8 *offset, int olen, u8 *data, int dlen)
 453 {
 454         int ret = -1; /* signal error */
 455
 456         if (i2c_wait4bus(base) < 0)
 457                 return -1;
 458
 459         if (i2c_write_addr(base, chip_addr, I2C_WRITE_BIT, 0) != 0 &&
 460             __i2c_write_data(base, offset, olen) == olen) {
 461                 ret = __i2c_write_data(base, data, dlen);
 462         }
 463
 464         writeb(I2C_CR_MEN, &base->cr);
 465         if (i2c_wait4bus(base)) /* Wait until STOP */
 466                 debug("i2c_write: wait4bus timed out\n");
 467
 468         if (ret == dlen)
 469                 return 0;
 470
 471         return -1;
 472 }
 473
 474 static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip)
 475 {
 476         /* For unknown reason the controller will ACK when
 477          * probing for a slave with the same address, so skip
 478          * it.
 479          */
 480         if (chip == (readb(&base->adr) >> 1))
 481                 return -1;
 482
 483         return __i2c_read(base, chip, 0, 0, NULL, 0);
 484 }
 485
 486 static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base,
 487                                 uint speed, int i2c_clk)
 488 {
 489         writeb(0, &base->cr);           /* stop controller */
 490         set_i2c_bus_speed(base, i2c_clk, speed);
 491         writeb(I2C_CR_MEN, &base->cr);  /* start controller */
 492
 493         return 0;
 494 }
 495
 496 #ifndef CONFIG_DM_I2C
 497 static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 498 {
 499         __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
 500                    get_i2c_clock(adap->hwadapnr), adap->hwadapnr);
 501 }
 502
 503 static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip)
 504 {
 505         return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
 506 }
 507
 508 static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset,
 509                         int olen, u8 *data, int dlen)
 510 {
 511         u8 *o = (u8 *)&offset;
 512
 513         return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
 514                           olen, data, dlen);
 515 }
 516
 517 static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset,
 518                          int olen, u8 *data, int dlen)
 519 {
 520         u8 *o = (u8 *)&offset;
 521
 522         return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
 523                            olen, data, dlen);
 524 }
 525
 526 static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 527 {
 528         return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
 529                                    get_i2c_clock(adap->hwadapnr));
 530 }
 531
 532 /*
 533  * Register fsl i2c adapters
 534  */
 535 U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 536                          fsl_i2c_write, fsl_i2c_set_bus_speed,
 537                          CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
 538                          0)
 539 #ifdef CONFIG_SYS_FSL_I2C2_OFFSET
 540 U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 541                          fsl_i2c_write, fsl_i2c_set_bus_speed,
 542                          CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
 543                          1)
 544 #endif
 545 #ifdef CONFIG_SYS_FSL_I2C3_OFFSET
 546 U_BOOT_I2C_ADAP_COMPLETE(fsl_2, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 547                          fsl_i2c_write, fsl_i2c_set_bus_speed,
 548                          CONFIG_SYS_FSL_I2C3_SPEED, CONFIG_SYS_FSL_I2C3_SLAVE,
 549                          2)
 550 #endif
 551 #ifdef CONFIG_SYS_FSL_I2C4_OFFSET
 552 U_BOOT_I2C_ADAP_COMPLETE(fsl_3, fsl_i2c_init, fsl_i2c_probe_chip, fsl_i2c_read,
 553                          fsl_i2c_write, fsl_i2c_set_bus_speed,
 554                          CONFIG_SYS_FSL_I2C4_SPEED, CONFIG_SYS_FSL_I2C4_SLAVE,
 555                          3)
 556 #endif
 557 #else /* CONFIG_DM_I2C */
 558 static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
 559                               u32 chip_flags)
 560 {
 561         struct fsl_i2c_dev *dev = dev_get_priv(bus);
 562
 563         return __i2c_probe_chip(dev->base, chip_addr);
 564 }
 565
 566 static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed)
 567 {
 568         struct fsl_i2c_dev *dev = dev_get_priv(bus);
 569
 570         return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk);
 571 }
 572
 573 static int fsl_i2c_ofdata_to_platdata(struct udevice *bus)
 574 {
 575         struct fsl_i2c_dev *dev = dev_get_priv(bus);
 576         fdt_addr_t addr;
 577
 578         addr = dev_read_u32_default(bus, "reg", -1);
 579
 580         dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, sizeof(struct fsl_i2c_base));
 581
 582         if (!dev->base)
 583                 return -ENOMEM;
 584
 585         dev->index = dev_read_u32_default(bus, "cell-index", -1);
 586         dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr",
 587                                              0x7f);
 588         dev->speed = dev_read_u32_default(bus, "clock-frequency", 400000);
 589
 590         dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk;
 591
 592         return 0;
 593 }
 594
 595 static int fsl_i2c_probe(struct udevice *bus)
 596 {
 597         struct fsl_i2c_dev *dev = dev_get_priv(bus);
 598
 599         __i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk,
 600                    dev->index);
 601         return 0;
 602 }
 603
 604 static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
 605 {
 606         struct fsl_i2c_dev *dev = dev_get_priv(bus);
 607         struct i2c_msg *dmsg, *omsg, dummy;
 608
 609         memset(&dummy, 0, sizeof(struct i2c_msg));
 610
 611         /* We expect either two messages (one with an offset and one with the
 612          * actual data) or one message (just data)
 613          */
 614         if (nmsgs > 2 || nmsgs == 0) {
 615                 debug("%s: Only one or two messages are supported.", __func__);
 616                 return -1;
 617         }
 618
 619         omsg = nmsgs == 1 ? &dummy : msg;
 620         dmsg = nmsgs == 1 ? msg : msg + 1;
 621
 622         if (dmsg->flags & I2C_M_RD)
 623                 return __i2c_read(dev->base, dmsg->addr, omsg->buf, omsg->len,
 624                                   dmsg->buf, dmsg->len);
 625         else
 626                 return __i2c_write(dev->base, dmsg->addr, omsg->buf, omsg->len,
 627                                    dmsg->buf, dmsg->len);
 628 }
 629
 630 static const struct dm_i2c_ops fsl_i2c_ops = {
 631         .xfer           = fsl_i2c_xfer,
 632         .probe_chip     = fsl_i2c_probe_chip,
 633         .set_bus_speed  = fsl_i2c_set_bus_speed,
 634 };
 635
 636 static const struct udevice_id fsl_i2c_ids[] = {
 637         { .compatible = "fsl-i2c", },
 638         { /* sentinel */ }
 639 };
 640
 641 U_BOOT_DRIVER(i2c_fsl) = {
 642         .name = "i2c_fsl",
 643         .id = UCLASS_I2C,
 644         .of_match = fsl_i2c_ids,
 645         .probe = fsl_i2c_probe,
 646         .ofdata_to_platdata = fsl_i2c_ofdata_to_platdata,
 647         .priv_auto_alloc_size = sizeof(struct fsl_i2c_dev),
 648         .ops = &fsl_i2c_ops,
 649 };
 650
 651 #endif /* CONFIG_DM_I2C */