drivers/i2c/fsl_i2c.c

   1 /*
   2  * Copyright 2006 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18
  19 #include <common.h>
  20
  21 #ifdef CONFIG_FSL_I2C
  22 #ifdef CONFIG_HARD_I2C
  23
  24 #include <command.h>
  25 #include <i2c.h>                /* Functional interface */
  26
  27 #include <asm/io.h>
  28 #include <asm/fsl_i2c.h>        /* HW definitions */
  29
  30 #define I2C_TIMEOUT     (CFG_HZ / 4)
  31
  32 #define I2C_READ_BIT  1
  33 #define I2C_WRITE_BIT 0
  34
  35 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
  36  * Default is bus 0.  This is necessary because the DDR initialization
  37  * runs from ROM, and we can't switch buses because we can't modify
  38  * the global variables.
  39  */
  40 #ifdef CFG_SPD_BUS_NUM
  41 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
  42 #else
  43 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
  44 #endif
  45
  46 static volatile struct fsl_i2c *i2c_dev[2] = {
  47         (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
  48 #ifdef CFG_I2C2_OFFSET
  49         (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
  50 #endif
  51 };
  52
  53 void
  54 i2c_init(int speed, int slaveadd)
  55 {
  56         volatile struct fsl_i2c *dev;
  57
  58         dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
  59
  60         writeb(0, &dev->cr);                    /* stop I2C controller */
  61         udelay(5);                              /* let it shutdown in peace */
  62         writeb(0x3F, &dev->fdr);                /* set bus speed */
  63         writeb(0x3F, &dev->dfsrr);              /* set default filter */
  64         writeb(slaveadd << 1, &dev->adr);       /* write slave address */
  65         writeb(0x0, &dev->sr);                  /* clear status register */
  66         writeb(I2C_CR_MEN, &dev->cr);           /* start I2C controller */
  67
  68 #ifdef  CFG_I2C2_OFFSET
  69         dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
  70
  71         writeb(0, &dev->cr);                    /* stop I2C controller */
  72         udelay(5);                              /* let it shutdown in peace */
  73         writeb(0x3F, &dev->fdr);                /* set bus speed */
  74         writeb(0x3F, &dev->dfsrr);              /* set default filter */
  75         writeb(slaveadd << 1, &dev->adr);       /* write slave address */
  76         writeb(0x0, &dev->sr);                  /* clear status register */
  77         writeb(I2C_CR_MEN, &dev->cr);           /* start I2C controller */
  78 #endif  /* CFG_I2C2_OFFSET */
  79 }
  80
  81 static __inline__ int
  82 i2c_wait4bus(void)
  83 {
  84         ulong timeval = get_timer(0);
  85
  86         while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
  87                 if (get_timer(timeval) > I2C_TIMEOUT) {
  88                         return -1;
  89                 }
  90         }
  91
  92         return 0;
  93 }
  94
  95 static __inline__ int
  96 i2c_wait(int write)
  97 {
  98         u32 csr;
  99         ulong timeval = get_timer(0);
 100
 101         do {
 102                 csr = readb(&i2c_dev[i2c_bus_num]->sr);
 103                 if (!(csr & I2C_SR_MIF))
 104                         continue;
 105
 106                 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
 107
 108                 if (csr & I2C_SR_MAL) {
 109                         debug("i2c_wait: MAL\n");
 110                         return -1;
 111                 }
 112
 113                 if (!(csr & I2C_SR_MCF))        {
 114                         debug("i2c_wait: unfinished\n");
 115                         return -1;
 116                 }
 117
 118                 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
 119                         debug("i2c_wait: No RXACK\n");
 120                         return -1;
 121                 }
 122
 123                 return 0;
 124         } while (get_timer (timeval) < I2C_TIMEOUT);
 125
 126         debug("i2c_wait: timed out\n");
 127         return -1;
 128 }
 129
 130 static __inline__ int
 131 i2c_write_addr (u8 dev, u8 dir, int rsta)
 132 {
 133         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
 134                | (rsta ? I2C_CR_RSTA : 0),
 135                &i2c_dev[i2c_bus_num]->cr);
 136
 137         writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
 138
 139         if (i2c_wait(I2C_WRITE_BIT) < 0)
 140                 return 0;
 141
 142         return 1;
 143 }
 144
 145 static __inline__ int
 146 __i2c_write(u8 *data, int length)
 147 {
 148         int i;
 149
 150         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
 151                &i2c_dev[i2c_bus_num]->cr);
 152
 153         for (i = 0; i < length; i++) {
 154                 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
 155
 156                 if (i2c_wait(I2C_WRITE_BIT) < 0)
 157                         break;
 158         }
 159
 160         return i;
 161 }
 162
 163 static __inline__ int
 164 __i2c_read(u8 *data, int length)
 165 {
 166         int i;
 167
 168         writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
 169                &i2c_dev[i2c_bus_num]->cr);
 170
 171         /* dummy read */
 172         readb(&i2c_dev[i2c_bus_num]->dr);
 173
 174         for (i = 0; i < length; i++) {
 175                 if (i2c_wait(I2C_READ_BIT) < 0)
 176                         break;
 177
 178                 /* Generate ack on last next to last byte */
 179                 if (i == length - 2)
 180                         writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
 181                                &i2c_dev[i2c_bus_num]->cr);
 182
 183                 /* Generate stop on last byte */
 184                 if (i == length - 1)
 185                         writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
 186
 187                 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
 188         }
 189
 190         return i;
 191 }
 192
 193 int
 194 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
 195 {
 196         int i = -1; /* signal error */
 197         u8 *a = (u8*)&addr;
 198
 199         if (i2c_wait4bus() >= 0
 200             && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
 201             && __i2c_write(&a[4 - alen], alen) == alen)
 202                 i = 0; /* No error so far */
 203
 204         if (length
 205             && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0)
 206                 i = __i2c_read(data, length);
 207
 208         writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
 209
 210         if (i == length)
 211             return 0;
 212
 213         return -1;
 214 }
 215
 216 int
 217 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 218 {
 219         int i = -1; /* signal error */
 220         u8 *a = (u8*)&addr;
 221
 222         if (i2c_wait4bus() >= 0
 223             && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
 224             && __i2c_write(&a[4 - alen], alen) == alen) {
 225                 i = __i2c_write(data, length);
 226         }
 227
 228         writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
 229
 230         if (i == length)
 231             return 0;
 232
 233         return -1;
 234 }
 235
 236 int
 237 i2c_probe(uchar chip)
 238 {
 239         /* For unknow reason the controller will ACK when
 240          * probing for a slave with the same address, so skip
 241          * it.
 242          */
 243         if (chip == (readb(&i2c_dev[i2c_bus_num]->adr) >> 1))
 244                 return -1;
 245
 246         return i2c_read(chip, 0, 0, NULL, 0);
 247 }
 248
 249 uchar
 250 i2c_reg_read(uchar i2c_addr, uchar reg)
 251 {
 252         uchar buf[1];
 253
 254         i2c_read(i2c_addr, reg, 1, buf, 1);
 255
 256         return buf[0];
 257 }
 258
 259 void
 260 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
 261 {
 262         i2c_write(i2c_addr, reg, 1, &val, 1);
 263 }
 264
 265 int i2c_set_bus_num(unsigned int bus)
 266 {
 267 #ifdef CFG_I2C2_OFFSET
 268         if (bus > 1) {
 269 #else
 270         if (bus > 0) {
 271 #endif
 272                 return -1;
 273         }
 274
 275         i2c_bus_num = bus;
 276
 277         return 0;
 278 }
 279
 280 int i2c_set_bus_speed(unsigned int speed)
 281 {
 282         return -1;
 283 }
 284
 285 unsigned int i2c_get_bus_num(void)
 286 {
 287         return i2c_bus_num;
 288 }
 289
 290 unsigned int i2c_get_bus_speed(void)
 291 {
 292         return 0;
 293 }
 294 #endif /* CONFIG_HARD_I2C */
 295 #endif /* CONFIG_FSL_I2C */