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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/i2c/fti2c010.c
2 * Faraday I2C Controller
4 * (C) Copyright 2010 Faraday Technology
5 * Dante Su <dantesu@faraday-tech.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 * NOTE: This driver should be converted to driver model before June 2017.
10 * Please see doc/driver-model/i2c-howto.txt for instructions.
19 #ifndef CONFIG_SYS_I2C_SPEED
20 #define CONFIG_SYS_I2C_SPEED 5000
23 #ifndef CONFIG_SYS_I2C_SLAVE
24 #define CONFIG_SYS_I2C_SLAVE 0
27 #ifndef CONFIG_FTI2C010_CLOCK
28 #define CONFIG_FTI2C010_CLOCK clk_get_rate("I2C")
31 #ifndef CONFIG_FTI2C010_TIMEOUT
32 #define CONFIG_FTI2C010_TIMEOUT 10 /* ms */
35 /* 7-bit dev address + 1-bit read/write */
36 #define I2C_RD(dev) ((((dev) << 1) & 0xfe) | 1)
37 #define I2C_WR(dev) (((dev) << 1) & 0xfe)
39 struct fti2c010_chip
{
40 struct fti2c010_regs
*regs
;
43 static struct fti2c010_chip chip_list
[] = {
45 .regs
= (struct fti2c010_regs
*)CONFIG_FTI2C010_BASE
,
47 #ifdef CONFIG_FTI2C010_BASE1
49 .regs
= (struct fti2c010_regs
*)CONFIG_FTI2C010_BASE1
,
52 #ifdef CONFIG_FTI2C010_BASE2
54 .regs
= (struct fti2c010_regs
*)CONFIG_FTI2C010_BASE2
,
57 #ifdef CONFIG_FTI2C010_BASE3
59 .regs
= (struct fti2c010_regs
*)CONFIG_FTI2C010_BASE3
,
64 static int fti2c010_reset(struct fti2c010_chip
*chip
)
68 struct fti2c010_regs
*regs
= chip
->regs
;
70 writel(CR_I2CRST
, ®s
->cr
);
71 for (ts
= get_timer(0); get_timer(ts
) < CONFIG_FTI2C010_TIMEOUT
; ) {
72 if (!(readl(®s
->cr
) & CR_I2CRST
)) {
79 printf("fti2c010: reset timeout\n");
84 static int fti2c010_wait(struct fti2c010_chip
*chip
, uint32_t mask
)
88 struct fti2c010_regs
*regs
= chip
->regs
;
90 for (ts
= get_timer(0); get_timer(ts
) < CONFIG_FTI2C010_TIMEOUT
; ) {
91 stat
= readl(®s
->sr
);
92 if ((stat
& mask
) == mask
) {
101 static unsigned int set_i2c_bus_speed(struct fti2c010_chip
*chip
,
104 struct fti2c010_regs
*regs
= chip
->regs
;
105 unsigned int clk
= CONFIG_FTI2C010_CLOCK
;
106 unsigned int gsr
= 0;
107 unsigned int tsr
= 32;
108 unsigned int div
, rate
;
110 for (div
= 0; div
< 0x3ffff; ++div
) {
111 /* SCLout = PCLK/(2*(COUNT + 2) + GSR) */
112 rate
= clk
/ (2 * (div
+ 2) + gsr
);
117 writel(TGSR_GSR(gsr
) | TGSR_TSR(tsr
), ®s
->tgsr
);
118 writel(CDR_DIV(div
), ®s
->cdr
);
124 * Initialization, must be called once on start up, may be called
125 * repeatedly to change the speed and slave addresses.
127 static void fti2c010_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
129 struct fti2c010_chip
*chip
= chip_list
+ adap
->hwadapnr
;
134 #ifdef CONFIG_SYS_I2C_INIT_BOARD
135 /* Call board specific i2c bus reset routine before accessing the
136 * environment, which might be in a chip on that bus. For details
137 * about this problem see doc/I2C_Edge_Conditions.
144 fti2c010_reset(chip
);
146 set_i2c_bus_speed(chip
, speed
);
148 /* slave init, don't care */
152 * Probe the given I2C chip address. Returns 0 if a chip responded,
155 static int fti2c010_probe(struct i2c_adapter
*adap
, u8 dev
)
157 struct fti2c010_chip
*chip
= chip_list
+ adap
->hwadapnr
;
158 struct fti2c010_regs
*regs
= chip
->regs
;
161 /* 1. Select slave device (7bits Address + 1bit R/W) */
162 writel(I2C_WR(dev
), ®s
->dr
);
163 writel(CR_ENABLE
| CR_TBEN
| CR_START
, ®s
->cr
);
164 ret
= fti2c010_wait(chip
, SR_DT
);
168 /* 2. Select device register */
169 writel(0, ®s
->dr
);
170 writel(CR_ENABLE
| CR_TBEN
, ®s
->cr
);
171 ret
= fti2c010_wait(chip
, SR_DT
);
176 static void to_i2c_addr(u8
*buf
, uint32_t addr
, int alen
)
180 if (!buf
|| alen
<= 0)
185 shift
= (alen
- 1) * 8;
187 buf
[i
] = (u8
)(addr
>> shift
);
192 static int fti2c010_read(struct i2c_adapter
*adap
,
193 u8 dev
, uint addr
, int alen
, uchar
*buf
, int len
)
195 struct fti2c010_chip
*chip
= chip_list
+ adap
->hwadapnr
;
196 struct fti2c010_regs
*regs
= chip
->regs
;
198 uchar paddr
[4] = { 0 };
200 to_i2c_addr(paddr
, addr
, alen
);
203 * Phase A. Set register address
206 /* A.1 Select slave device (7bits Address + 1bit R/W) */
207 writel(I2C_WR(dev
), ®s
->dr
);
208 writel(CR_ENABLE
| CR_TBEN
| CR_START
, ®s
->cr
);
209 ret
= fti2c010_wait(chip
, SR_DT
);
213 /* A.2 Select device register */
214 for (pos
= 0; pos
< alen
; ++pos
) {
215 uint32_t ctrl
= CR_ENABLE
| CR_TBEN
;
217 writel(paddr
[pos
], ®s
->dr
);
218 writel(ctrl
, ®s
->cr
);
219 ret
= fti2c010_wait(chip
, SR_DT
);
225 * Phase B. Get register data
228 /* B.1 Select slave device (7bits Address + 1bit R/W) */
229 writel(I2C_RD(dev
), ®s
->dr
);
230 writel(CR_ENABLE
| CR_TBEN
| CR_START
, ®s
->cr
);
231 ret
= fti2c010_wait(chip
, SR_DT
);
235 /* B.2 Get register data */
236 for (pos
= 0; pos
< len
; ++pos
) {
237 uint32_t ctrl
= CR_ENABLE
| CR_TBEN
;
238 uint32_t stat
= SR_DR
;
240 if (pos
== len
- 1) {
241 ctrl
|= CR_NAK
| CR_STOP
;
244 writel(ctrl
, ®s
->cr
);
245 ret
= fti2c010_wait(chip
, stat
);
248 buf
[pos
] = (uchar
)(readl(®s
->dr
) & 0xFF);
254 static int fti2c010_write(struct i2c_adapter
*adap
,
255 u8 dev
, uint addr
, int alen
, u8
*buf
, int len
)
257 struct fti2c010_chip
*chip
= chip_list
+ adap
->hwadapnr
;
258 struct fti2c010_regs
*regs
= chip
->regs
;
260 uchar paddr
[4] = { 0 };
262 to_i2c_addr(paddr
, addr
, alen
);
265 * Phase A. Set register address
267 * A.1 Select slave device (7bits Address + 1bit R/W)
269 writel(I2C_WR(dev
), ®s
->dr
);
270 writel(CR_ENABLE
| CR_TBEN
| CR_START
, ®s
->cr
);
271 ret
= fti2c010_wait(chip
, SR_DT
);
275 /* A.2 Select device register */
276 for (pos
= 0; pos
< alen
; ++pos
) {
277 uint32_t ctrl
= CR_ENABLE
| CR_TBEN
;
279 writel(paddr
[pos
], ®s
->dr
);
280 writel(ctrl
, ®s
->cr
);
281 ret
= fti2c010_wait(chip
, SR_DT
);
287 * Phase B. Set register data
289 for (pos
= 0; pos
< len
; ++pos
) {
290 uint32_t ctrl
= CR_ENABLE
| CR_TBEN
;
294 writel(buf
[pos
], ®s
->dr
);
295 writel(ctrl
, ®s
->cr
);
296 ret
= fti2c010_wait(chip
, SR_DT
);
304 static unsigned int fti2c010_set_bus_speed(struct i2c_adapter
*adap
,
307 struct fti2c010_chip
*chip
= chip_list
+ adap
->hwadapnr
;
310 fti2c010_reset(chip
);
311 ret
= set_i2c_bus_speed(chip
, speed
);
317 * Register i2c adapters
319 U_BOOT_I2C_ADAP_COMPLETE(i2c_0
, fti2c010_init
, fti2c010_probe
, fti2c010_read
,
320 fti2c010_write
, fti2c010_set_bus_speed
,
321 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
,
323 #ifdef CONFIG_FTI2C010_BASE1
324 U_BOOT_I2C_ADAP_COMPLETE(i2c_1
, fti2c010_init
, fti2c010_probe
, fti2c010_read
,
325 fti2c010_write
, fti2c010_set_bus_speed
,
326 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
,
329 #ifdef CONFIG_FTI2C010_BASE2
330 U_BOOT_I2C_ADAP_COMPLETE(i2c_2
, fti2c010_init
, fti2c010_probe
, fti2c010_read
,
331 fti2c010_write
, fti2c010_set_bus_speed
,
332 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
,
335 #ifdef CONFIG_FTI2C010_BASE3
336 U_BOOT_I2C_ADAP_COMPLETE(i2c_3
, fti2c010_init
, fti2c010_probe
, fti2c010_read
,
337 fti2c010_write
, fti2c010_set_bus_speed
,
338 CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
,