2 * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
3 * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
5 * This file is based on: drivers/i2c/zynq_i2c.c,
6 * with added driver-model support and code cleanup.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/types.h>
15 #include <linux/errno.h>
22 DECLARE_GLOBAL_DATA_PTR
;
24 /* i2c register set */
25 struct cdns_i2c_regs
{
36 u32 interrupt_disable
;
39 /* Control register fields */
40 #define CDNS_I2C_CONTROL_RW 0x00000001
41 #define CDNS_I2C_CONTROL_MS 0x00000002
42 #define CDNS_I2C_CONTROL_NEA 0x00000004
43 #define CDNS_I2C_CONTROL_ACKEN 0x00000008
44 #define CDNS_I2C_CONTROL_HOLD 0x00000010
45 #define CDNS_I2C_CONTROL_SLVMON 0x00000020
46 #define CDNS_I2C_CONTROL_CLR_FIFO 0x00000040
47 #define CDNS_I2C_CONTROL_DIV_B_SHIFT 8
48 #define CDNS_I2C_CONTROL_DIV_B_MASK 0x00003F00
49 #define CDNS_I2C_CONTROL_DIV_A_SHIFT 14
50 #define CDNS_I2C_CONTROL_DIV_A_MASK 0x0000C000
52 /* Status register values */
53 #define CDNS_I2C_STATUS_RXDV 0x00000020
54 #define CDNS_I2C_STATUS_TXDV 0x00000040
55 #define CDNS_I2C_STATUS_RXOVF 0x00000080
56 #define CDNS_I2C_STATUS_BA 0x00000100
58 /* Interrupt register fields */
59 #define CDNS_I2C_INTERRUPT_COMP 0x00000001
60 #define CDNS_I2C_INTERRUPT_DATA 0x00000002
61 #define CDNS_I2C_INTERRUPT_NACK 0x00000004
62 #define CDNS_I2C_INTERRUPT_TO 0x00000008
63 #define CDNS_I2C_INTERRUPT_SLVRDY 0x00000010
64 #define CDNS_I2C_INTERRUPT_RXOVF 0x00000020
65 #define CDNS_I2C_INTERRUPT_TXOVF 0x00000040
66 #define CDNS_I2C_INTERRUPT_RXUNF 0x00000080
67 #define CDNS_I2C_INTERRUPT_ARBLOST 0x00000200
69 #define CDNS_I2C_FIFO_DEPTH 16
70 #define CDNS_I2C_TRANSFER_SIZE_MAX 255 /* Controller transfer limit */
71 #define CDNS_I2C_TRANSFER_SIZE (CDNS_I2C_TRANSFER_SIZE_MAX - 3)
73 #define CDNS_I2C_BROKEN_HOLD_BIT BIT(0)
76 static void cdns_i2c_debug_status(struct cdns_i2c_regs
*cdns_i2c
)
80 int_status
= readl(&cdns_i2c
->interrupt_status
);
82 status
= readl(&cdns_i2c
->status
);
83 if (int_status
|| status
) {
85 if (int_status
& CDNS_I2C_INTERRUPT_COMP
)
87 if (int_status
& CDNS_I2C_INTERRUPT_DATA
)
89 if (int_status
& CDNS_I2C_INTERRUPT_NACK
)
91 if (int_status
& CDNS_I2C_INTERRUPT_TO
)
93 if (int_status
& CDNS_I2C_INTERRUPT_SLVRDY
)
95 if (int_status
& CDNS_I2C_INTERRUPT_RXOVF
)
97 if (int_status
& CDNS_I2C_INTERRUPT_TXOVF
)
99 if (int_status
& CDNS_I2C_INTERRUPT_RXUNF
)
101 if (int_status
& CDNS_I2C_INTERRUPT_ARBLOST
)
103 if (status
& CDNS_I2C_STATUS_RXDV
)
105 if (status
& CDNS_I2C_STATUS_TXDV
)
107 if (status
& CDNS_I2C_STATUS_RXOVF
)
109 if (status
& CDNS_I2C_STATUS_BA
)
111 debug("TS%d ", readl(&cdns_i2c
->transfer_size
));
117 struct i2c_cdns_bus
{
119 unsigned int input_freq
;
120 struct cdns_i2c_regs __iomem
*regs
; /* register base */
126 struct cdns_i2c_platform_data
{
130 /* Wait for an interrupt */
131 static u32
cdns_i2c_wait(struct cdns_i2c_regs
*cdns_i2c
, u32 mask
)
133 int timeout
, int_status
;
135 for (timeout
= 0; timeout
< 100; timeout
++) {
136 int_status
= readl(&cdns_i2c
->interrupt_status
);
137 if (int_status
& mask
)
142 /* Clear interrupt status flags */
143 writel(int_status
& mask
, &cdns_i2c
->interrupt_status
);
145 return int_status
& mask
;
148 #define CDNS_I2C_DIVA_MAX 4
149 #define CDNS_I2C_DIVB_MAX 64
151 static int cdns_i2c_calc_divs(unsigned long *f
, unsigned long input_clk
,
152 unsigned int *a
, unsigned int *b
)
154 unsigned long fscl
= *f
, best_fscl
= *f
, actual_fscl
, temp
;
155 unsigned int div_a
, div_b
, calc_div_a
= 0, calc_div_b
= 0;
156 unsigned int last_error
, current_error
;
158 /* calculate (divisor_a+1) x (divisor_b+1) */
159 temp
= input_clk
/ (22 * fscl
);
162 * If the calculated value is negative or 0CDNS_I2C_DIVA_MAX,
163 * the fscl input is out of range. Return error.
165 if (!temp
|| (temp
> (CDNS_I2C_DIVA_MAX
* CDNS_I2C_DIVB_MAX
)))
169 for (div_a
= 0; div_a
< CDNS_I2C_DIVA_MAX
; div_a
++) {
170 div_b
= DIV_ROUND_UP(input_clk
, 22 * fscl
* (div_a
+ 1));
172 if ((div_b
< 1) || (div_b
> CDNS_I2C_DIVB_MAX
))
176 actual_fscl
= input_clk
/ (22 * (div_a
+ 1) * (div_b
+ 1));
178 if (actual_fscl
> fscl
)
181 current_error
= ((actual_fscl
> fscl
) ? (actual_fscl
- fscl
) :
182 (fscl
- actual_fscl
));
184 if (last_error
> current_error
) {
187 best_fscl
= actual_fscl
;
188 last_error
= current_error
;
199 static int cdns_i2c_set_bus_speed(struct udevice
*dev
, unsigned int speed
)
201 struct i2c_cdns_bus
*bus
= dev_get_priv(dev
);
202 u32 div_a
= 0, div_b
= 0;
203 unsigned long speed_p
= speed
;
206 if (speed
> 400000) {
207 debug("%s, failed to set clock speed to %u\n", __func__
,
212 ret
= cdns_i2c_calc_divs(&speed_p
, bus
->input_freq
, &div_a
, &div_b
);
216 debug("%s: div_a: %d, div_b: %d, input freq: %d, speed: %d/%ld\n",
217 __func__
, div_a
, div_b
, bus
->input_freq
, speed
, speed_p
);
219 writel((div_b
<< CDNS_I2C_CONTROL_DIV_B_SHIFT
) |
220 (div_a
<< CDNS_I2C_CONTROL_DIV_A_SHIFT
), &bus
->regs
->control
);
222 /* Enable master mode, ack, and 7-bit addressing */
223 setbits_le32(&bus
->regs
->control
, CDNS_I2C_CONTROL_MS
|
224 CDNS_I2C_CONTROL_ACKEN
| CDNS_I2C_CONTROL_NEA
);
229 static int cdns_i2c_write_data(struct i2c_cdns_bus
*i2c_bus
, u32 addr
, u8
*data
,
233 struct cdns_i2c_regs
*regs
= i2c_bus
->regs
;
235 /* Set the controller in Master transmit mode and clear FIFO */
236 setbits_le32(®s
->control
, CDNS_I2C_CONTROL_CLR_FIFO
);
237 clrbits_le32(®s
->control
, CDNS_I2C_CONTROL_RW
);
239 /* Check message size against FIFO depth, and set hold bus bit
240 * if it is greater than FIFO depth
242 if (len
> CDNS_I2C_FIFO_DEPTH
)
243 setbits_le32(®s
->control
, CDNS_I2C_CONTROL_HOLD
);
245 /* Clear the interrupts in status register */
246 writel(0xFF, ®s
->interrupt_status
);
248 writel(addr
, ®s
->address
);
251 writel(*(cur_data
++), ®s
->data
);
252 if (readl(®s
->transfer_size
) == CDNS_I2C_FIFO_DEPTH
) {
253 if (!cdns_i2c_wait(regs
, CDNS_I2C_INTERRUPT_COMP
)) {
254 /* Release the bus */
255 clrbits_le32(®s
->control
,
256 CDNS_I2C_CONTROL_HOLD
);
262 /* All done... release the bus */
263 if (!i2c_bus
->hold_flag
)
264 clrbits_le32(®s
->control
, CDNS_I2C_CONTROL_HOLD
);
266 /* Wait for the address and data to be sent */
267 if (!cdns_i2c_wait(regs
, CDNS_I2C_INTERRUPT_COMP
))
272 static inline bool cdns_is_hold_quirk(int hold_quirk
, int curr_recv_count
)
274 return hold_quirk
&& (curr_recv_count
== CDNS_I2C_FIFO_DEPTH
+ 1);
277 static int cdns_i2c_read_data(struct i2c_cdns_bus
*i2c_bus
, u32 addr
, u8
*data
,
281 struct cdns_i2c_regs
*regs
= i2c_bus
->regs
;
283 int updatetx
, hold_quirk
;
285 /* Check the hardware can handle the requested bytes */
286 if ((recv_count
< 0))
289 curr_recv_count
= recv_count
;
291 /* Check for the message size against the FIFO depth */
292 if (recv_count
> CDNS_I2C_FIFO_DEPTH
)
293 setbits_le32(®s
->control
, CDNS_I2C_CONTROL_HOLD
);
295 setbits_le32(®s
->control
, CDNS_I2C_CONTROL_CLR_FIFO
|
296 CDNS_I2C_CONTROL_RW
);
298 if (recv_count
> CDNS_I2C_TRANSFER_SIZE
) {
299 curr_recv_count
= CDNS_I2C_TRANSFER_SIZE
;
300 writel(curr_recv_count
, ®s
->transfer_size
);
302 writel(recv_count
, ®s
->transfer_size
);
305 /* Start reading data */
306 writel(addr
, ®s
->address
);
308 updatetx
= recv_count
> curr_recv_count
;
310 hold_quirk
= (i2c_bus
->quirks
& CDNS_I2C_BROKEN_HOLD_BIT
) && updatetx
;
313 while (readl(®s
->status
) & CDNS_I2C_STATUS_RXDV
) {
314 if (recv_count
< CDNS_I2C_FIFO_DEPTH
&&
315 !i2c_bus
->hold_flag
) {
316 clrbits_le32(®s
->control
,
317 CDNS_I2C_CONTROL_HOLD
);
319 *(cur_data
)++ = readl(®s
->data
);
323 if (cdns_is_hold_quirk(hold_quirk
, curr_recv_count
))
327 if (cdns_is_hold_quirk(hold_quirk
, curr_recv_count
)) {
328 /* wait while fifo is full */
329 while (readl(®s
->transfer_size
) !=
330 (curr_recv_count
- CDNS_I2C_FIFO_DEPTH
))
333 * Check number of bytes to be received against maximum
334 * transfer size and update register accordingly.
336 if ((recv_count
- CDNS_I2C_FIFO_DEPTH
) >
337 CDNS_I2C_TRANSFER_SIZE
) {
338 writel(CDNS_I2C_TRANSFER_SIZE
,
339 ®s
->transfer_size
);
340 curr_recv_count
= CDNS_I2C_TRANSFER_SIZE
+
343 writel(recv_count
- CDNS_I2C_FIFO_DEPTH
,
344 ®s
->transfer_size
);
345 curr_recv_count
= recv_count
;
347 } else if (recv_count
&& !hold_quirk
&& !curr_recv_count
) {
348 writel(addr
, ®s
->address
);
349 if (recv_count
> CDNS_I2C_TRANSFER_SIZE
) {
350 writel(CDNS_I2C_TRANSFER_SIZE
,
351 ®s
->transfer_size
);
352 curr_recv_count
= CDNS_I2C_TRANSFER_SIZE
;
354 writel(recv_count
, ®s
->transfer_size
);
355 curr_recv_count
= recv_count
;
360 /* Wait for the address and data to be sent */
361 if (!cdns_i2c_wait(regs
, CDNS_I2C_INTERRUPT_COMP
))
367 static int cdns_i2c_xfer(struct udevice
*dev
, struct i2c_msg
*msg
,
370 struct i2c_cdns_bus
*i2c_bus
= dev_get_priv(dev
);
374 hold_quirk
= !!(i2c_bus
->quirks
& CDNS_I2C_BROKEN_HOLD_BIT
);
378 * This controller does not give completion interrupt after a
379 * master receive message if HOLD bit is set (repeated start),
380 * resulting in SW timeout. Hence, if a receive message is
381 * followed by any other message, an error is returned
382 * indicating that this sequence is not supported.
384 for (count
= 0; (count
< nmsgs
- 1) && hold_quirk
; count
++) {
385 if (msg
[count
].flags
& I2C_M_RD
) {
386 printf("Can't do repeated start after a receive message\n");
391 i2c_bus
->hold_flag
= 1;
392 setbits_le32(&i2c_bus
->regs
->control
, CDNS_I2C_CONTROL_HOLD
);
394 i2c_bus
->hold_flag
= 0;
397 debug("i2c_xfer: %d messages\n", nmsgs
);
398 for (; nmsgs
> 0; nmsgs
--, msg
++) {
399 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
400 if (msg
->flags
& I2C_M_RD
) {
401 ret
= cdns_i2c_read_data(i2c_bus
, msg
->addr
, msg
->buf
,
404 ret
= cdns_i2c_write_data(i2c_bus
, msg
->addr
, msg
->buf
,
408 debug("i2c_write: error sending\n");
416 static int cdns_i2c_ofdata_to_platdata(struct udevice
*dev
)
418 struct i2c_cdns_bus
*i2c_bus
= dev_get_priv(dev
);
419 struct cdns_i2c_platform_data
*pdata
=
420 (struct cdns_i2c_platform_data
*)dev_get_driver_data(dev
);
422 i2c_bus
->regs
= (struct cdns_i2c_regs
*)devfdt_get_addr(dev
);
427 i2c_bus
->quirks
= pdata
->quirks
;
429 i2c_bus
->input_freq
= 100000000; /* TODO hardcode input freq for now */
434 static const struct dm_i2c_ops cdns_i2c_ops
= {
435 .xfer
= cdns_i2c_xfer
,
436 .set_bus_speed
= cdns_i2c_set_bus_speed
,
439 static const struct cdns_i2c_platform_data r1p10_i2c_def
= {
440 .quirks
= CDNS_I2C_BROKEN_HOLD_BIT
,
443 static const struct udevice_id cdns_i2c_of_match
[] = {
444 { .compatible
= "cdns,i2c-r1p10", .data
= (ulong
)&r1p10_i2c_def
},
445 { .compatible
= "cdns,i2c-r1p14" },
446 { /* end of table */ }
449 U_BOOT_DRIVER(cdns_i2c
) = {
452 .of_match
= cdns_i2c_of_match
,
453 .ofdata_to_platdata
= cdns_i2c_ofdata_to_platdata
,
454 .priv_auto_alloc_size
= sizeof(struct i2c_cdns_bus
),
455 .ops
= &cdns_i2c_ops
,