3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <gdsys_fpga.h>
12 DECLARE_GLOBAL_DATA_PTR
;
15 I2CINT_ERROR_EV
= 1 << 13,
16 I2CINT_TRANSMIT_EV
= 1 << 14,
17 I2CINT_RECEIVE_EV
= 1 << 15,
21 I2CMB_WRITE
= 1 << 10,
22 I2CMB_2BYTE
= 1 << 11,
23 I2CMB_HOLD_BUS
= 1 << 13,
24 I2CMB_NATIVE
= 2 << 14,
27 static int wait_for_int(bool read
)
32 FPGA_GET_REG(I2C_ADAP_HWNR
, i2c
.interrupt_status
, &val
);
33 while (!(val
& (I2CINT_ERROR_EV
34 | (read
? I2CINT_RECEIVE_EV
: I2CINT_TRANSMIT_EV
)))) {
39 FPGA_GET_REG(I2C_ADAP_HWNR
, i2c
.interrupt_status
, &val
);
42 return (val
& I2CINT_ERROR_EV
) ? 1 : 0;
45 static int ihs_i2c_transfer(uchar chip
, uchar
*buffer
, int len
, bool read
,
50 FPGA_SET_REG(I2C_ADAP_HWNR
, i2c
.interrupt_status
, I2CINT_ERROR_EV
51 | I2CINT_RECEIVE_EV
| I2CINT_TRANSMIT_EV
);
52 FPGA_GET_REG(I2C_ADAP_HWNR
, i2c
.interrupt_status
, &val
);
58 val
|= buffer
[1] << 8;
59 FPGA_SET_REG(I2C_ADAP_HWNR
, i2c
.write_mailbox_ext
, val
);
62 FPGA_SET_REG(I2C_ADAP_HWNR
, i2c
.write_mailbox
,
64 | (read
? 0 : I2CMB_WRITE
)
66 | ((len
> 1) ? I2CMB_2BYTE
: 0)
67 | (is_last
? 0 : I2CMB_HOLD_BUS
));
69 if (wait_for_int(read
))
73 FPGA_GET_REG(I2C_ADAP_HWNR
, i2c
.read_mailbox_ext
, &val
);
74 buffer
[0] = val
& 0xff;
82 static int ihs_i2c_address(uchar chip
, uint addr
, int alen
, bool hold_bus
)
84 int shift
= (alen
-1) * 8;
87 int transfer
= min(alen
, 2);
89 bool is_last
= alen
<= transfer
;
91 buf
[0] = addr
>> shift
;
93 buf
[1] = addr
>> (shift
- 8);
95 if (ihs_i2c_transfer(chip
, buf
, transfer
, false,
96 hold_bus
? false : is_last
))
106 static int ihs_i2c_access(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
107 int alen
, uchar
*buffer
, int len
, bool read
)
112 if (ihs_i2c_address(chip
, addr
, alen
, !read
))
116 int transfer
= min(len
, 2);
118 if (ihs_i2c_transfer(chip
, buffer
, transfer
, read
,
131 static void ihs_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
133 #ifdef CONFIG_SYS_I2C_INIT_BOARD
135 * Call board specific i2c bus reset routine before accessing the
136 * environment, which might be in a chip on that bus. For details
137 * about this problem see doc/I2C_Edge_Conditions.
143 static int ihs_i2c_probe(struct i2c_adapter
*adap
, uchar chip
)
147 if (ihs_i2c_transfer(chip
, buffer
, 0, true, true))
153 static int ihs_i2c_read(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
154 int alen
, uchar
*buffer
, int len
)
156 return ihs_i2c_access(adap
, chip
, addr
, alen
, buffer
, len
, true);
159 static int ihs_i2c_write(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
160 int alen
, uchar
*buffer
, int len
)
162 return ihs_i2c_access(adap
, chip
, addr
, alen
, buffer
, len
, false);
165 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter
*adap
,
168 if (speed
!= adap
->speed
)
174 * Register IHS i2c adapters
176 #ifdef CONFIG_SYS_I2C_IHS_CH0
177 U_BOOT_I2C_ADAP_COMPLETE(ihs0
, ihs_i2c_init
, ihs_i2c_probe
,
178 ihs_i2c_read
, ihs_i2c_write
,
179 ihs_i2c_set_bus_speed
,
180 CONFIG_SYS_I2C_IHS_SPEED_0
,
181 CONFIG_SYS_I2C_IHS_SLAVE_0
, 0)
183 #ifdef CONFIG_SYS_I2C_IHS_CH1
184 U_BOOT_I2C_ADAP_COMPLETE(ihs1
, ihs_i2c_init
, ihs_i2c_probe
,
185 ihs_i2c_read
, ihs_i2c_write
,
186 ihs_i2c_set_bus_speed
,
187 CONFIG_SYS_I2C_IHS_SPEED_1
,
188 CONFIG_SYS_I2C_IHS_SLAVE_1
, 1)
190 #ifdef CONFIG_SYS_I2C_IHS_CH2
191 U_BOOT_I2C_ADAP_COMPLETE(ihs2
, ihs_i2c_init
, ihs_i2c_probe
,
192 ihs_i2c_read
, ihs_i2c_write
,
193 ihs_i2c_set_bus_speed
,
194 CONFIG_SYS_I2C_IHS_SPEED_2
,
195 CONFIG_SYS_I2C_IHS_SLAVE_2
, 2)
197 #ifdef CONFIG_SYS_I2C_IHS_CH3
198 U_BOOT_I2C_ADAP_COMPLETE(ihs3
, ihs_i2c_init
, ihs_i2c_probe
,
199 ihs_i2c_read
, ihs_i2c_write
,
200 ihs_i2c_set_bus_speed
,
201 CONFIG_SYS_I2C_IHS_SPEED_3
,
202 CONFIG_SYS_I2C_IHS_SLAVE_3
, 3)