2 * Copyright 2013 Broadcom Corporation.
4 * SPDX-License-Identifier: GPL-2.0+
6 * NOTE: This driver should be converted to driver model before June 2017.
7 * Please see doc/driver-model/i2c-howto.txt for instructions.
12 #include <linux/errno.h>
13 #include <asm/arch/sysmap.h>
14 #include <asm/kona-common/clk.h>
17 /* Hardware register offsets and field defintions */
18 #define CS_OFFSET 0x00000020
19 #define CS_ACK_SHIFT 3
20 #define CS_ACK_MASK 0x00000008
21 #define CS_ACK_CMD_GEN_START 0x00000000
22 #define CS_ACK_CMD_GEN_RESTART 0x00000001
23 #define CS_CMD_SHIFT 1
24 #define CS_CMD_CMD_NO_ACTION 0x00000000
25 #define CS_CMD_CMD_START_RESTART 0x00000001
26 #define CS_CMD_CMD_STOP 0x00000002
28 #define CS_EN_CMD_ENABLE_BSC 0x00000001
30 #define TIM_OFFSET 0x00000024
31 #define TIM_PRESCALE_SHIFT 6
33 #define TIM_NO_DIV_SHIFT 2
34 #define TIM_DIV_SHIFT 0
36 #define DAT_OFFSET 0x00000028
38 #define TOUT_OFFSET 0x0000002c
40 #define TXFCR_OFFSET 0x0000003c
41 #define TXFCR_FIFO_FLUSH_MASK 0x00000080
42 #define TXFCR_FIFO_EN_MASK 0x00000040
44 #define IER_OFFSET 0x00000044
45 #define IER_READ_COMPLETE_INT_MASK 0x00000010
46 #define IER_I2C_INT_EN_MASK 0x00000008
47 #define IER_FIFO_INT_EN_MASK 0x00000002
48 #define IER_NOACK_EN_MASK 0x00000001
50 #define ISR_OFFSET 0x00000048
51 #define ISR_RESERVED_MASK 0xffffff60
52 #define ISR_CMDBUSY_MASK 0x00000080
53 #define ISR_READ_COMPLETE_MASK 0x00000010
54 #define ISR_SES_DONE_MASK 0x00000008
55 #define ISR_ERR_MASK 0x00000004
56 #define ISR_TXFIFOEMPTY_MASK 0x00000002
57 #define ISR_NOACK_MASK 0x00000001
59 #define CLKEN_OFFSET 0x0000004c
60 #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
61 #define CLKEN_M_SHIFT 4
62 #define CLKEN_N_SHIFT 1
63 #define CLKEN_CLKEN_MASK 0x00000001
65 #define FIFO_STATUS_OFFSET 0x00000054
66 #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
67 #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
69 #define HSTIM_OFFSET 0x00000058
70 #define HSTIM_HS_MODE_MASK 0x00008000
71 #define HSTIM_HS_HOLD_SHIFT 10
72 #define HSTIM_HS_HIGH_PHASE_SHIFT 5
73 #define HSTIM_HS_SETUP_SHIFT 0
75 #define PADCTL_OFFSET 0x0000005c
76 #define PADCTL_PAD_OUT_EN_MASK 0x00000004
78 #define RXFCR_OFFSET 0x00000068
79 #define RXFCR_NACK_EN_SHIFT 7
80 #define RXFCR_READ_COUNT_SHIFT 0
81 #define RXFIFORDOUT_OFFSET 0x0000006c
83 /* Locally used constants */
84 #define MAX_RX_FIFO_SIZE 64U /* bytes */
85 #define MAX_TX_FIFO_SIZE 64U /* bytes */
87 #define I2C_TIMEOUT 100000 /* usecs */
89 #define WAIT_INT_CHK 100 /* usecs */
90 #if I2C_TIMEOUT % WAIT_INT_CHK
91 #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
94 /* Operations that can be commanded to the controller */
102 enum bus_speed_index
{
108 /* Internal divider settings for standard mode, fast mode and fast mode plus */
109 struct bus_speed_cfg
{
110 uint8_t time_m
; /* Number of cycles for setup time */
111 uint8_t time_n
; /* Number of cycles for hold time */
112 uint8_t prescale
; /* Prescale divider */
113 uint8_t time_p
; /* Timing coefficient */
114 uint8_t no_div
; /* Disable clock divider */
115 uint8_t time_div
; /* Post-prescale divider */
118 static const struct bus_speed_cfg std_cfg_table
[] = {
119 [BCM_SPD_100K
] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
120 [BCM_SPD_400K
] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
121 [BCM_SPD_1MHZ
] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
124 struct bcm_kona_i2c_dev
{
127 const struct bus_speed_cfg
*std_cfg
;
130 /* Keep these two defines in sync */
131 #define DEF_SPD 100000
132 #define DEF_SPD_ENUM BCM_SPD_100K
134 #define DEF_DEVICE(num) \
135 {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
137 static struct bcm_kona_i2c_dev g_i2c_devs
[CONFIG_SYS_MAX_I2C_BUS
] = {
138 #ifdef CONFIG_SYS_I2C_BASE0
141 #ifdef CONFIG_SYS_I2C_BASE1
144 #ifdef CONFIG_SYS_I2C_BASE2
147 #ifdef CONFIG_SYS_I2C_BASE3
150 #ifdef CONFIG_SYS_I2C_BASE4
153 #ifdef CONFIG_SYS_I2C_BASE5
158 #define I2C_M_TEN 0x0010 /* ten bit address */
159 #define I2C_M_RD 0x0001 /* read data */
160 #define I2C_M_NOSTART 0x4000 /* no restart between msgs */
162 struct kona_i2c_msg
{
169 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev
*dev
,
170 enum bcm_kona_cmd_t cmd
)
172 debug("%s, %d\n", __func__
, cmd
);
175 case BCM_CMD_NOACTION
:
176 writel((CS_CMD_CMD_NO_ACTION
<< CS_CMD_SHIFT
) |
177 (CS_EN_CMD_ENABLE_BSC
<< CS_EN_SHIFT
),
178 dev
->base
+ CS_OFFSET
);
182 writel((CS_ACK_CMD_GEN_START
<< CS_ACK_SHIFT
) |
183 (CS_CMD_CMD_START_RESTART
<< CS_CMD_SHIFT
) |
184 (CS_EN_CMD_ENABLE_BSC
<< CS_EN_SHIFT
),
185 dev
->base
+ CS_OFFSET
);
188 case BCM_CMD_RESTART
:
189 writel((CS_ACK_CMD_GEN_RESTART
<< CS_ACK_SHIFT
) |
190 (CS_CMD_CMD_START_RESTART
<< CS_CMD_SHIFT
) |
191 (CS_EN_CMD_ENABLE_BSC
<< CS_EN_SHIFT
),
192 dev
->base
+ CS_OFFSET
);
196 writel((CS_CMD_CMD_STOP
<< CS_CMD_SHIFT
) |
197 (CS_EN_CMD_ENABLE_BSC
<< CS_EN_SHIFT
),
198 dev
->base
+ CS_OFFSET
);
202 printf("Unknown command %d\n", cmd
);
206 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev
*dev
)
208 writel(readl(dev
->base
+ CLKEN_OFFSET
) | CLKEN_CLKEN_MASK
,
209 dev
->base
+ CLKEN_OFFSET
);
212 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev
*dev
)
214 writel(readl(dev
->base
+ CLKEN_OFFSET
) & ~CLKEN_CLKEN_MASK
,
215 dev
->base
+ CLKEN_OFFSET
);
218 /* Wait until at least one of the mask bit(s) are set */
219 static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev
*dev
,
220 unsigned long time_left
,
226 status
= readl(dev
->base
+ ISR_OFFSET
);
228 if ((status
& ~ISR_RESERVED_MASK
) == 0) {
229 debug("Bogus I2C interrupt 0x%x\n", status
);
233 /* Must flush the TX FIFO when NAK detected */
234 if (status
& ISR_NOACK_MASK
)
235 writel(TXFCR_FIFO_FLUSH_MASK
| TXFCR_FIFO_EN_MASK
,
236 dev
->base
+ TXFCR_OFFSET
);
238 writel(status
& ~ISR_RESERVED_MASK
, dev
->base
+ ISR_OFFSET
);
241 /* We are done since one of the mask bits are set */
244 udelay(WAIT_INT_CHK
);
245 time_left
-= WAIT_INT_CHK
;
250 /* Send command to I2C bus */
251 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev
*dev
,
252 enum bcm_kona_cmd_t cmd
)
255 unsigned long time_left
= I2C_TIMEOUT
;
257 /* Send the command */
258 bcm_kona_i2c_send_cmd_to_ctrl(dev
, cmd
);
260 /* Wait for transaction to finish or timeout */
261 time_left
= wait_for_int_timeout(dev
, time_left
, IER_I2C_INT_EN_MASK
);
264 printf("controller timed out\n");
269 bcm_kona_i2c_send_cmd_to_ctrl(dev
, BCM_CMD_NOACTION
);
274 /* Read a single RX FIFO worth of data from the i2c bus */
275 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev
*dev
,
276 uint8_t *buf
, unsigned int len
,
277 unsigned int last_byte_nak
)
279 unsigned long time_left
= I2C_TIMEOUT
;
281 /* Start the RX FIFO */
282 writel((last_byte_nak
<< RXFCR_NACK_EN_SHIFT
) |
283 (len
<< RXFCR_READ_COUNT_SHIFT
), dev
->base
+ RXFCR_OFFSET
);
285 /* Wait for FIFO read to complete */
287 wait_for_int_timeout(dev
, time_left
, IER_READ_COMPLETE_INT_MASK
);
290 printf("RX FIFO time out\n");
294 /* Read data from FIFO */
295 for (; len
> 0; len
--, buf
++)
296 *buf
= readl(dev
->base
+ RXFIFORDOUT_OFFSET
);
301 /* Read any amount of data using the RX FIFO from the i2c bus */
302 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev
*dev
,
303 struct kona_i2c_msg
*msg
)
305 unsigned int bytes_to_read
= MAX_RX_FIFO_SIZE
;
306 unsigned int last_byte_nak
= 0;
307 unsigned int bytes_read
= 0;
310 uint8_t *tmp_buf
= msg
->buf
;
312 while (bytes_read
< msg
->len
) {
313 if (msg
->len
- bytes_read
<= MAX_RX_FIFO_SIZE
) {
314 last_byte_nak
= 1; /* NAK last byte of transfer */
315 bytes_to_read
= msg
->len
- bytes_read
;
318 rc
= bcm_kona_i2c_read_fifo_single(dev
, tmp_buf
, bytes_to_read
,
323 bytes_read
+= bytes_to_read
;
324 tmp_buf
+= bytes_to_read
;
330 /* Write a single byte of data to the i2c bus */
331 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev
*dev
, uint8_t data
,
332 unsigned int nak_expected
)
334 unsigned long time_left
= I2C_TIMEOUT
;
335 unsigned int nak_received
;
337 /* Clear pending session done interrupt */
338 writel(ISR_SES_DONE_MASK
, dev
->base
+ ISR_OFFSET
);
340 /* Send one byte of data */
341 writel(data
, dev
->base
+ DAT_OFFSET
);
343 time_left
= wait_for_int_timeout(dev
, time_left
, IER_I2C_INT_EN_MASK
);
346 debug("controller timed out\n");
350 nak_received
= readl(dev
->base
+ CS_OFFSET
) & CS_ACK_MASK
? 1 : 0;
352 if (nak_received
^ nak_expected
) {
353 debug("unexpected NAK/ACK\n");
360 /* Write a single TX FIFO worth of data to the i2c bus */
361 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev
*dev
,
362 uint8_t *buf
, unsigned int len
)
365 unsigned long time_left
= I2C_TIMEOUT
;
366 unsigned int fifo_status
;
368 /* Write data into FIFO */
369 for (k
= 0; k
< len
; k
++)
370 writel(buf
[k
], (dev
->base
+ DAT_OFFSET
));
372 /* Wait for FIFO to empty */
375 wait_for_int_timeout(dev
, time_left
,
376 (IER_FIFO_INT_EN_MASK
|
378 fifo_status
= readl(dev
->base
+ FIFO_STATUS_OFFSET
);
379 } while (time_left
&& !(fifo_status
& FIFO_STATUS_TXFIFO_EMPTY_MASK
));
381 /* Check if there was a NAK */
382 if (readl(dev
->base
+ CS_OFFSET
) & CS_ACK_MASK
) {
383 printf("unexpected NAK\n");
387 /* Check if a timeout occurred */
389 printf("completion timed out\n");
396 /* Write any amount of data using TX FIFO to the i2c bus */
397 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev
*dev
,
398 struct kona_i2c_msg
*msg
)
400 unsigned int bytes_to_write
= MAX_TX_FIFO_SIZE
;
401 unsigned int bytes_written
= 0;
404 uint8_t *tmp_buf
= msg
->buf
;
406 while (bytes_written
< msg
->len
) {
407 if (msg
->len
- bytes_written
<= MAX_TX_FIFO_SIZE
)
408 bytes_to_write
= msg
->len
- bytes_written
;
410 rc
= bcm_kona_i2c_write_fifo_single(dev
, tmp_buf
,
415 bytes_written
+= bytes_to_write
;
416 tmp_buf
+= bytes_to_write
;
422 /* Send i2c address */
423 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev
*dev
,
424 struct kona_i2c_msg
*msg
)
428 if (msg
->flags
& I2C_M_TEN
) {
429 /* First byte is 11110XX0 where XX is upper 2 bits */
430 addr
= 0xf0 | ((msg
->addr
& 0x300) >> 7);
431 if (bcm_kona_i2c_write_byte(dev
, addr
, 0) < 0)
434 /* Second byte is the remaining 8 bits */
435 addr
= msg
->addr
& 0xff;
436 if (bcm_kona_i2c_write_byte(dev
, addr
, 0) < 0)
439 if (msg
->flags
& I2C_M_RD
) {
440 /* For read, send restart command */
441 if (bcm_kona_send_i2c_cmd(dev
, BCM_CMD_RESTART
) < 0)
444 /* Then re-send the first byte with the read bit set */
445 addr
= 0xf0 | ((msg
->addr
& 0x300) >> 7) | 0x01;
446 if (bcm_kona_i2c_write_byte(dev
, addr
, 0) < 0)
450 addr
= msg
->addr
<< 1;
452 if (msg
->flags
& I2C_M_RD
)
455 if (bcm_kona_i2c_write_byte(dev
, addr
, 0) < 0)
462 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev
*dev
)
464 writel(readl(dev
->base
+ CLKEN_OFFSET
) & ~CLKEN_AUTOSENSE_OFF_MASK
,
465 dev
->base
+ CLKEN_OFFSET
);
468 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev
*dev
)
470 writel(readl(dev
->base
+ HSTIM_OFFSET
) & ~HSTIM_HS_MODE_MASK
,
471 dev
->base
+ HSTIM_OFFSET
);
473 writel((dev
->std_cfg
->prescale
<< TIM_PRESCALE_SHIFT
) |
474 (dev
->std_cfg
->time_p
<< TIM_P_SHIFT
) |
475 (dev
->std_cfg
->no_div
<< TIM_NO_DIV_SHIFT
) |
476 (dev
->std_cfg
->time_div
<< TIM_DIV_SHIFT
),
477 dev
->base
+ TIM_OFFSET
);
479 writel((dev
->std_cfg
->time_m
<< CLKEN_M_SHIFT
) |
480 (dev
->std_cfg
->time_n
<< CLKEN_N_SHIFT
) |
481 CLKEN_CLKEN_MASK
, dev
->base
+ CLKEN_OFFSET
);
484 /* Master transfer function */
485 static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev
*dev
,
486 struct kona_i2c_msg msgs
[], int num
)
488 struct kona_i2c_msg
*pmsg
;
492 /* Enable pad output */
493 writel(0, dev
->base
+ PADCTL_OFFSET
);
495 /* Enable internal clocks */
496 bcm_kona_i2c_enable_clock(dev
);
498 /* Send start command */
499 rc
= bcm_kona_send_i2c_cmd(dev
, BCM_CMD_START
);
501 printf("Start command failed rc = %d\n", rc
);
502 goto xfer_disable_pad
;
505 /* Loop through all messages */
506 for (i
= 0; i
< num
; i
++) {
509 /* Send restart for subsequent messages */
510 if ((i
!= 0) && ((pmsg
->flags
& I2C_M_NOSTART
) == 0)) {
511 rc
= bcm_kona_send_i2c_cmd(dev
, BCM_CMD_RESTART
);
513 printf("restart cmd failed rc = %d\n", rc
);
518 /* Send slave address */
519 if (!(pmsg
->flags
& I2C_M_NOSTART
)) {
520 rc
= bcm_kona_i2c_do_addr(dev
, pmsg
);
522 debug("NAK from addr %2.2x msg#%d rc = %d\n",
528 /* Perform data transfer */
529 if (pmsg
->flags
& I2C_M_RD
) {
530 rc
= bcm_kona_i2c_read_fifo(dev
, pmsg
);
532 printf("read failure\n");
536 rc
= bcm_kona_i2c_write_fifo(dev
, pmsg
);
538 printf("write failure");
547 /* Send a STOP command */
548 bcm_kona_send_i2c_cmd(dev
, BCM_CMD_STOP
);
551 /* Disable pad output */
552 writel(PADCTL_PAD_OUT_EN_MASK
, dev
->base
+ PADCTL_OFFSET
);
554 /* Stop internal clock */
555 bcm_kona_i2c_disable_clock(dev
);
560 static uint
bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev
*dev
,
565 dev
->std_cfg
= &std_cfg_table
[BCM_SPD_100K
];
568 dev
->std_cfg
= &std_cfg_table
[BCM_SPD_400K
];
571 dev
->std_cfg
= &std_cfg_table
[BCM_SPD_1MHZ
];
574 printf("%d hz bus speed not supported\n", speed
);
581 static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev
*dev
)
583 /* Parse bus speed */
584 bcm_kona_i2c_assign_bus_speed(dev
, dev
->speed
);
586 /* Enable internal clocks */
587 bcm_kona_i2c_enable_clock(dev
);
589 /* Configure internal dividers */
590 bcm_kona_i2c_config_timing(dev
);
592 /* Disable timeout */
593 writel(0, dev
->base
+ TOUT_OFFSET
);
595 /* Enable autosense */
596 bcm_kona_i2c_enable_autosense(dev
);
599 writel(TXFCR_FIFO_FLUSH_MASK
| TXFCR_FIFO_EN_MASK
,
600 dev
->base
+ TXFCR_OFFSET
);
602 /* Mask all interrupts */
603 writel(0, dev
->base
+ IER_OFFSET
);
605 /* Clear all pending interrupts */
606 writel(ISR_CMDBUSY_MASK
|
607 ISR_READ_COMPLETE_MASK
|
610 ISR_TXFIFOEMPTY_MASK
| ISR_NOACK_MASK
, dev
->base
+ ISR_OFFSET
);
612 /* Enable the controller but leave it idle */
613 bcm_kona_i2c_send_cmd_to_ctrl(dev
, BCM_CMD_NOACTION
);
615 /* Disable pad output */
616 writel(PADCTL_PAD_OUT_EN_MASK
, dev
->base
+ PADCTL_OFFSET
);
622 struct bcm_kona_i2c_dev
*kona_get_dev(struct i2c_adapter
*adap
)
624 return &g_i2c_devs
[adap
->hwadapnr
];
627 static void kona_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
629 struct bcm_kona_i2c_dev
*dev
= kona_get_dev(adap
);
631 if (clk_bsc_enable(dev
->base
))
634 bcm_kona_i2c_init(dev
);
637 static int kona_i2c_read(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
638 int alen
, uchar
*buffer
, int len
)
640 /* msg[0] writes the addr, msg[1] reads the data */
641 struct kona_i2c_msg msg
[2];
642 unsigned char msgbuf0
[64];
643 struct bcm_kona_i2c_dev
*dev
= kona_get_dev(adap
);
648 msg
[0].buf
= msgbuf0
; /* msgbuf0 contains incrementing reg addr */
651 msg
[1].flags
= I2C_M_RD
;
652 /* msg[1].buf dest ptr increments each read */
654 msgbuf0
[0] = (unsigned char)addr
;
657 if (bcm_kona_i2c_xfer(dev
, msg
, 2) < 0) {
658 /* Sending 2 i2c messages */
659 kona_i2c_init(adap
, adap
->speed
, adap
->slaveaddr
);
660 debug("I2C read: I/O error\n");
666 static int kona_i2c_write(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
667 int alen
, uchar
*buffer
, int len
)
669 struct kona_i2c_msg msg
[1];
670 unsigned char msgbuf0
[64];
672 struct bcm_kona_i2c_dev
*dev
= kona_get_dev(adap
);
676 msg
[0].len
= 2; /* addr byte plus data */
677 msg
[0].buf
= msgbuf0
;
679 for (i
= 0; i
< len
; i
++) {
681 msgbuf0
[1] = buffer
[i
];
682 if (bcm_kona_i2c_xfer(dev
, msg
, 1) < 0) {
683 kona_i2c_init(adap
, adap
->speed
, adap
->slaveaddr
);
684 debug("I2C write: I/O error\n");
691 static int kona_i2c_probe(struct i2c_adapter
*adap
, uchar chip
)
696 * read addr 0x0 of the given chip.
698 return kona_i2c_read(adap
, chip
, 0x0, 1, &tmp
, 1);
701 static uint
kona_i2c_set_bus_speed(struct i2c_adapter
*adap
, uint speed
)
703 struct bcm_kona_i2c_dev
*dev
= kona_get_dev(adap
);
704 return bcm_kona_i2c_assign_bus_speed(dev
, speed
);
708 * Register kona i2c adapters. Keep the order below so
709 * that the bus number matches the adapter number.
711 #define DEF_ADAPTER(num) \
712 U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
713 kona_i2c_read, kona_i2c_write, \
714 kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
716 #ifdef CONFIG_SYS_I2C_BASE0
719 #ifdef CONFIG_SYS_I2C_BASE1
722 #ifdef CONFIG_SYS_I2C_BASE2
725 #ifdef CONFIG_SYS_I2C_BASE3
728 #ifdef CONFIG_SYS_I2C_BASE4
731 #ifdef CONFIG_SYS_I2C_BASE5