2 * LPC32xx I2C interface driver
4 * (C) Copyright 2014-2015 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/errno.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/i2c.h>
20 * Provide default speed and slave if target did not
23 #if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
24 #define CONFIG_SYS_I2C_LPC32XX_SPEED 350000
27 #if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
28 #define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
31 /* TX register fields */
32 #define LPC32XX_I2C_TX_START 0x00000100
33 #define LPC32XX_I2C_TX_STOP 0x00000200
35 /* Control register values */
36 #define LPC32XX_I2C_SOFT_RESET 0x00000100
38 /* Status register values */
39 #define LPC32XX_I2C_STAT_TFF 0x00000400
40 #define LPC32XX_I2C_STAT_RFE 0x00000200
41 #define LPC32XX_I2C_STAT_DRMI 0x00000008
42 #define LPC32XX_I2C_STAT_NAI 0x00000004
43 #define LPC32XX_I2C_STAT_TDI 0x00000001
46 static struct lpc32xx_i2c_base
*lpc32xx_i2c
[] = {
47 (struct lpc32xx_i2c_base
*)I2C1_BASE
,
48 (struct lpc32xx_i2c_base
*)I2C2_BASE
,
49 (struct lpc32xx_i2c_base
*)(USB_BASE
+ 0x300)
53 /* Set I2C bus speed */
54 static unsigned int __i2c_set_bus_speed(struct lpc32xx_i2c_base
*base
,
55 unsigned int speed
, unsigned int chip
)
62 /* OTG I2C clock source and CLK registers are different */
64 half_period
= (get_periph_clk_rate() / speed
) / 2;
65 if (half_period
> 0xFF)
68 half_period
= (get_hclk_clk_rate() / speed
) / 2;
69 if (half_period
> 0x3FF)
73 writel(half_period
, &base
->clk_hi
);
74 writel(half_period
, &base
->clk_lo
);
78 /* I2C init called by cmd_i2c when doing 'i2c reset'. */
79 static void __i2c_init(struct lpc32xx_i2c_base
*base
,
80 int requested_speed
, int slaveadd
, unsigned int chip
)
82 /* soft reset (auto-clears) */
83 writel(LPC32XX_I2C_SOFT_RESET
, &base
->ctrl
);
84 /* set HI and LO periods for half of the default speed */
85 __i2c_set_bus_speed(base
, requested_speed
, chip
);
88 /* I2C probe called by cmd_i2c when doing 'i2c probe'. */
89 static int __i2c_probe_chip(struct lpc32xx_i2c_base
*base
, u8 dev
)
93 /* Soft-reset the controller */
94 writel(LPC32XX_I2C_SOFT_RESET
, &base
->ctrl
);
95 while (readl(&base
->ctrl
) & LPC32XX_I2C_SOFT_RESET
)
97 /* Addre slave for write with start before and stop after */
98 writel((dev
<<1) | LPC32XX_I2C_TX_START
| LPC32XX_I2C_TX_STOP
,
100 /* wait for end of transation */
101 while (!((stat
= readl(&base
->stat
)) & LPC32XX_I2C_STAT_TDI
))
103 /* was there no acknowledge? */
104 return (stat
& LPC32XX_I2C_STAT_NAI
) ? -1 : 0;
108 * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
109 * Begin write, send address byte(s), begin read, receive data bytes, end.
111 static int __i2c_read(struct lpc32xx_i2c_base
*base
, u8 dev
, uint addr
,
112 int alen
, u8
*data
, int length
)
116 /* Soft-reset the controller */
117 writel(LPC32XX_I2C_SOFT_RESET
, &base
->ctrl
);
118 while (readl(&base
->ctrl
) & LPC32XX_I2C_SOFT_RESET
)
120 /* do we need to write an address at all? */
122 /* Address slave in write mode */
123 writel((dev
<<1) | LPC32XX_I2C_TX_START
, &base
->tx
);
124 /* write address bytes */
126 /* compute address byte + stop for the last one */
127 int a
= (addr
>> (8 * alen
)) & 0xff;
129 a
|= LPC32XX_I2C_TX_STOP
;
130 /* Send address byte */
131 writel(a
, &base
->tx
);
133 /* wait for end of transation */
134 while (!((stat
= readl(&base
->stat
)) & LPC32XX_I2C_STAT_TDI
))
136 /* clear end-of-transaction flag */
137 writel(1, &base
->stat
);
139 /* do we have to read data at all? */
141 /* Address slave in read mode */
142 writel(1 | (dev
<<1) | LPC32XX_I2C_TX_START
, &base
->tx
);
145 while (length
| wlen
) {
146 /* read status for TFF and RFE */
147 stat
= readl(&base
->stat
);
148 /* must we, can we write a trigger byte? */
150 & (!(stat
& LPC32XX_I2C_STAT_TFF
))) {
152 /* write trigger byte + stop if last */
154 LPC32XX_I2C_TX_STOP
, &base
->tx
);
156 /* must we, can we read a data byte? */
158 & (!(stat
& LPC32XX_I2C_STAT_RFE
))) {
161 *(data
++) = readl(&base
->rx
);
164 /* wait for end of transation */
165 while (!((stat
= readl(&base
->stat
)) & LPC32XX_I2C_STAT_TDI
))
167 /* clear end-of-transaction flag */
168 writel(1, &base
->stat
);
175 * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
176 * Begin write, send address byte(s), send data bytes, end.
178 static int __i2c_write(struct lpc32xx_i2c_base
*base
, u8 dev
, uint addr
,
179 int alen
, u8
*data
, int length
)
183 /* Soft-reset the controller */
184 writel(LPC32XX_I2C_SOFT_RESET
, &base
->ctrl
);
185 while (readl(&base
->ctrl
) & LPC32XX_I2C_SOFT_RESET
)
187 /* do we need to write anything at all? */
189 /* Address slave in write mode */
190 writel((dev
<<1) | LPC32XX_I2C_TX_START
, &base
->tx
);
193 /* write address bytes */
195 /* wait for transmit fifo not full */
196 stat
= readl(&base
->stat
);
197 if (!(stat
& LPC32XX_I2C_STAT_TFF
)) {
199 int a
= (addr
>> (8 * alen
)) & 0xff;
200 if (!(alen
| length
))
201 a
|= LPC32XX_I2C_TX_STOP
;
202 /* Send address byte */
203 writel(a
, &base
->tx
);
207 /* wait for transmit fifo not full */
208 stat
= readl(&base
->stat
);
209 if (!(stat
& LPC32XX_I2C_STAT_TFF
)) {
210 /* compute data byte, add stop if length==0 */
214 d
|= LPC32XX_I2C_TX_STOP
;
216 writel(d
, &base
->tx
);
219 /* wait for end of transation */
220 while (!((stat
= readl(&base
->stat
)) & LPC32XX_I2C_STAT_TDI
))
222 /* clear end-of-transaction flag */
223 writel(1, &base
->stat
);
227 #ifndef CONFIG_DM_I2C
228 static void lpc32xx_i2c_init(struct i2c_adapter
*adap
,
229 int requested_speed
, int slaveadd
)
231 __i2c_init(lpc32xx_i2c
[adap
->hwadapnr
], requested_speed
, slaveadd
,
235 static int lpc32xx_i2c_probe_chip(struct i2c_adapter
*adap
, u8 dev
)
237 return __i2c_probe_chip(lpc32xx_i2c
[adap
->hwadapnr
], dev
);
240 static int lpc32xx_i2c_read(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
241 int alen
, u8
*data
, int length
)
243 return __i2c_read(lpc32xx_i2c
[adap
->hwadapnr
], dev
, addr
,
247 static int lpc32xx_i2c_write(struct i2c_adapter
*adap
, u8 dev
, uint addr
,
248 int alen
, u8
*data
, int length
)
250 return __i2c_write(lpc32xx_i2c
[adap
->hwadapnr
], dev
, addr
,
254 static unsigned int lpc32xx_i2c_set_bus_speed(struct i2c_adapter
*adap
,
257 return __i2c_set_bus_speed(lpc32xx_i2c
[adap
->hwadapnr
], speed
,
261 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_0
, lpc32xx_i2c_init
, lpc32xx_i2c_probe_chip
,
262 lpc32xx_i2c_read
, lpc32xx_i2c_write
,
263 lpc32xx_i2c_set_bus_speed
,
264 CONFIG_SYS_I2C_LPC32XX_SPEED
,
265 CONFIG_SYS_I2C_LPC32XX_SLAVE
,
268 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_1
, lpc32xx_i2c_init
, lpc32xx_i2c_probe_chip
,
269 lpc32xx_i2c_read
, lpc32xx_i2c_write
,
270 lpc32xx_i2c_set_bus_speed
,
271 CONFIG_SYS_I2C_LPC32XX_SPEED
,
272 CONFIG_SYS_I2C_LPC32XX_SLAVE
,
275 U_BOOT_I2C_ADAP_COMPLETE(lpc32xx_2
, lpc32xx_i2c_init
, NULL
,
276 lpc32xx_i2c_read
, lpc32xx_i2c_write
,
277 lpc32xx_i2c_set_bus_speed
,
281 #else /* CONFIG_DM_I2C */
282 static int lpc32xx_i2c_probe(struct udevice
*bus
)
284 struct lpc32xx_i2c_dev
*dev
= dev_get_platdata(bus
);
285 bus
->seq
= dev
->index
;
287 __i2c_init(dev
->base
, dev
->speed
, 0, dev
->index
);
291 static int lpc32xx_i2c_probe_chip(struct udevice
*bus
, u32 chip_addr
,
294 struct lpc32xx_i2c_dev
*dev
= dev_get_platdata(bus
);
295 return __i2c_probe_chip(dev
->base
, chip_addr
);
298 static int lpc32xx_i2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
,
301 struct lpc32xx_i2c_dev
*dev
= dev_get_platdata(bus
);
302 struct i2c_msg
*dmsg
, *omsg
, dummy
;
303 uint i
= 0, address
= 0;
305 memset(&dummy
, 0, sizeof(struct i2c_msg
));
307 /* We expect either two messages (one with an offset and one with the
308 * actual data) or one message (just data)
310 if (nmsgs
> 2 || nmsgs
== 0) {
311 debug("%s: Only one or two messages are supported.", __func__
);
315 omsg
= nmsgs
== 1 ? &dummy
: msg
;
316 dmsg
= nmsgs
== 1 ? msg
: msg
+ 1;
318 /* the address is expected to be a uint, not a array. */
319 address
= omsg
->buf
[0];
320 for (i
= 1; i
< omsg
->len
; i
++)
321 address
= (address
<< 8) + omsg
->buf
[i
];
323 if (dmsg
->flags
& I2C_M_RD
)
324 return __i2c_read(dev
->base
, dmsg
->addr
, address
,
325 omsg
->len
, dmsg
->buf
, dmsg
->len
);
327 return __i2c_write(dev
->base
, dmsg
->addr
, address
,
328 omsg
->len
, dmsg
->buf
, dmsg
->len
);
331 static int lpc32xx_i2c_set_bus_speed(struct udevice
*bus
, unsigned int speed
)
333 struct lpc32xx_i2c_dev
*dev
= dev_get_platdata(bus
);
334 return __i2c_set_bus_speed(dev
->base
, speed
, dev
->index
);
337 static int lpc32xx_i2c_reset(struct udevice
*bus
)
339 struct lpc32xx_i2c_dev
*dev
= dev_get_platdata(bus
);
341 __i2c_init(dev
->base
, dev
->speed
, 0, dev
->index
);
345 static const struct dm_i2c_ops lpc32xx_i2c_ops
= {
346 .xfer
= lpc32xx_i2c_xfer
,
347 .probe_chip
= lpc32xx_i2c_probe_chip
,
348 .deblock
= lpc32xx_i2c_reset
,
349 .set_bus_speed
= lpc32xx_i2c_set_bus_speed
,
352 U_BOOT_DRIVER(i2c_lpc32xx
) = {
354 .name
= "i2c_lpc32xx",
355 .probe
= lpc32xx_i2c_probe
,
356 .ops
= &lpc32xx_i2c_ops
,
358 #endif /* CONFIG_DM_I2C */