2 * i2c driver for Freescale i.MX series
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
7 * Based on i2c-imx.c from linux kernel:
8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
10 * Copyright (C) 2007 RightHand Technologies, Inc.
11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
14 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/clock.h>
19 #include <asm/arch/imx-regs.h>
20 #include <asm/errno.h>
33 #define I2CR_IEN (1 << 7)
34 #define I2CR_IIEN (1 << 6)
35 #define I2CR_MSTA (1 << 5)
36 #define I2CR_MTX (1 << 4)
37 #define I2CR_TX_NO_AK (1 << 3)
38 #define I2CR_RSTA (1 << 2)
40 #define I2SR_ICF (1 << 7)
41 #define I2SR_IBB (1 << 5)
42 #define I2SR_IAL (1 << 4)
43 #define I2SR_IIF (1 << 1)
44 #define I2SR_RX_NO_AK (1 << 0)
46 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
47 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
50 static u16 i2c_clk_div
[50][2] = {
51 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
52 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
53 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
54 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
55 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
56 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
57 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
58 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
59 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
60 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
61 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
62 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
63 { 3072, 0x1E }, { 3840, 0x1F }
67 * Calculate and set proper clock divider
69 static uint8_t i2c_imx_get_clk(unsigned int rate
)
71 unsigned int i2c_clk_rate
;
75 #if defined(CONFIG_MX31)
76 struct clock_control_regs
*sc_regs
=
77 (struct clock_control_regs
*)CCM_BASE
;
79 /* start the required I2C clock */
80 writel(readl(&sc_regs
->cgr0
) | (3 << CONFIG_SYS_I2C_CLK_OFFSET
),
84 /* Divider value calculation */
85 i2c_clk_rate
= mxc_get_clock(MXC_I2C_CLK
);
86 div
= (i2c_clk_rate
+ rate
- 1) / rate
;
87 if (div
< i2c_clk_div
[0][0])
89 else if (div
> i2c_clk_div
[ARRAY_SIZE(i2c_clk_div
) - 1][0])
90 clk_div
= ARRAY_SIZE(i2c_clk_div
) - 1;
92 for (clk_div
= 0; i2c_clk_div
[clk_div
][0] < div
; clk_div
++)
95 /* Store divider value */
102 static int bus_i2c_set_bus_speed(void *base
, int speed
)
104 struct mxc_i2c_regs
*i2c_regs
= (struct mxc_i2c_regs
*)base
;
105 u8 clk_idx
= i2c_imx_get_clk(speed
);
106 u8 idx
= i2c_clk_div
[clk_idx
][1];
108 /* Store divider value */
109 writeb(idx
, &i2c_regs
->ifdr
);
112 writeb(0, &i2c_regs
->i2cr
);
113 writeb(0, &i2c_regs
->i2sr
);
120 static unsigned int bus_i2c_get_bus_speed(void *base
)
122 struct mxc_i2c_regs
*i2c_regs
= (struct mxc_i2c_regs
*)base
;
123 u8 clk_idx
= readb(&i2c_regs
->ifdr
);
126 for (clk_div
= 0; i2c_clk_div
[clk_div
][1] != clk_idx
; clk_div
++)
129 return mxc_get_clock(MXC_I2C_CLK
) / i2c_clk_div
[clk_div
][0];
132 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
133 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
134 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
136 static int wait_for_sr_state(struct mxc_i2c_regs
*i2c_regs
, unsigned state
)
140 ulong start_time
= get_timer(0);
142 sr
= readb(&i2c_regs
->i2sr
);
144 writeb(sr
& ~I2SR_IAL
, &i2c_regs
->i2sr
);
145 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
146 __func__
, sr
, readb(&i2c_regs
->i2cr
), state
);
149 if ((sr
& (state
>> 8)) == (unsigned char)state
)
152 elapsed
= get_timer(start_time
);
153 if (elapsed
> (CONFIG_SYS_HZ
/ 10)) /* .1 seconds */
156 printf("%s: failed sr=%x cr=%x state=%x\n", __func__
,
157 sr
, readb(&i2c_regs
->i2cr
), state
);
161 static int tx_byte(struct mxc_i2c_regs
*i2c_regs
, u8 byte
)
165 writeb(0, &i2c_regs
->i2sr
);
166 writeb(byte
, &i2c_regs
->i2dr
);
167 ret
= wait_for_sr_state(i2c_regs
, ST_IIF
);
170 if (ret
& I2SR_RX_NO_AK
)
176 * Stop I2C transaction
178 static void i2c_imx_stop(struct mxc_i2c_regs
*i2c_regs
)
181 unsigned int temp
= readb(&i2c_regs
->i2cr
);
183 temp
&= ~(I2CR_MSTA
| I2CR_MTX
);
184 writeb(temp
, &i2c_regs
->i2cr
);
185 ret
= wait_for_sr_state(i2c_regs
, ST_BUS_IDLE
);
187 printf("%s:trigger stop failed\n", __func__
);
191 * Send start signal, chip address and
192 * write register address
194 static int i2c_init_transfer_(struct mxc_i2c_regs
*i2c_regs
,
195 uchar chip
, uint addr
, int alen
)
200 /* Enable I2C controller */
201 if (!(readb(&i2c_regs
->i2cr
) & I2CR_IEN
)) {
202 writeb(I2CR_IEN
, &i2c_regs
->i2cr
);
203 /* Wait for controller to be stable */
206 if (readb(&i2c_regs
->iadr
) == (chip
<< 1))
207 writeb((chip
<< 1) ^ 2, &i2c_regs
->iadr
);
208 writeb(0, &i2c_regs
->i2sr
);
209 ret
= wait_for_sr_state(i2c_regs
, ST_BUS_IDLE
);
213 /* Start I2C transaction */
214 temp
= readb(&i2c_regs
->i2cr
);
216 writeb(temp
, &i2c_regs
->i2cr
);
218 ret
= wait_for_sr_state(i2c_regs
, ST_BUS_BUSY
);
222 temp
|= I2CR_MTX
| I2CR_TX_NO_AK
;
223 writeb(temp
, &i2c_regs
->i2cr
);
225 /* write slave address */
226 ret
= tx_byte(i2c_regs
, chip
<< 1);
231 ret
= tx_byte(i2c_regs
, (addr
>> (alen
* 8)) & 0xff);
238 static int i2c_idle_bus(void *base
);
240 static int i2c_init_transfer(struct mxc_i2c_regs
*i2c_regs
,
241 uchar chip
, uint addr
, int alen
)
245 for (retry
= 0; retry
< 3; retry
++) {
246 ret
= i2c_init_transfer_(i2c_regs
, chip
, addr
, alen
);
249 i2c_imx_stop(i2c_regs
);
253 printf("%s: failed for chip 0x%x retry=%d\n", __func__
, chip
,
255 if (ret
!= -ERESTART
)
256 writeb(0, &i2c_regs
->i2cr
); /* Disable controller */
258 if (i2c_idle_bus(i2c_regs
) < 0)
261 printf("%s: give up i2c_regs=%p\n", __func__
, i2c_regs
);
266 * Read data from I2C device
268 int bus_i2c_read(void *base
, uchar chip
, uint addr
, int alen
, uchar
*buf
,
274 struct mxc_i2c_regs
*i2c_regs
= (struct mxc_i2c_regs
*)base
;
276 ret
= i2c_init_transfer(i2c_regs
, chip
, addr
, alen
);
280 temp
= readb(&i2c_regs
->i2cr
);
282 writeb(temp
, &i2c_regs
->i2cr
);
284 ret
= tx_byte(i2c_regs
, (chip
<< 1) | 1);
286 i2c_imx_stop(i2c_regs
);
290 /* setup bus to read data */
291 temp
= readb(&i2c_regs
->i2cr
);
292 temp
&= ~(I2CR_MTX
| I2CR_TX_NO_AK
);
294 temp
|= I2CR_TX_NO_AK
;
295 writeb(temp
, &i2c_regs
->i2cr
);
296 writeb(0, &i2c_regs
->i2sr
);
297 readb(&i2c_regs
->i2dr
); /* dummy read to clear ICF */
300 for (i
= 0; i
< len
; i
++) {
301 ret
= wait_for_sr_state(i2c_regs
, ST_IIF
);
303 i2c_imx_stop(i2c_regs
);
308 * It must generate STOP before read I2DR to prevent
309 * controller from generating another clock cycle
311 if (i
== (len
- 1)) {
312 i2c_imx_stop(i2c_regs
);
313 } else if (i
== (len
- 2)) {
314 temp
= readb(&i2c_regs
->i2cr
);
315 temp
|= I2CR_TX_NO_AK
;
316 writeb(temp
, &i2c_regs
->i2cr
);
318 writeb(0, &i2c_regs
->i2sr
);
319 buf
[i
] = readb(&i2c_regs
->i2dr
);
321 i2c_imx_stop(i2c_regs
);
326 * Write data to I2C device
328 int bus_i2c_write(void *base
, uchar chip
, uint addr
, int alen
,
329 const uchar
*buf
, int len
)
333 struct mxc_i2c_regs
*i2c_regs
= (struct mxc_i2c_regs
*)base
;
335 ret
= i2c_init_transfer(i2c_regs
, chip
, addr
, alen
);
339 for (i
= 0; i
< len
; i
++) {
340 ret
= tx_byte(i2c_regs
, buf
[i
]);
344 i2c_imx_stop(i2c_regs
);
351 int (*idle_bus_fn
)(void *p
);
355 unsigned curr_i2c_bus
;
356 struct i2c_parms i2c_data
[3];
360 * For SPL boot some boards need i2c before SDRAM is initialized so force
361 * variables to live in SRAM
363 static struct sram_data
__attribute__((section(".data"))) srdata
;
367 #ifdef CONFIG_SYS_I2C_BASE
368 #ifdef CONFIG_I2C_MULTI_BUS
369 void *ret
= srdata
.i2c_data
[srdata
.curr_i2c_bus
].base
;
373 return (void *)CONFIG_SYS_I2C_BASE
;
374 #elif defined(CONFIG_I2C_MULTI_BUS)
375 return srdata
.i2c_data
[srdata
.curr_i2c_bus
].base
;
377 return srdata
.i2c_data
[0].base
;
381 static struct i2c_parms
*i2c_get_parms(void *base
)
384 struct i2c_parms
*p
= srdata
.i2c_data
;
385 while (i
< ARRAY_SIZE(srdata
.i2c_data
)) {
391 printf("Invalid I2C base: %p\n", base
);
395 static int i2c_idle_bus(void *base
)
397 struct i2c_parms
*p
= i2c_get_parms(base
);
398 if (p
&& p
->idle_bus_fn
)
399 return p
->idle_bus_fn(p
->idle_bus_data
);
403 #ifdef CONFIG_I2C_MULTI_BUS
404 unsigned int i2c_get_bus_num(void)
406 return srdata
.curr_i2c_bus
;
409 int i2c_set_bus_num(unsigned bus_idx
)
411 if (bus_idx
>= ARRAY_SIZE(srdata
.i2c_data
))
413 if (!srdata
.i2c_data
[bus_idx
].base
)
415 srdata
.curr_i2c_bus
= bus_idx
;
420 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buf
, int len
)
422 return bus_i2c_read(get_base(), chip
, addr
, alen
, buf
, len
);
425 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buf
, int len
)
427 return bus_i2c_write(get_base(), chip
, addr
, alen
, buf
, len
);
431 * Test if a chip at a given address responds (probe the chip)
433 int i2c_probe(uchar chip
)
435 return bus_i2c_write(get_base(), chip
, 0, 0, NULL
, 0);
438 void bus_i2c_init(void *base
, int speed
, int unused
,
439 int (*idle_bus_fn
)(void *p
), void *idle_bus_data
)
442 struct i2c_parms
*p
= srdata
.i2c_data
;
446 if (!p
->base
|| (p
->base
== base
)) {
449 p
->idle_bus_fn
= idle_bus_fn
;
450 p
->idle_bus_data
= idle_bus_data
;
456 if (i
>= ARRAY_SIZE(srdata
.i2c_data
))
459 bus_i2c_set_bus_speed(base
, speed
);
465 void i2c_init(int speed
, int unused
)
467 bus_i2c_init(get_base(), speed
, unused
, NULL
, NULL
);
473 int i2c_set_bus_speed(unsigned int speed
)
475 return bus_i2c_set_bus_speed(get_base(), speed
);
481 unsigned int i2c_get_bus_speed(void)
483 return bus_i2c_get_bus_speed(get_base());