drivers/i2c/mxc_i2c.c

   1 /*
   2  * i2c driver for Freescale i.MX series
   3  *
   4  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
   5  * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  *
   7  * Based on i2c-imx.c from linux kernel:
   8  *  Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
   9  *  Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  10  *  Copyright (C) 2007 RightHand Technologies, Inc.
  11  *  Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  12  *
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #include <common.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/imx-regs.h>
  20 #include <asm/errno.h>
  21 #include <asm/io.h>
  22 #include <i2c.h>
  23 #include <watchdog.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 #ifdef I2C_QUIRK_REG
  28 struct mxc_i2c_regs {
  29         uint8_t         iadr;
  30         uint8_t         ifdr;
  31         uint8_t         i2cr;
  32         uint8_t         i2sr;
  33         uint8_t         i2dr;
  34 };
  35 #else
  36 struct mxc_i2c_regs {
  37         uint32_t        iadr;
  38         uint32_t        ifdr;
  39         uint32_t        i2cr;
  40         uint32_t        i2sr;
  41         uint32_t        i2dr;
  42 };
  43 #endif
  44
  45 #define I2CR_IIEN       (1 << 6)
  46 #define I2CR_MSTA       (1 << 5)
  47 #define I2CR_MTX        (1 << 4)
  48 #define I2CR_TX_NO_AK   (1 << 3)
  49 #define I2CR_RSTA       (1 << 2)
  50
  51 #define I2SR_ICF        (1 << 7)
  52 #define I2SR_IBB        (1 << 5)
  53 #define I2SR_IAL        (1 << 4)
  54 #define I2SR_IIF        (1 << 1)
  55 #define I2SR_RX_NO_AK   (1 << 0)
  56
  57 #ifdef I2C_QUIRK_REG
  58 #define I2CR_IEN        (0 << 7)
  59 #define I2CR_IDIS       (1 << 7)
  60 #define I2SR_IIF_CLEAR  (1 << 1)
  61 #else
  62 #define I2CR_IEN        (1 << 7)
  63 #define I2CR_IDIS       (0 << 7)
  64 #define I2SR_IIF_CLEAR  (0 << 1)
  65 #endif
  66
  67 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE)
  68 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
  69 #endif
  70
  71 #ifdef I2C_QUIRK_REG
  72 static u16 i2c_clk_div[60][2] = {
  73         { 20,   0x00 }, { 22,   0x01 }, { 24,   0x02 }, { 26,   0x03 },
  74         { 28,   0x04 }, { 30,   0x05 }, { 32,   0x09 }, { 34,   0x06 },
  75         { 36,   0x0A }, { 40,   0x07 }, { 44,   0x0C }, { 48,   0x0D },
  76         { 52,   0x43 }, { 56,   0x0E }, { 60,   0x45 }, { 64,   0x12 },
  77         { 68,   0x0F }, { 72,   0x13 }, { 80,   0x14 }, { 88,   0x15 },
  78         { 96,   0x19 }, { 104,  0x16 }, { 112,  0x1A }, { 128,  0x17 },
  79         { 136,  0x4F }, { 144,  0x1C }, { 160,  0x1D }, { 176,  0x55 },
  80         { 192,  0x1E }, { 208,  0x56 }, { 224,  0x22 }, { 228,  0x24 },
  81         { 240,  0x1F }, { 256,  0x23 }, { 288,  0x5C }, { 320,  0x25 },
  82         { 384,  0x26 }, { 448,  0x2A }, { 480,  0x27 }, { 512,  0x2B },
  83         { 576,  0x2C }, { 640,  0x2D }, { 768,  0x31 }, { 896,  0x32 },
  84         { 960,  0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  85         { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  86         { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  87         { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  88 };
  89 #else
  90 static u16 i2c_clk_div[50][2] = {
  91         { 22,   0x20 }, { 24,   0x21 }, { 26,   0x22 }, { 28,   0x23 },
  92         { 30,   0x00 }, { 32,   0x24 }, { 36,   0x25 }, { 40,   0x26 },
  93         { 42,   0x03 }, { 44,   0x27 }, { 48,   0x28 }, { 52,   0x05 },
  94         { 56,   0x29 }, { 60,   0x06 }, { 64,   0x2A }, { 72,   0x2B },
  95         { 80,   0x2C }, { 88,   0x09 }, { 96,   0x2D }, { 104,  0x0A },
  96         { 112,  0x2E }, { 128,  0x2F }, { 144,  0x0C }, { 160,  0x30 },
  97         { 192,  0x31 }, { 224,  0x32 }, { 240,  0x0F }, { 256,  0x33 },
  98         { 288,  0x10 }, { 320,  0x34 }, { 384,  0x35 }, { 448,  0x36 },
  99         { 480,  0x13 }, { 512,  0x37 }, { 576,  0x14 }, { 640,  0x38 },
 100         { 768,  0x39 }, { 896,  0x3A }, { 960,  0x17 }, { 1024, 0x3B },
 101         { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
 102         { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
 103         { 3072, 0x1E }, { 3840, 0x1F }
 104 };
 105 #endif
 106
 107
 108 #ifndef CONFIG_SYS_MXC_I2C1_SPEED
 109 #define CONFIG_SYS_MXC_I2C1_SPEED 100000
 110 #endif
 111 #ifndef CONFIG_SYS_MXC_I2C2_SPEED
 112 #define CONFIG_SYS_MXC_I2C2_SPEED 100000
 113 #endif
 114 #ifndef CONFIG_SYS_MXC_I2C3_SPEED
 115 #define CONFIG_SYS_MXC_I2C3_SPEED 100000
 116 #endif
 117 #ifndef CONFIG_SYS_MXC_I2C4_SPEED
 118 #define CONFIG_SYS_MXC_I2C4_SPEED 100000
 119 #endif
 120
 121 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
 122 #define CONFIG_SYS_MXC_I2C1_SLAVE 0
 123 #endif
 124 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
 125 #define CONFIG_SYS_MXC_I2C2_SLAVE 0
 126 #endif
 127 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
 128 #define CONFIG_SYS_MXC_I2C3_SLAVE 0
 129 #endif
 130 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
 131 #define CONFIG_SYS_MXC_I2C4_SLAVE 0
 132 #endif
 133
 134
 135 /*
 136  * Calculate and set proper clock divider
 137  */
 138 static uint8_t i2c_imx_get_clk(unsigned int rate)
 139 {
 140         unsigned int i2c_clk_rate;
 141         unsigned int div;
 142         u8 clk_div;
 143
 144 #if defined(CONFIG_MX31)
 145         struct clock_control_regs *sc_regs =
 146                 (struct clock_control_regs *)CCM_BASE;
 147
 148         /* start the required I2C clock */
 149         writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
 150                 &sc_regs->cgr0);
 151 #endif
 152
 153         /* Divider value calculation */
 154         i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
 155         div = (i2c_clk_rate + rate - 1) / rate;
 156         if (div < i2c_clk_div[0][0])
 157                 clk_div = 0;
 158         else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
 159                 clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
 160         else
 161                 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
 162                         ;
 163
 164         /* Store divider value */
 165         return clk_div;
 166 }
 167
 168 /*
 169  * Set I2C Bus speed
 170  */
 171 static int bus_i2c_set_bus_speed(void *base, int speed)
 172 {
 173         struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
 174         u8 clk_idx = i2c_imx_get_clk(speed);
 175         u8 idx = i2c_clk_div[clk_idx][1];
 176
 177         /* Store divider value */
 178         writeb(idx, &i2c_regs->ifdr);
 179
 180         /* Reset module */
 181         writeb(I2CR_IDIS, &i2c_regs->i2cr);
 182         writeb(0, &i2c_regs->i2sr);
 183         return 0;
 184 }
 185
 186 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
 187 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
 188 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
 189
 190 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state)
 191 {
 192         unsigned sr;
 193         ulong elapsed;
 194         ulong start_time = get_timer(0);
 195         for (;;) {
 196                 sr = readb(&i2c_regs->i2sr);
 197                 if (sr & I2SR_IAL) {
 198 #ifdef I2C_QUIRK_REG
 199                         writeb(sr | I2SR_IAL, &i2c_regs->i2sr);
 200 #else
 201                         writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr);
 202 #endif
 203                         printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
 204                                 __func__, sr, readb(&i2c_regs->i2cr), state);
 205                         return -ERESTART;
 206                 }
 207                 if ((sr & (state >> 8)) == (unsigned char)state)
 208                         return sr;
 209                 WATCHDOG_RESET();
 210                 elapsed = get_timer(start_time);
 211                 if (elapsed > (CONFIG_SYS_HZ / 10))     /* .1 seconds */
 212                         break;
 213         }
 214         printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
 215                         sr, readb(&i2c_regs->i2cr), state);
 216         return -ETIMEDOUT;
 217 }
 218
 219 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
 220 {
 221         int ret;
 222
 223         writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
 224         writeb(byte, &i2c_regs->i2dr);
 225         ret = wait_for_sr_state(i2c_regs, ST_IIF);
 226         if (ret < 0)
 227                 return ret;
 228         if (ret & I2SR_RX_NO_AK)
 229                 return -ENODEV;
 230         return 0;
 231 }
 232
 233 /*
 234  * Stop I2C transaction
 235  */
 236 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs)
 237 {
 238         int ret;
 239         unsigned int temp = readb(&i2c_regs->i2cr);
 240
 241         temp &= ~(I2CR_MSTA | I2CR_MTX);
 242         writeb(temp, &i2c_regs->i2cr);
 243         ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
 244         if (ret < 0)
 245                 printf("%s:trigger stop failed\n", __func__);
 246 }
 247
 248 /*
 249  * Send start signal, chip address and
 250  * write register address
 251  */
 252 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs,
 253                 uchar chip, uint addr, int alen)
 254 {
 255         unsigned int temp;
 256         int ret;
 257
 258         /* Enable I2C controller */
 259 #ifdef I2C_QUIRK_REG
 260         if (readb(&i2c_regs->i2cr) & I2CR_IDIS) {
 261 #else
 262         if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) {
 263 #endif
 264                 writeb(I2CR_IEN, &i2c_regs->i2cr);
 265                 /* Wait for controller to be stable */
 266                 udelay(50);
 267         }
 268         if (readb(&i2c_regs->iadr) == (chip << 1))
 269                 writeb((chip << 1) ^ 2, &i2c_regs->iadr);
 270         writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
 271         ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE);
 272         if (ret < 0)
 273                 return ret;
 274
 275         /* Start I2C transaction */
 276         temp = readb(&i2c_regs->i2cr);
 277         temp |= I2CR_MSTA;
 278         writeb(temp, &i2c_regs->i2cr);
 279
 280         ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY);
 281         if (ret < 0)
 282                 return ret;
 283
 284         temp |= I2CR_MTX | I2CR_TX_NO_AK;
 285         writeb(temp, &i2c_regs->i2cr);
 286
 287         /* write slave address */
 288         ret = tx_byte(i2c_regs, chip << 1);
 289         if (ret < 0)
 290                 return ret;
 291
 292         while (alen--) {
 293                 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff);
 294                 if (ret < 0)
 295                         return ret;
 296         }
 297         return 0;
 298 }
 299
 300 static int i2c_idle_bus(void *base);
 301
 302 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs,
 303                 uchar chip, uint addr, int alen)
 304 {
 305         int retry;
 306         int ret;
 307         for (retry = 0; retry < 3; retry++) {
 308                 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen);
 309                 if (ret >= 0)
 310                         return 0;
 311                 i2c_imx_stop(i2c_regs);
 312                 if (ret == -ENODEV)
 313                         return ret;
 314
 315                 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
 316                                 retry);
 317                 if (ret != -ERESTART)
 318                         /* Disable controller */
 319                         writeb(I2CR_IDIS, &i2c_regs->i2cr);
 320                 udelay(100);
 321                 if (i2c_idle_bus(i2c_regs) < 0)
 322                         break;
 323         }
 324         printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs);
 325         return ret;
 326 }
 327
 328 /*
 329  * Read data from I2C device
 330  */
 331 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf,
 332                 int len)
 333 {
 334         int ret;
 335         unsigned int temp;
 336         int i;
 337         struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
 338
 339         ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
 340         if (ret < 0)
 341                 return ret;
 342
 343         temp = readb(&i2c_regs->i2cr);
 344         temp |= I2CR_RSTA;
 345         writeb(temp, &i2c_regs->i2cr);
 346
 347         ret = tx_byte(i2c_regs, (chip << 1) | 1);
 348         if (ret < 0) {
 349                 i2c_imx_stop(i2c_regs);
 350                 return ret;
 351         }
 352
 353         /* setup bus to read data */
 354         temp = readb(&i2c_regs->i2cr);
 355         temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
 356         if (len == 1)
 357                 temp |= I2CR_TX_NO_AK;
 358         writeb(temp, &i2c_regs->i2cr);
 359         writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
 360         readb(&i2c_regs->i2dr);         /* dummy read to clear ICF */
 361
 362         /* read data */
 363         for (i = 0; i < len; i++) {
 364                 ret = wait_for_sr_state(i2c_regs, ST_IIF);
 365                 if (ret < 0) {
 366                         i2c_imx_stop(i2c_regs);
 367                         return ret;
 368                 }
 369
 370                 /*
 371                  * It must generate STOP before read I2DR to prevent
 372                  * controller from generating another clock cycle
 373                  */
 374                 if (i == (len - 1)) {
 375                         i2c_imx_stop(i2c_regs);
 376                 } else if (i == (len - 2)) {
 377                         temp = readb(&i2c_regs->i2cr);
 378                         temp |= I2CR_TX_NO_AK;
 379                         writeb(temp, &i2c_regs->i2cr);
 380                 }
 381                 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr);
 382                 buf[i] = readb(&i2c_regs->i2dr);
 383         }
 384         i2c_imx_stop(i2c_regs);
 385         return 0;
 386 }
 387
 388 /*
 389  * Write data to I2C device
 390  */
 391 int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
 392                 const uchar *buf, int len)
 393 {
 394         int ret;
 395         int i;
 396         struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base;
 397
 398         ret = i2c_init_transfer(i2c_regs, chip, addr, alen);
 399         if (ret < 0)
 400                 return ret;
 401
 402         for (i = 0; i < len; i++) {
 403                 ret = tx_byte(i2c_regs, buf[i]);
 404                 if (ret < 0)
 405                         break;
 406         }
 407         i2c_imx_stop(i2c_regs);
 408         return ret;
 409 }
 410
 411 static void * const i2c_bases[] = {
 412 #if defined(CONFIG_MX25)
 413         (void *)IMX_I2C_BASE,
 414         (void *)IMX_I2C2_BASE,
 415         (void *)IMX_I2C3_BASE
 416 #elif defined(CONFIG_MX27)
 417         (void *)IMX_I2C1_BASE,
 418         (void *)IMX_I2C2_BASE
 419 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
 420         defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
 421         defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
 422         (void *)I2C1_BASE_ADDR,
 423         (void *)I2C2_BASE_ADDR,
 424         (void *)I2C3_BASE_ADDR
 425 #elif defined(CONFIG_VF610)
 426         (void *)I2C0_BASE_ADDR
 427 #elif defined(CONFIG_FSL_LSCH3)
 428         (void *)I2C1_BASE_ADDR,
 429         (void *)I2C2_BASE_ADDR,
 430         (void *)I2C3_BASE_ADDR,
 431         (void *)I2C4_BASE_ADDR
 432 #else
 433 #error "architecture not supported"
 434 #endif
 435 };
 436
 437 struct i2c_parms {
 438         void *base;
 439         void *idle_bus_data;
 440         int (*idle_bus_fn)(void *p);
 441 };
 442
 443 struct sram_data {
 444         unsigned curr_i2c_bus;
 445         struct i2c_parms i2c_data[ARRAY_SIZE(i2c_bases)];
 446 };
 447
 448 void *i2c_get_base(struct i2c_adapter *adap)
 449 {
 450         return i2c_bases[adap->hwadapnr];
 451 }
 452
 453 static struct i2c_parms *i2c_get_parms(void *base)
 454 {
 455         struct sram_data *srdata = (void *)gd->srdata;
 456         int i = 0;
 457         struct i2c_parms *p = srdata->i2c_data;
 458         while (i < ARRAY_SIZE(srdata->i2c_data)) {
 459                 if (p->base == base)
 460                         return p;
 461                 p++;
 462                 i++;
 463         }
 464         printf("Invalid I2C base: %p\n", base);
 465         return NULL;
 466 }
 467
 468 static int i2c_idle_bus(void *base)
 469 {
 470         struct i2c_parms *p = i2c_get_parms(base);
 471         if (p && p->idle_bus_fn)
 472                 return p->idle_bus_fn(p->idle_bus_data);
 473         return 0;
 474 }
 475
 476 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
 477                                 uint addr, int alen, uint8_t *buffer,
 478                                 int len)
 479 {
 480         return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
 481 }
 482
 483 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
 484                                 uint addr, int alen, uint8_t *buffer,
 485                                 int len)
 486 {
 487         return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
 488 }
 489
 490 /*
 491  * Test if a chip at a given address responds (probe the chip)
 492  */
 493 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
 494 {
 495         return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
 496 }
 497
 498 void bus_i2c_init(void *base, int speed, int unused,
 499                 int (*idle_bus_fn)(void *p), void *idle_bus_data)
 500 {
 501         struct sram_data *srdata = (void *)gd->srdata;
 502         int i = 0;
 503         struct i2c_parms *p = srdata->i2c_data;
 504         if (!base)
 505                 return;
 506         for (;;) {
 507                 if (!p->base || (p->base == base)) {
 508                         p->base = base;
 509                         if (idle_bus_fn) {
 510                                 p->idle_bus_fn = idle_bus_fn;
 511                                 p->idle_bus_data = idle_bus_data;
 512                         }
 513                         break;
 514                 }
 515                 p++;
 516                 i++;
 517                 if (i >= ARRAY_SIZE(srdata->i2c_data))
 518                         return;
 519         }
 520         bus_i2c_set_bus_speed(base, speed);
 521 }
 522
 523 /*
 524  * Init I2C Bus
 525  */
 526 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 527 {
 528         bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL);
 529 }
 530
 531 /*
 532  * Set I2C Speed
 533  */
 534 static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
 535 {
 536         return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
 537 }
 538
 539 /*
 540  * Register mxc i2c adapters
 541  */
 542 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
 543                          mxc_i2c_read, mxc_i2c_write,
 544                          mxc_i2c_set_bus_speed,
 545                          CONFIG_SYS_MXC_I2C1_SPEED,
 546                          CONFIG_SYS_MXC_I2C1_SLAVE, 0)
 547 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
 548                          mxc_i2c_read, mxc_i2c_write,
 549                          mxc_i2c_set_bus_speed,
 550                          CONFIG_SYS_MXC_I2C2_SPEED,
 551                          CONFIG_SYS_MXC_I2C2_SLAVE, 1)
 552 #ifdef CONFIG_SYS_I2C_MXC_I2C3
 553 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
 554                          mxc_i2c_read, mxc_i2c_write,
 555                          mxc_i2c_set_bus_speed,
 556                          CONFIG_SYS_MXC_I2C3_SPEED,
 557                          CONFIG_SYS_MXC_I2C3_SLAVE, 2)
 558 #endif
 559 #ifdef CONFIG_SYS_I2C_MXC_I2C4
 560 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
 561                          mxc_i2c_read, mxc_i2c_write,
 562                          mxc_i2c_set_bus_speed,
 563                          CONFIG_SYS_MXC_I2C4_SPEED,
 564                          CONFIG_SYS_MXC_I2C4_SLAVE, 3)
 565 #endif