drivers/i2c/mxs_i2c.c

   1 /*
   2  * Freescale i.MX28 I2C Driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Partly based on Linux kernel i2c-mxs.c driver:
   8  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   9  *
  10  * Which was based on a (non-working) driver which was:
  11  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <malloc.h>
  18 #include <i2c.h>
  19 #include <asm/errno.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/imx-regs.h>
  23 #include <asm/arch/sys_proto.h>
  24
  25 #define MXS_I2C_MAX_TIMEOUT     1000000
  26
  27 static void mxs_i2c_reset(void)
  28 {
  29         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  30         int ret;
  31         int speed = i2c_get_bus_speed();
  32
  33         ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
  34         if (ret) {
  35                 debug("MXS I2C: Block reset timeout\n");
  36                 return;
  37         }
  38
  39         writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
  40                 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
  41                 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
  42                 &i2c_regs->hw_i2c_ctrl1_clr);
  43
  44         writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
  45
  46         i2c_set_bus_speed(speed);
  47 }
  48
  49 static void mxs_i2c_setup_read(uint8_t chip, int len)
  50 {
  51         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  52
  53         writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
  54                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
  55                 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
  56                 &i2c_regs->hw_i2c_queuecmd);
  57
  58         writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
  59
  60         writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
  61                 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
  62                 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
  63
  64         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
  65 }
  66
  67 static int mxs_i2c_write(uchar chip, uint addr, int alen,
  68                         uchar *buf, int blen, int stop)
  69 {
  70         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  71         uint32_t data, tmp;
  72         int i, remain, off;
  73         int timeout = MXS_I2C_MAX_TIMEOUT;
  74
  75         if ((alen > 4) || (alen == 0)) {
  76                 debug("MXS I2C: Invalid address length\n");
  77                 return -EINVAL;
  78         }
  79
  80         if (stop)
  81                 stop = I2C_QUEUECMD_POST_SEND_STOP;
  82
  83         writel(I2C_QUEUECMD_PRE_SEND_START |
  84                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
  85                 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
  86                 &i2c_regs->hw_i2c_queuecmd);
  87
  88         data = (chip << 1) << 24;
  89
  90         for (i = 0; i < alen; i++) {
  91                 data >>= 8;
  92                 data |= ((char *)&addr)[alen - i - 1] << 24;
  93                 if ((i & 3) == 2)
  94                         writel(data, &i2c_regs->hw_i2c_data);
  95         }
  96
  97         off = i;
  98         for (; i < off + blen; i++) {
  99                 data >>= 8;
 100                 data |= buf[i - off] << 24;
 101                 if ((i & 3) == 2)
 102                         writel(data, &i2c_regs->hw_i2c_data);
 103         }
 104
 105         remain = 24 - ((i & 3) * 8);
 106         if (remain)
 107                 writel(data >> remain, &i2c_regs->hw_i2c_data);
 108
 109         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 110
 111         while (--timeout) {
 112                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 113                 if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY)
 114                         break;
 115         }
 116
 117         if (!timeout) {
 118                 debug("MXS I2C: Failed transmitting data!\n");
 119                 return -EINVAL;
 120         }
 121
 122         return 0;
 123 }
 124
 125 static int mxs_i2c_wait_for_ack(void)
 126 {
 127         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 128         uint32_t tmp;
 129         int timeout = MXS_I2C_MAX_TIMEOUT;
 130
 131         for (;;) {
 132                 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
 133                 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
 134                         debug("MXS I2C: No slave ACK\n");
 135                         goto err;
 136                 }
 137
 138                 if (tmp & (
 139                         I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 140                         I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
 141                         debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
 142                         goto err;
 143                 }
 144
 145                 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
 146                         break;
 147
 148                 if (!timeout--) {
 149                         debug("MXS I2C: Operation timed out\n");
 150                         goto err;
 151                 }
 152
 153                 udelay(1);
 154         }
 155
 156         return 0;
 157
 158 err:
 159         mxs_i2c_reset();
 160         return 1;
 161 }
 162
 163 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 164 {
 165         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 166         uint32_t tmp = 0;
 167         int timeout = MXS_I2C_MAX_TIMEOUT;
 168         int ret;
 169         int i;
 170
 171         ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
 172         if (ret) {
 173                 debug("MXS I2C: Failed writing address\n");
 174                 return ret;
 175         }
 176
 177         ret = mxs_i2c_wait_for_ack();
 178         if (ret) {
 179                 debug("MXS I2C: Failed writing address\n");
 180                 return ret;
 181         }
 182
 183         mxs_i2c_setup_read(chip, len);
 184         ret = mxs_i2c_wait_for_ack();
 185         if (ret) {
 186                 debug("MXS I2C: Failed reading address\n");
 187                 return ret;
 188         }
 189
 190         for (i = 0; i < len; i++) {
 191                 if (!(i & 3)) {
 192                         while (--timeout) {
 193                                 tmp = readl(&i2c_regs->hw_i2c_queuestat);
 194                                 if (!(tmp & I2C_QUEUESTAT_RD_QUEUE_EMPTY))
 195                                         break;
 196                         }
 197
 198                         if (!timeout) {
 199                                 debug("MXS I2C: Failed receiving data!\n");
 200                                 return -ETIMEDOUT;
 201                         }
 202
 203                         tmp = readl(&i2c_regs->hw_i2c_queuedata);
 204                 }
 205                 buffer[i] = tmp & 0xff;
 206                 tmp >>= 8;
 207         }
 208
 209         return 0;
 210 }
 211
 212 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 213 {
 214         int ret;
 215         ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1);
 216         if (ret) {
 217                 debug("MXS I2C: Failed writing address\n");
 218                 return ret;
 219         }
 220
 221         ret = mxs_i2c_wait_for_ack();
 222         if (ret)
 223                 debug("MXS I2C: Failed writing address\n");
 224
 225         return ret;
 226 }
 227
 228 int i2c_probe(uchar chip)
 229 {
 230         int ret;
 231         ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
 232         if (!ret)
 233                 ret = mxs_i2c_wait_for_ack();
 234         mxs_i2c_reset();
 235         return ret;
 236 }
 237
 238 int i2c_set_bus_speed(unsigned int speed)
 239 {
 240         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 241         /*
 242          * The timing derivation algorithm. There is no documentation for this
 243          * algorithm available, it was derived by using the scope and fiddling
 244          * with constants until the result observed on the scope was good enough
 245          * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
 246          * possible to assume the algorithm works for other frequencies as well.
 247          *
 248          * Note it was necessary to cap the frequency on both ends as it's not
 249          * possible to configure completely arbitrary frequency for the I2C bus
 250          * clock.
 251          */
 252         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
 253         uint32_t base = ((clk / speed) - 38) / 2;
 254         uint16_t high_count = base + 3;
 255         uint16_t low_count = base - 3;
 256         uint16_t rcv_count = (high_count * 3) / 4;
 257         uint16_t xmit_count = low_count / 4;
 258
 259         if (speed > 540000) {
 260                 printf("MXS I2C: Speed too high (%d Hz)\n", speed);
 261                 return -EINVAL;
 262         }
 263
 264         if (speed < 12000) {
 265                 printf("MXS I2C: Speed too low (%d Hz)\n", speed);
 266                 return -EINVAL;
 267         }
 268
 269         writel((high_count << 16) | rcv_count, &i2c_regs->hw_i2c_timing0);
 270         writel((low_count << 16) | xmit_count, &i2c_regs->hw_i2c_timing1);
 271
 272         writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
 273                 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
 274                 &i2c_regs->hw_i2c_timing2);
 275
 276         return 0;
 277 }
 278
 279 unsigned int i2c_get_bus_speed(void)
 280 {
 281         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 282         uint32_t clk = mxc_get_clock(MXC_XTAL_CLK);
 283         uint32_t timing0;
 284
 285         timing0 = readl(&i2c_regs->hw_i2c_timing0);
 286         /*
 287          * This is a reverse version of the algorithm presented in
 288          * i2c_set_bus_speed(). Please refer there for details.
 289          */
 290         return clk / ((((timing0 >> 16) - 3) * 2) + 38);
 291 }
 292
 293 void i2c_init(int speed, int slaveadd)
 294 {
 295         mxs_i2c_reset();
 296         i2c_set_bus_speed(speed);
 297
 298         return;
 299 }