drivers/i2c/mxs_i2c.c

   1 /*
   2  * Freescale i.MX28 I2C Driver
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Partly based on Linux kernel i2c-mxs.c driver:
   8  * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
   9  *
  10  * Which was based on a (non-working) driver which was:
  11  * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  26  *
  27  */
  28
  29 #include <common.h>
  30 #include <malloc.h>
  31 #include <asm/errno.h>
  32 #include <asm/io.h>
  33 #include <asm/arch/clock.h>
  34 #include <asm/arch/imx-regs.h>
  35 #include <asm/arch/sys_proto.h>
  36
  37 #define MXS_I2C_MAX_TIMEOUT     1000000
  38
  39 void mxs_i2c_reset(void)
  40 {
  41         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  42         int ret;
  43         int speed = i2c_get_bus_speed();
  44
  45         ret = mxs_reset_block(&i2c_regs->hw_i2c_ctrl0_reg);
  46         if (ret) {
  47                 debug("MXS I2C: Block reset timeout\n");
  48                 return;
  49         }
  50
  51         writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | I2C_CTRL1_NO_SLAVE_ACK_IRQ |
  52                 I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
  53                 I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ,
  54                 &i2c_regs->hw_i2c_ctrl1_clr);
  55
  56         writel(I2C_QUEUECTRL_PIO_QUEUE_MODE, &i2c_regs->hw_i2c_queuectrl_set);
  57
  58         i2c_set_bus_speed(speed);
  59 }
  60
  61 void mxs_i2c_setup_read(uint8_t chip, int len)
  62 {
  63         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  64
  65         writel(I2C_QUEUECMD_RETAIN_CLOCK | I2C_QUEUECMD_PRE_SEND_START |
  66                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
  67                 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET),
  68                 &i2c_regs->hw_i2c_queuecmd);
  69
  70         writel((chip << 1) | 1, &i2c_regs->hw_i2c_data);
  71
  72         writel(I2C_QUEUECMD_SEND_NAK_ON_LAST | I2C_QUEUECMD_MASTER_MODE |
  73                 (len << I2C_QUEUECMD_XFER_COUNT_OFFSET) |
  74                 I2C_QUEUECMD_POST_SEND_STOP, &i2c_regs->hw_i2c_queuecmd);
  75
  76         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
  77 }
  78
  79 void mxs_i2c_write(uchar chip, uint addr, int alen,
  80                         uchar *buf, int blen, int stop)
  81 {
  82         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
  83         uint32_t data;
  84         int i, remain, off;
  85
  86         if ((alen > 4) || (alen == 0)) {
  87                 debug("MXS I2C: Invalid address length\n");
  88                 return;
  89         }
  90
  91         if (stop)
  92                 stop = I2C_QUEUECMD_POST_SEND_STOP;
  93
  94         writel(I2C_QUEUECMD_PRE_SEND_START |
  95                 I2C_QUEUECMD_MASTER_MODE | I2C_QUEUECMD_DIRECTION |
  96                 ((blen + alen + 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET) | stop,
  97                 &i2c_regs->hw_i2c_queuecmd);
  98
  99         data = (chip << 1) << 24;
 100
 101         for (i = 0; i < alen; i++) {
 102                 data >>= 8;
 103                 data |= ((char *)&addr)[alen - i - 1] << 24;
 104                 if ((i & 3) == 2)
 105                         writel(data, &i2c_regs->hw_i2c_data);
 106         }
 107
 108         off = i;
 109         for (; i < off + blen; i++) {
 110                 data >>= 8;
 111                 data |= buf[i - off] << 24;
 112                 if ((i & 3) == 2)
 113                         writel(data, &i2c_regs->hw_i2c_data);
 114         }
 115
 116         remain = 24 - ((i & 3) * 8);
 117         if (remain)
 118                 writel(data >> remain, &i2c_regs->hw_i2c_data);
 119
 120         writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set);
 121 }
 122
 123 int mxs_i2c_wait_for_ack(void)
 124 {
 125         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 126         uint32_t tmp;
 127         int timeout = MXS_I2C_MAX_TIMEOUT;
 128
 129         for (;;) {
 130                 tmp = readl(&i2c_regs->hw_i2c_ctrl1);
 131                 if (tmp & I2C_CTRL1_NO_SLAVE_ACK_IRQ) {
 132                         debug("MXS I2C: No slave ACK\n");
 133                         goto err;
 134                 }
 135
 136                 if (tmp & (
 137                         I2C_CTRL1_EARLY_TERM_IRQ | I2C_CTRL1_MASTER_LOSS_IRQ |
 138                         I2C_CTRL1_SLAVE_STOP_IRQ | I2C_CTRL1_SLAVE_IRQ)) {
 139                         debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp);
 140                         goto err;
 141                 }
 142
 143                 if (tmp & I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ)
 144                         break;
 145
 146                 if (!timeout--) {
 147                         debug("MXS I2C: Operation timed out\n");
 148                         goto err;
 149                 }
 150
 151                 udelay(1);
 152         }
 153
 154         return 0;
 155
 156 err:
 157         mxs_i2c_reset();
 158         return 1;
 159 }
 160
 161 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 162 {
 163         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 164         uint32_t tmp = 0;
 165         int ret;
 166         int i;
 167
 168         mxs_i2c_write(chip, addr, alen, NULL, 0, 0);
 169         ret = mxs_i2c_wait_for_ack();
 170         if (ret) {
 171                 debug("MXS I2C: Failed writing address\n");
 172                 return ret;
 173         }
 174
 175         mxs_i2c_setup_read(chip, len);
 176         ret = mxs_i2c_wait_for_ack();
 177         if (ret) {
 178                 debug("MXS I2C: Failed reading address\n");
 179                 return ret;
 180         }
 181
 182         for (i = 0; i < len; i++) {
 183                 if (!(i & 3)) {
 184                         while (readl(&i2c_regs->hw_i2c_queuestat) &
 185                                 I2C_QUEUESTAT_RD_QUEUE_EMPTY)
 186                                 ;
 187                         tmp = readl(&i2c_regs->hw_i2c_queuedata);
 188                 }
 189                 buffer[i] = tmp & 0xff;
 190                 tmp >>= 8;
 191         }
 192
 193         return 0;
 194 }
 195
 196 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 197 {
 198         int ret;
 199         mxs_i2c_write(chip, addr, alen, buffer, len, 1);
 200         ret = mxs_i2c_wait_for_ack();
 201         if (ret)
 202                 debug("MXS I2C: Failed writing address\n");
 203
 204         return ret;
 205 }
 206
 207 int i2c_probe(uchar chip)
 208 {
 209         int ret;
 210         mxs_i2c_write(chip, 0, 1, NULL, 0, 1);
 211         ret = mxs_i2c_wait_for_ack();
 212         mxs_i2c_reset();
 213         return ret;
 214 }
 215
 216 static struct mxs_i2c_speed_table {
 217         uint32_t        speed;
 218         uint32_t        timing0;
 219         uint32_t        timing1;
 220 } mxs_i2c_tbl[] = {
 221         {
 222                 100000,
 223                 (0x0078 << I2C_TIMING0_HIGH_COUNT_OFFSET) |
 224                 (0x0030 << I2C_TIMING0_RCV_COUNT_OFFSET),
 225                 (0x0080 << I2C_TIMING1_LOW_COUNT_OFFSET) |
 226                 (0x0030 << I2C_TIMING1_XMIT_COUNT_OFFSET)
 227         },
 228         {
 229                 400000,
 230                 (0x000f << I2C_TIMING0_HIGH_COUNT_OFFSET) |
 231                 (0x0007 << I2C_TIMING0_RCV_COUNT_OFFSET),
 232                 (0x001f << I2C_TIMING1_LOW_COUNT_OFFSET) |
 233                 (0x000f << I2C_TIMING1_XMIT_COUNT_OFFSET),
 234         }
 235 };
 236
 237 static struct mxs_i2c_speed_table *mxs_i2c_speed_to_cfg(uint32_t speed)
 238 {
 239         int i;
 240         for (i = 0; i < ARRAY_SIZE(mxs_i2c_tbl); i++)
 241                 if (mxs_i2c_tbl[i].speed == speed)
 242                         return &mxs_i2c_tbl[i];
 243         return NULL;
 244 }
 245
 246 static uint32_t mxs_i2c_cfg_to_speed(uint32_t timing0, uint32_t timing1)
 247 {
 248         int i;
 249         for (i = 0; i < ARRAY_SIZE(mxs_i2c_tbl); i++) {
 250                 if (mxs_i2c_tbl[i].timing0 != timing0)
 251                         continue;
 252                 if (mxs_i2c_tbl[i].timing1 != timing1)
 253                         continue;
 254                 return mxs_i2c_tbl[i].speed;
 255         }
 256
 257         return 0;
 258 }
 259
 260 int i2c_set_bus_speed(unsigned int speed)
 261 {
 262         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 263         struct mxs_i2c_speed_table *spd = mxs_i2c_speed_to_cfg(speed);
 264
 265         if (!spd) {
 266                 printf("MXS I2C: Invalid speed selected (%d Hz)\n", speed);
 267                 return -EINVAL;
 268         }
 269
 270         writel(spd->timing0, &i2c_regs->hw_i2c_timing0);
 271         writel(spd->timing1, &i2c_regs->hw_i2c_timing1);
 272
 273         writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET) |
 274                 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET),
 275                 &i2c_regs->hw_i2c_timing2);
 276
 277         return 0;
 278 }
 279
 280 unsigned int i2c_get_bus_speed(void)
 281 {
 282         struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE;
 283         uint32_t timing0, timing1;
 284
 285         timing0 = readl(&i2c_regs->hw_i2c_timing0);
 286         timing1 = readl(&i2c_regs->hw_i2c_timing1);
 287
 288         return mxs_i2c_cfg_to_speed(timing0, timing1);
 289 }
 290
 291 void i2c_init(int speed, int slaveadd)
 292 {
 293         mxs_i2c_reset();
 294         i2c_set_bus_speed(speed);
 295
 296         return;
 297 }