2 * Freescale i.MX28 I2C Driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Partly based on Linux kernel i2c-mxs.c driver:
8 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
10 * Which was based on a (non-working) driver which was:
11 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
32 #include <asm/errno.h>
34 #include <asm/arch/clock.h>
35 #include <asm/arch/imx-regs.h>
36 #include <asm/arch/sys_proto.h>
38 #define MXS_I2C_MAX_TIMEOUT 1000000
40 void mxs_i2c_reset(void)
42 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
44 int speed
= i2c_get_bus_speed();
46 ret
= mxs_reset_block(&i2c_regs
->hw_i2c_ctrl0_reg
);
48 debug("MXS I2C: Block reset timeout\n");
52 writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
| I2C_CTRL1_NO_SLAVE_ACK_IRQ
|
53 I2C_CTRL1_EARLY_TERM_IRQ
| I2C_CTRL1_MASTER_LOSS_IRQ
|
54 I2C_CTRL1_SLAVE_STOP_IRQ
| I2C_CTRL1_SLAVE_IRQ
,
55 &i2c_regs
->hw_i2c_ctrl1_clr
);
57 writel(I2C_QUEUECTRL_PIO_QUEUE_MODE
, &i2c_regs
->hw_i2c_queuectrl_set
);
59 i2c_set_bus_speed(speed
);
62 void mxs_i2c_setup_read(uint8_t chip
, int len
)
64 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
66 writel(I2C_QUEUECMD_RETAIN_CLOCK
| I2C_QUEUECMD_PRE_SEND_START
|
67 I2C_QUEUECMD_MASTER_MODE
| I2C_QUEUECMD_DIRECTION
|
68 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET
),
69 &i2c_regs
->hw_i2c_queuecmd
);
71 writel((chip
<< 1) | 1, &i2c_regs
->hw_i2c_data
);
73 writel(I2C_QUEUECMD_SEND_NAK_ON_LAST
| I2C_QUEUECMD_MASTER_MODE
|
74 (len
<< I2C_QUEUECMD_XFER_COUNT_OFFSET
) |
75 I2C_QUEUECMD_POST_SEND_STOP
, &i2c_regs
->hw_i2c_queuecmd
);
77 writel(I2C_QUEUECTRL_QUEUE_RUN
, &i2c_regs
->hw_i2c_queuectrl_set
);
80 void mxs_i2c_write(uchar chip
, uint addr
, int alen
,
81 uchar
*buf
, int blen
, int stop
)
83 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
87 if ((alen
> 4) || (alen
== 0)) {
88 debug("MXS I2C: Invalid address length\n");
93 stop
= I2C_QUEUECMD_POST_SEND_STOP
;
95 writel(I2C_QUEUECMD_PRE_SEND_START
|
96 I2C_QUEUECMD_MASTER_MODE
| I2C_QUEUECMD_DIRECTION
|
97 ((blen
+ alen
+ 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET
) | stop
,
98 &i2c_regs
->hw_i2c_queuecmd
);
100 data
= (chip
<< 1) << 24;
102 for (i
= 0; i
< alen
; i
++) {
104 data
|= ((char *)&addr
)[alen
- i
- 1] << 24;
106 writel(data
, &i2c_regs
->hw_i2c_data
);
110 for (; i
< off
+ blen
; i
++) {
112 data
|= buf
[i
- off
] << 24;
114 writel(data
, &i2c_regs
->hw_i2c_data
);
117 remain
= 24 - ((i
& 3) * 8);
119 writel(data
>> remain
, &i2c_regs
->hw_i2c_data
);
121 writel(I2C_QUEUECTRL_QUEUE_RUN
, &i2c_regs
->hw_i2c_queuectrl_set
);
124 int mxs_i2c_wait_for_ack(void)
126 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
128 int timeout
= MXS_I2C_MAX_TIMEOUT
;
131 tmp
= readl(&i2c_regs
->hw_i2c_ctrl1
);
132 if (tmp
& I2C_CTRL1_NO_SLAVE_ACK_IRQ
) {
133 debug("MXS I2C: No slave ACK\n");
138 I2C_CTRL1_EARLY_TERM_IRQ
| I2C_CTRL1_MASTER_LOSS_IRQ
|
139 I2C_CTRL1_SLAVE_STOP_IRQ
| I2C_CTRL1_SLAVE_IRQ
)) {
140 debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp
);
144 if (tmp
& I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
)
148 debug("MXS I2C: Operation timed out\n");
162 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
164 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
169 mxs_i2c_write(chip
, addr
, alen
, NULL
, 0, 0);
170 ret
= mxs_i2c_wait_for_ack();
172 debug("MXS I2C: Failed writing address\n");
176 mxs_i2c_setup_read(chip
, len
);
177 ret
= mxs_i2c_wait_for_ack();
179 debug("MXS I2C: Failed reading address\n");
183 for (i
= 0; i
< len
; i
++) {
185 while (readl(&i2c_regs
->hw_i2c_queuestat
) &
186 I2C_QUEUESTAT_RD_QUEUE_EMPTY
)
188 tmp
= readl(&i2c_regs
->hw_i2c_queuedata
);
190 buffer
[i
] = tmp
& 0xff;
197 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
200 mxs_i2c_write(chip
, addr
, alen
, buffer
, len
, 1);
201 ret
= mxs_i2c_wait_for_ack();
203 debug("MXS I2C: Failed writing address\n");
208 int i2c_probe(uchar chip
)
211 mxs_i2c_write(chip
, 0, 1, NULL
, 0, 1);
212 ret
= mxs_i2c_wait_for_ack();
217 int i2c_set_bus_speed(unsigned int speed
)
219 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
221 * The timing derivation algorithm. There is no documentation for this
222 * algorithm available, it was derived by using the scope and fiddling
223 * with constants until the result observed on the scope was good enough
224 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
225 * possible to assume the algorithm works for other frequencies as well.
227 * Note it was necessary to cap the frequency on both ends as it's not
228 * possible to configure completely arbitrary frequency for the I2C bus
231 uint32_t clk
= mxc_get_clock(MXC_XTAL_CLK
);
232 uint32_t base
= ((clk
/ speed
) - 38) / 2;
233 uint16_t high_count
= base
+ 3;
234 uint16_t low_count
= base
- 3;
235 uint16_t rcv_count
= (high_count
* 3) / 4;
236 uint16_t xmit_count
= low_count
/ 4;
238 if (speed
> 540000) {
239 printf("MXS I2C: Speed too high (%d Hz)\n", speed
);
244 printf("MXS I2C: Speed too low (%d Hz)\n", speed
);
248 writel((high_count
<< 16) | rcv_count
, &i2c_regs
->hw_i2c_timing0
);
249 writel((low_count
<< 16) | xmit_count
, &i2c_regs
->hw_i2c_timing1
);
251 writel((0x0030 << I2C_TIMING2_BUS_FREE_OFFSET
) |
252 (0x0030 << I2C_TIMING2_LEADIN_COUNT_OFFSET
),
253 &i2c_regs
->hw_i2c_timing2
);
258 unsigned int i2c_get_bus_speed(void)
260 struct mxs_i2c_regs
*i2c_regs
= (struct mxs_i2c_regs
*)MXS_I2C0_BASE
;
261 uint32_t clk
= mxc_get_clock(MXC_XTAL_CLK
);
264 timing0
= readl(&i2c_regs
->hw_i2c_timing0
);
266 * This is a reverse version of the algorithm presented in
267 * i2c_set_bus_speed(). Please refer there for details.
269 return clk
/ ((((timing0
>> 16) - 3) * 2) + 38);
272 void i2c_init(int speed
, int slaveadd
)
275 i2c_set_bus_speed(speed
);