2 * Freescale i.MX28 I2C Driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Partly based on Linux kernel i2c-mxs.c driver:
8 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
10 * Which was based on a (non-working) driver which was:
11 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <asm/errno.h>
33 #include <asm/arch/clock.h>
34 #include <asm/arch/imx-regs.h>
35 #include <asm/arch/sys_proto.h>
37 #define MXS_I2C_MAX_TIMEOUT 1000000
39 void mxs_i2c_reset(void)
41 struct mx28_i2c_regs
*i2c_regs
= (struct mx28_i2c_regs
*)MXS_I2C0_BASE
;
44 ret
= mx28_reset_block(&i2c_regs
->hw_i2c_ctrl0_reg
);
46 debug("MXS I2C: Block reset timeout\n");
50 writel(I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
| I2C_CTRL1_NO_SLAVE_ACK_IRQ
|
51 I2C_CTRL1_EARLY_TERM_IRQ
| I2C_CTRL1_MASTER_LOSS_IRQ
|
52 I2C_CTRL1_SLAVE_STOP_IRQ
| I2C_CTRL1_SLAVE_IRQ
,
53 &i2c_regs
->hw_i2c_ctrl1_clr
);
55 writel(I2C_QUEUECTRL_PIO_QUEUE_MODE
, &i2c_regs
->hw_i2c_queuectrl_set
);
58 void mxs_i2c_setup_read(uint8_t chip
, int len
)
60 struct mx28_i2c_regs
*i2c_regs
= (struct mx28_i2c_regs
*)MXS_I2C0_BASE
;
62 writel(I2C_QUEUECMD_RETAIN_CLOCK
| I2C_QUEUECMD_PRE_SEND_START
|
63 I2C_QUEUECMD_MASTER_MODE
| I2C_QUEUECMD_DIRECTION
|
64 (1 << I2C_QUEUECMD_XFER_COUNT_OFFSET
),
65 &i2c_regs
->hw_i2c_queuecmd
);
67 writel((chip
<< 1) | 1, &i2c_regs
->hw_i2c_data
);
69 writel(I2C_QUEUECMD_SEND_NAK_ON_LAST
| I2C_QUEUECMD_MASTER_MODE
|
70 (len
<< I2C_QUEUECMD_XFER_COUNT_OFFSET
) |
71 I2C_QUEUECMD_POST_SEND_STOP
, &i2c_regs
->hw_i2c_queuecmd
);
73 writel(I2C_QUEUECTRL_QUEUE_RUN
, &i2c_regs
->hw_i2c_queuectrl_set
);
76 void mxs_i2c_write(uchar chip
, uint addr
, int alen
,
77 uchar
*buf
, int blen
, int stop
)
79 struct mx28_i2c_regs
*i2c_regs
= (struct mx28_i2c_regs
*)MXS_I2C0_BASE
;
83 if ((alen
> 4) || (alen
== 0)) {
84 debug("MXS I2C: Invalid address length\n");
89 stop
= I2C_QUEUECMD_POST_SEND_STOP
;
91 writel(I2C_QUEUECMD_PRE_SEND_START
|
92 I2C_QUEUECMD_MASTER_MODE
| I2C_QUEUECMD_DIRECTION
|
93 ((blen
+ alen
+ 1) << I2C_QUEUECMD_XFER_COUNT_OFFSET
) | stop
,
94 &i2c_regs
->hw_i2c_queuecmd
);
96 data
= (chip
<< 1) << 24;
98 for (i
= 0; i
< alen
; i
++) {
100 data
|= ((char *)&addr
)[i
] << 24;
102 writel(data
, &i2c_regs
->hw_i2c_data
);
106 for (; i
< off
+ blen
; i
++) {
108 data
|= buf
[i
- off
] << 24;
110 writel(data
, &i2c_regs
->hw_i2c_data
);
113 remain
= 24 - ((i
& 3) * 8);
115 writel(data
>> remain
, &i2c_regs
->hw_i2c_data
);
117 writel(I2C_QUEUECTRL_QUEUE_RUN
, &i2c_regs
->hw_i2c_queuectrl_set
);
120 int mxs_i2c_wait_for_ack(void)
122 struct mx28_i2c_regs
*i2c_regs
= (struct mx28_i2c_regs
*)MXS_I2C0_BASE
;
124 int timeout
= MXS_I2C_MAX_TIMEOUT
;
127 tmp
= readl(&i2c_regs
->hw_i2c_ctrl1
);
128 if (tmp
& I2C_CTRL1_NO_SLAVE_ACK_IRQ
) {
129 debug("MXS I2C: No slave ACK\n");
134 I2C_CTRL1_EARLY_TERM_IRQ
| I2C_CTRL1_MASTER_LOSS_IRQ
|
135 I2C_CTRL1_SLAVE_STOP_IRQ
| I2C_CTRL1_SLAVE_IRQ
)) {
136 debug("MXS I2C: Error (CTRL1 = %08x)\n", tmp
);
140 if (tmp
& I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ
)
144 debug("MXS I2C: Operation timed out\n");
158 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
160 struct mx28_i2c_regs
*i2c_regs
= (struct mx28_i2c_regs
*)MXS_I2C0_BASE
;
165 mxs_i2c_write(chip
, addr
, alen
, NULL
, 0, 0);
166 ret
= mxs_i2c_wait_for_ack();
168 debug("MXS I2C: Failed writing address\n");
172 mxs_i2c_setup_read(chip
, len
);
173 ret
= mxs_i2c_wait_for_ack();
175 debug("MXS I2C: Failed reading address\n");
179 for (i
= 0; i
< len
; i
++) {
181 while (readl(&i2c_regs
->hw_i2c_queuestat
) &
182 I2C_QUEUESTAT_RD_QUEUE_EMPTY
)
184 tmp
= readl(&i2c_regs
->hw_i2c_queuedata
);
186 buffer
[i
] = tmp
& 0xff;
193 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
196 mxs_i2c_write(chip
, addr
, alen
, buffer
, len
, 1);
197 ret
= mxs_i2c_wait_for_ack();
199 debug("MXS I2C: Failed writing address\n");
204 int i2c_probe(uchar chip
)
207 mxs_i2c_write(chip
, 0, 1, NULL
, 0, 1);
208 ret
= mxs_i2c_wait_for_ack();
213 void i2c_init(int speed
, int slaveadd
)
215 struct mx28_i2c_regs
*i2c_regs
= (struct mx28_i2c_regs
*)MXS_I2C0_BASE
;
221 writel((0x0078 << I2C_TIMING0_HIGH_COUNT_OFFSET
) |
222 (0x0030 << I2C_TIMING0_RCV_COUNT_OFFSET
),
223 &i2c_regs
->hw_i2c_timing0
);
224 writel((0x0080 << I2C_TIMING1_LOW_COUNT_OFFSET
) |
225 (0x0030 << I2C_TIMING1_XMIT_COUNT_OFFSET
),
226 &i2c_regs
->hw_i2c_timing1
);
229 writel((0x000f << I2C_TIMING0_HIGH_COUNT_OFFSET
) |
230 (0x0007 << I2C_TIMING0_RCV_COUNT_OFFSET
),
231 &i2c_regs
->hw_i2c_timing0
);
232 writel((0x001f << I2C_TIMING1_LOW_COUNT_OFFSET
) |
233 (0x000f << I2C_TIMING1_XMIT_COUNT_OFFSET
),
234 &i2c_regs
->hw_i2c_timing1
);
237 printf("MXS I2C: Invalid speed selected (%d Hz)\n", speed
);
241 writel((0x0015 << I2C_TIMING2_BUS_FREE_OFFSET
) |
242 (0x000d << I2C_TIMING2_LEADIN_COUNT_OFFSET
),
243 &i2c_regs
->hw_i2c_timing2
);