4 * Copyright (c) 2004 Texas Instruments
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
25 #include <asm/arch/i2c.h>
28 #include "omap24xx_i2c.h"
30 DECLARE_GLOBAL_DATA_PTR
;
32 #define I2C_TIMEOUT 1000
34 static void wait_for_bb(void);
35 static u16
wait_for_pin(void);
36 static void flush_fifo(void);
38 static struct i2c
*i2c_base
= (struct i2c
*)I2C_DEFAULT_BASE
;
40 static unsigned int bus_initialized
[I2C_BUS_MAX
];
41 static unsigned int current_bus
;
43 void i2c_init(int speed
, int slaveadd
)
45 int psc
, fsscll
, fssclh
;
46 int hsscll
= 0, hssclh
= 0;
48 int timeout
= I2C_TIMEOUT
;
50 /* Only handle standard, fast and high speeds */
51 if ((speed
!= OMAP_I2C_STANDARD
) &&
52 (speed
!= OMAP_I2C_FAST_MODE
) &&
53 (speed
!= OMAP_I2C_HIGH_SPEED
)) {
54 printf("Error : I2C unsupported speed %d\n", speed
);
58 psc
= I2C_IP_CLK
/ I2C_INTERNAL_SAMPLING_CLK
;
60 if (psc
< I2C_PSC_MIN
) {
61 printf("Error : I2C unsupported prescalar %d\n", psc
);
65 if (speed
== OMAP_I2C_HIGH_SPEED
) {
68 /* For first phase of HS mode */
69 fsscll
= fssclh
= I2C_INTERNAL_SAMPLING_CLK
/
70 (2 * OMAP_I2C_FAST_MODE
);
72 fsscll
-= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
;
73 fssclh
-= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
;
74 if (((fsscll
< 0) || (fssclh
< 0)) ||
75 ((fsscll
> 255) || (fssclh
> 255))) {
76 puts("Error : I2C initializing first phase clock\n");
80 /* For second phase of HS mode */
81 hsscll
= hssclh
= I2C_INTERNAL_SAMPLING_CLK
/ (2 * speed
);
83 hsscll
-= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
;
84 hssclh
-= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
;
85 if (((fsscll
< 0) || (fssclh
< 0)) ||
86 ((fsscll
> 255) || (fssclh
> 255))) {
87 puts("Error : I2C initializing second phase clock\n");
91 scll
= (unsigned int)hsscll
<< 8 | (unsigned int)fsscll
;
92 sclh
= (unsigned int)hssclh
<< 8 | (unsigned int)fssclh
;
95 /* Standard and fast speed */
96 fsscll
= fssclh
= I2C_INTERNAL_SAMPLING_CLK
/ (2 * speed
);
98 fsscll
-= I2C_FASTSPEED_SCLL_TRIM
;
99 fssclh
-= I2C_FASTSPEED_SCLH_TRIM
;
100 if (((fsscll
< 0) || (fssclh
< 0)) ||
101 ((fsscll
> 255) || (fssclh
> 255))) {
102 puts("Error : I2C initializing clock\n");
106 scll
= (unsigned int)fsscll
;
107 sclh
= (unsigned int)fssclh
;
110 if (readw(&i2c_base
->con
) & I2C_CON_EN
) {
111 writew(0, &i2c_base
->con
);
115 writew(0x2, &i2c_base
->sysc
); /* for ES2 after soft reset */
118 writew(I2C_CON_EN
, &i2c_base
->con
);
119 while (!(readw(&i2c_base
->syss
) & I2C_SYSS_RDONE
) && timeout
--) {
121 puts("ERROR: Timeout in soft-reset\n");
127 writew(0, &i2c_base
->con
);
128 writew(psc
, &i2c_base
->psc
);
129 writew(scll
, &i2c_base
->scll
);
130 writew(sclh
, &i2c_base
->sclh
);
133 writew(slaveadd
, &i2c_base
->oa
);
134 writew(I2C_CON_EN
, &i2c_base
->con
);
136 /* have to enable intrrupts or OMAP i2c module doesn't work */
137 writew(I2C_IE_XRDY_IE
| I2C_IE_RRDY_IE
| I2C_IE_ARDY_IE
|
138 I2C_IE_NACK_IE
| I2C_IE_AL_IE
, &i2c_base
->ie
);
141 writew(0xFFFF, &i2c_base
->stat
);
142 writew(0, &i2c_base
->cnt
);
144 if (gd
->flags
& GD_FLG_RELOC
)
145 bus_initialized
[current_bus
] = 1;
148 static int i2c_read_byte(u8 devaddr
, u8 regoffset
, u8
*value
)
153 /* wait until bus not busy */
157 writew(1, &i2c_base
->cnt
);
158 /* set slave address */
159 writew(devaddr
, &i2c_base
->sa
);
160 /* no stop bit needed here */
161 writew(I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
|
162 I2C_CON_TRX
, &i2c_base
->con
);
164 /* send register offset */
166 status
= wait_for_pin();
167 if (status
== 0 || status
& I2C_STAT_NACK
) {
171 if (status
& I2C_STAT_XRDY
) {
172 /* Important: have to use byte access */
173 writeb(regoffset
, &i2c_base
->data
);
174 writew(I2C_STAT_XRDY
, &i2c_base
->stat
);
176 if (status
& I2C_STAT_ARDY
) {
177 writew(I2C_STAT_ARDY
, &i2c_base
->stat
);
182 /* set slave address */
183 writew(devaddr
, &i2c_base
->sa
);
184 /* read one byte from slave */
185 writew(1, &i2c_base
->cnt
);
186 /* need stop bit here */
187 writew(I2C_CON_EN
| I2C_CON_MST
|
188 I2C_CON_STT
| I2C_CON_STP
,
193 status
= wait_for_pin();
194 if (status
== 0 || status
& I2C_STAT_NACK
) {
198 if (status
& I2C_STAT_RRDY
) {
199 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
200 defined(CONFIG_OMAP44XX)
201 *value
= readb(&i2c_base
->data
);
203 *value
= readw(&i2c_base
->data
);
205 writew(I2C_STAT_RRDY
, &i2c_base
->stat
);
207 if (status
& I2C_STAT_ARDY
) {
208 writew(I2C_STAT_ARDY
, &i2c_base
->stat
);
215 writew(0xFFFF, &i2c_base
->stat
);
216 writew(0, &i2c_base
->cnt
);
220 static void flush_fifo(void)
223 /* note: if you try and read data when its not there or ready
224 * you get a bus error
227 stat
= readw(&i2c_base
->stat
);
228 if (stat
== I2C_STAT_RRDY
) {
229 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
230 defined(CONFIG_OMAP44XX)
231 readb(&i2c_base
->data
);
233 readw(&i2c_base
->data
);
235 writew(I2C_STAT_RRDY
, &i2c_base
->stat
);
242 int i2c_probe(uchar chip
)
245 int res
= 1; /* default = fail */
247 if (chip
== readw(&i2c_base
->oa
))
250 /* wait until bus not busy */
253 /* try to write one byte */
254 writew(1, &i2c_base
->cnt
);
255 /* set slave address */
256 writew(chip
, &i2c_base
->sa
);
257 /* stop bit needed here */
258 writew(I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_TRX
|
259 I2C_CON_STP
, &i2c_base
->con
);
261 status
= wait_for_pin();
263 /* check for ACK (!NAK) */
264 if (!(status
& I2C_STAT_NACK
))
267 /* abort transfer (force idle state) */
268 writew(0, &i2c_base
->con
);
271 /* don't allow any more data in... we don't want it. */
272 writew(0, &i2c_base
->cnt
);
273 writew(0xFFFF, &i2c_base
->stat
);
277 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
282 printf("I2C read: addr len %d not supported\n", alen
);
286 if (addr
+ len
> 256) {
287 puts("I2C read: address out of range\n");
291 for (i
= 0; i
< len
; i
++) {
292 if (i2c_read_byte(chip
, addr
+ i
, &buffer
[i
])) {
293 puts("I2C read: I/O error\n");
294 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
302 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
*buffer
, int len
)
309 printf("I2C write: addr len %d not supported\n", alen
);
313 if (addr
+ len
> 256) {
314 printf("I2C write: address 0x%x + 0x%x out of range\n",
319 /* wait until bus not busy */
322 /* start address phase - will write regoffset + len bytes data */
323 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
324 writew(alen
+ len
, &i2c_base
->cnt
);
325 /* set slave address */
326 writew(chip
, &i2c_base
->sa
);
327 /* stop bit needed here */
328 writew(I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STT
| I2C_CON_TRX
|
329 I2C_CON_STP
, &i2c_base
->con
);
331 /* Send address byte */
332 status
= wait_for_pin();
334 if (status
== 0 || status
& I2C_STAT_NACK
) {
336 printf("error waiting for i2c address ACK (status=0x%x)\n",
341 if (status
& I2C_STAT_XRDY
) {
342 writeb(addr
& 0xFF, &i2c_base
->data
);
343 writew(I2C_STAT_XRDY
, &i2c_base
->stat
);
346 printf("i2c bus not ready for transmit (status=0x%x)\n",
351 /* address phase is over, now write data */
352 for (i
= 0; i
< len
; i
++) {
353 status
= wait_for_pin();
355 if (status
== 0 || status
& I2C_STAT_NACK
) {
357 printf("i2c error waiting for data ACK (status=0x%x)\n",
362 if (status
& I2C_STAT_XRDY
) {
363 writeb(buffer
[i
], &i2c_base
->data
);
364 writew(I2C_STAT_XRDY
, &i2c_base
->stat
);
367 printf("i2c bus not ready for Tx (i=%d)\n", i
);
374 writew(0xFFFF, &i2c_base
->stat
);
378 static void wait_for_bb(void)
380 int timeout
= I2C_TIMEOUT
;
383 writew(0xFFFF, &i2c_base
->stat
); /* clear current interrupts...*/
384 while ((stat
= readw(&i2c_base
->stat
) & I2C_STAT_BB
) && timeout
--) {
385 writew(stat
, &i2c_base
->stat
);
390 printf("timed out in wait_for_bb: I2C_STAT=%x\n",
391 readw(&i2c_base
->stat
));
393 writew(0xFFFF, &i2c_base
->stat
); /* clear delayed stuff*/
396 static u16
wait_for_pin(void)
399 int timeout
= I2C_TIMEOUT
;
403 status
= readw(&i2c_base
->stat
);
405 (I2C_STAT_ROVR
| I2C_STAT_XUDF
| I2C_STAT_XRDY
|
406 I2C_STAT_RRDY
| I2C_STAT_ARDY
| I2C_STAT_NACK
|
407 I2C_STAT_AL
)) && timeout
--);
410 printf("timed out in wait_for_pin: I2C_STAT=%x\n",
411 readw(&i2c_base
->stat
));
412 writew(0xFFFF, &i2c_base
->stat
);
419 int i2c_set_bus_num(unsigned int bus
)
421 if ((bus
< 0) || (bus
>= I2C_BUS_MAX
)) {
422 printf("Bad bus: %d\n", bus
);
428 i2c_base
= (struct i2c
*)I2C_BASE3
;
432 i2c_base
= (struct i2c
*)I2C_BASE2
;
434 i2c_base
= (struct i2c
*)I2C_BASE1
;
438 if (!bus_initialized
[current_bus
])
439 i2c_init(CONFIG_SYS_I2C_SPEED
, CONFIG_SYS_I2C_SLAVE
);
444 int i2c_get_bus_num(void)
446 return (int) current_bus
;