drivers/i2c/omap24xx_i2c.c

   1 /*
   2  * Basic I2C functions
   3  *
   4  * Copyright (c) 2004 Texas Instruments
   5  *
   6  * This package is free software;  you can redistribute it and/or
   7  * modify it under the terms of the license found in the file
   8  * named COPYING that should have accompanied this file.
   9  *
  10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13  *
  14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15  *
  16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17  * Rewritten to fit into the current U-Boot framework
  18  *
  19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20  *
  21  */
  22
  23 #include <common.h>
  24
  25 #include <asm/arch/i2c.h>
  26 #include <asm/io.h>
  27
  28 #include "omap24xx_i2c.h"
  29
  30 static void wait_for_bb (void);
  31 static u16 wait_for_pin (void);
  32 static void flush_fifo(void);
  33
  34 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
  35
  36 static unsigned int bus_initialized[I2C_BUS_MAX];
  37 static unsigned int current_bus;
  38
  39 void i2c_init (int speed, int slaveadd)
  40 {
  41         int psc, fsscll, fssclh;
  42         int hsscll = 0, hssclh = 0;
  43         u32 scll, sclh;
  44
  45         /* Only handle standard, fast and high speeds */
  46         if ((speed != OMAP_I2C_STANDARD) &&
  47             (speed != OMAP_I2C_FAST_MODE) &&
  48             (speed != OMAP_I2C_HIGH_SPEED)) {
  49                 printf("Error : I2C unsupported speed %d\n", speed);
  50                 return;
  51         }
  52
  53         psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
  54         psc -= 1;
  55         if (psc < I2C_PSC_MIN) {
  56                 printf("Error : I2C unsupported prescalar %d\n", psc);
  57                 return;
  58         }
  59
  60         if (speed == OMAP_I2C_HIGH_SPEED) {
  61                 /* High speed */
  62
  63                 /* For first phase of HS mode */
  64                 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
  65                         (2 * OMAP_I2C_FAST_MODE);
  66
  67                 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
  68                 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
  69                 if (((fsscll < 0) || (fssclh < 0)) ||
  70                     ((fsscll > 255) || (fssclh > 255))) {
  71                         printf("Error : I2C initializing first phase clock\n");
  72                         return;
  73                 }
  74
  75                 /* For second phase of HS mode */
  76                 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  77
  78                 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
  79                 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
  80                 if (((fsscll < 0) || (fssclh < 0)) ||
  81                     ((fsscll > 255) || (fssclh > 255))) {
  82                         printf("Error : I2C initializing second phase clock\n");
  83                         return;
  84                 }
  85
  86                 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
  87                 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
  88
  89         } else {
  90                 /* Standard and fast speed */
  91                 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  92
  93                 fsscll -= I2C_FASTSPEED_SCLL_TRIM;
  94                 fssclh -= I2C_FASTSPEED_SCLH_TRIM;
  95                 if (((fsscll < 0) || (fssclh < 0)) ||
  96                     ((fsscll > 255) || (fssclh > 255))) {
  97                         printf("Error : I2C initializing clock\n");
  98                         return;
  99                 }
 100
 101                 scll = (unsigned int)fsscll;
 102                 sclh = (unsigned int)fssclh;
 103         }
 104
 105         writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
 106         udelay(1000);
 107         writew(0x0, &i2c_base->sysc); /* will probably self clear but */
 108
 109         if (readw (&i2c_base->con) & I2C_CON_EN) {
 110                 writew (0, &i2c_base->con);
 111                 udelay (50000);
 112         }
 113
 114         writew(psc, &i2c_base->psc);
 115         writew(scll, &i2c_base->scll);
 116         writew(sclh, &i2c_base->sclh);
 117
 118         /* own address */
 119         writew (slaveadd, &i2c_base->oa);
 120         writew (I2C_CON_EN, &i2c_base->con);
 121
 122         /* have to enable intrrupts or OMAP i2c module doesn't work */
 123         writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
 124                 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
 125         udelay (1000);
 126         flush_fifo();
 127         writew (0xFFFF, &i2c_base->stat);
 128         writew (0, &i2c_base->cnt);
 129
 130         bus_initialized[current_bus] = 1;
 131 }
 132
 133 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
 134 {
 135         int i2c_error = 0;
 136         u16 status;
 137
 138         /* wait until bus not busy */
 139         wait_for_bb ();
 140
 141         /* one byte only */
 142         writew (1, &i2c_base->cnt);
 143         /* set slave address */
 144         writew (devaddr, &i2c_base->sa);
 145         /* no stop bit needed here */
 146         writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
 147
 148         status = wait_for_pin ();
 149
 150         if (status & I2C_STAT_XRDY) {
 151                 /* Important: have to use byte access */
 152                 writeb (regoffset, &i2c_base->data);
 153                 udelay (20000);
 154                 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
 155                         i2c_error = 1;
 156                 }
 157         } else {
 158                 i2c_error = 1;
 159         }
 160
 161         if (!i2c_error) {
 162                 /* free bus, otherwise we can't use a combined transction */
 163                 writew (0, &i2c_base->con);
 164                 while (readw (&i2c_base->stat) || (readw (&i2c_base->con) & I2C_CON_MST)) {
 165                         udelay (10000);
 166                         /* Have to clear pending interrupt to clear I2C_STAT */
 167                         writew (0xFFFF, &i2c_base->stat);
 168                 }
 169
 170                 wait_for_bb ();
 171                 /* set slave address */
 172                 writew (devaddr, &i2c_base->sa);
 173                 /* read one byte from slave */
 174                 writew (1, &i2c_base->cnt);
 175                 /* need stop bit here */
 176                 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP,
 177                         &i2c_base->con);
 178
 179                 status = wait_for_pin ();
 180                 if (status & I2C_STAT_RRDY) {
 181 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
 182     defined(CONFIG_OMAP44XX)
 183                         *value = readb (&i2c_base->data);
 184 #else
 185                         *value = readw (&i2c_base->data);
 186 #endif
 187                         udelay (20000);
 188                 } else {
 189                         i2c_error = 1;
 190                 }
 191
 192                 if (!i2c_error) {
 193                         writew (I2C_CON_EN, &i2c_base->con);
 194                         while (readw (&i2c_base->stat)
 195                                || (readw (&i2c_base->con) & I2C_CON_MST)) {
 196                                 udelay (10000);
 197                                 writew (0xFFFF, &i2c_base->stat);
 198                         }
 199                 }
 200         }
 201         flush_fifo();
 202         writew (0xFFFF, &i2c_base->stat);
 203         writew (0, &i2c_base->cnt);
 204         return i2c_error;
 205 }
 206
 207 static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
 208 {
 209         int i2c_error = 0;
 210         u16 status, stat;
 211
 212         /* wait until bus not busy */
 213         wait_for_bb ();
 214
 215         /* two bytes */
 216         writew (2, &i2c_base->cnt);
 217         /* set slave address */
 218         writew (devaddr, &i2c_base->sa);
 219         /* stop bit needed here */
 220         writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
 221                 I2C_CON_STP, &i2c_base->con);
 222
 223         /* wait until state change */
 224         status = wait_for_pin ();
 225
 226         if (status & I2C_STAT_XRDY) {
 227 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
 228     defined(CONFIG_OMAP44XX)
 229                 /* send out 1 byte */
 230                 writeb (regoffset, &i2c_base->data);
 231                 writew (I2C_STAT_XRDY, &i2c_base->stat);
 232
 233                 status = wait_for_pin ();
 234                 if ((status & I2C_STAT_XRDY)) {
 235                         /* send out next 1 byte */
 236                         writeb (value, &i2c_base->data);
 237                         writew (I2C_STAT_XRDY, &i2c_base->stat);
 238                 } else {
 239                         i2c_error = 1;
 240                 }
 241 #else
 242                 /* send out two bytes */
 243                 writew ((value << 8) + regoffset, &i2c_base->data);
 244 #endif
 245                 /* must have enough delay to allow BB bit to go low */
 246                 udelay (50000);
 247                 if (readw (&i2c_base->stat) & I2C_STAT_NACK) {
 248                         i2c_error = 1;
 249                 }
 250         } else {
 251                 i2c_error = 1;
 252         }
 253
 254         if (!i2c_error) {
 255                 int eout = 200;
 256
 257                 writew (I2C_CON_EN, &i2c_base->con);
 258                 while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) {
 259                         udelay (1000);
 260                         /* have to read to clear intrrupt */
 261                         writew (0xFFFF, &i2c_base->stat);
 262                         if(--eout == 0) /* better leave with error than hang */
 263                                 break;
 264                 }
 265         }
 266         flush_fifo();
 267         writew (0xFFFF, &i2c_base->stat);
 268         writew (0, &i2c_base->cnt);
 269         return i2c_error;
 270 }
 271
 272 static void flush_fifo(void)
 273 {       u16 stat;
 274
 275         /* note: if you try and read data when its not there or ready
 276          * you get a bus error
 277          */
 278         while(1){
 279                 stat = readw(&i2c_base->stat);
 280                 if(stat == I2C_STAT_RRDY){
 281 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
 282     defined(CONFIG_OMAP44XX)
 283                         readb(&i2c_base->data);
 284 #else
 285                         readw(&i2c_base->data);
 286 #endif
 287                         writew(I2C_STAT_RRDY,&i2c_base->stat);
 288                         udelay(1000);
 289                 }else
 290                         break;
 291         }
 292 }
 293
 294 int i2c_probe (uchar chip)
 295 {
 296         int res = 1; /* default = fail */
 297
 298         if (chip == readw (&i2c_base->oa)) {
 299                 return res;
 300         }
 301
 302         /* wait until bus not busy */
 303         wait_for_bb ();
 304
 305         /* try to read one byte */
 306         writew (1, &i2c_base->cnt);
 307         /* set slave address */
 308         writew (chip, &i2c_base->sa);
 309         /* stop bit needed here */
 310         writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con);
 311         /* enough delay for the NACK bit set */
 312         udelay (50000);
 313
 314         if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) {
 315                 res = 0;      /* success case */
 316                 flush_fifo();
 317                 writew(0xFFFF, &i2c_base->stat);
 318         } else {
 319                 writew(0xFFFF, &i2c_base->stat);         /* failue, clear sources*/
 320                 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */
 321                 udelay(20000);
 322                 wait_for_bb ();
 323         }
 324         flush_fifo();
 325         writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
 326         writew(0xFFFF, &i2c_base->stat);
 327         return res;
 328 }
 329
 330 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
 331 {
 332         int i;
 333
 334         if (alen > 1) {
 335                 printf ("I2C read: addr len %d not supported\n", alen);
 336                 return 1;
 337         }
 338
 339         if (addr + len > 256) {
 340                 printf ("I2C read: address out of range\n");
 341                 return 1;
 342         }
 343
 344         for (i = 0; i < len; i++) {
 345                 if (i2c_read_byte (chip, addr + i, &buffer[i])) {
 346                         printf ("I2C read: I/O error\n");
 347                         i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 348                         return 1;
 349                 }
 350         }
 351
 352         return 0;
 353 }
 354
 355 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
 356 {
 357         int i;
 358
 359         if (alen > 1) {
 360                 printf ("I2C read: addr len %d not supported\n", alen);
 361                 return 1;
 362         }
 363
 364         if (addr + len > 256) {
 365                 printf ("I2C read: address out of range\n");
 366                 return 1;
 367         }
 368
 369         for (i = 0; i < len; i++) {
 370                 if (i2c_write_byte (chip, addr + i, buffer[i])) {
 371                         printf ("I2C read: I/O error\n");
 372                         i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 373                         return 1;
 374                 }
 375         }
 376
 377         return 0;
 378 }
 379
 380 static void wait_for_bb (void)
 381 {
 382         int timeout = 10;
 383         u16 stat;
 384
 385         writew(0xFFFF, &i2c_base->stat);         /* clear current interruts...*/
 386         while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
 387                 writew (stat, &i2c_base->stat);
 388                 udelay (50000);
 389         }
 390
 391         if (timeout <= 0) {
 392                 printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
 393                         readw (&i2c_base->stat));
 394         }
 395         writew(0xFFFF, &i2c_base->stat);         /* clear delayed stuff*/
 396 }
 397
 398 static u16 wait_for_pin (void)
 399 {
 400         u16 status;
 401         int timeout = 10;
 402
 403         do {
 404                 udelay (1000);
 405                 status = readw (&i2c_base->stat);
 406         } while (  !(status &
 407                    (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
 408                     I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
 409                     I2C_STAT_AL)) && timeout--);
 410
 411         if (timeout <= 0) {
 412                 printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
 413                         readw (&i2c_base->stat));
 414                         writew(0xFFFF, &i2c_base->stat);
 415 }
 416         return status;
 417 }
 418
 419 int i2c_set_bus_num(unsigned int bus)
 420 {
 421         if ((bus < 0) || (bus >= I2C_BUS_MAX)) {
 422                 printf("Bad bus: %d\n", bus);
 423                 return -1;
 424         }
 425
 426 #if I2C_BUS_MAX==3
 427         if (bus == 2)
 428                 i2c_base = (struct i2c *)I2C_BASE3;
 429         else
 430 #endif
 431         if (bus == 1)
 432                 i2c_base = (struct i2c *)I2C_BASE2;
 433         else
 434                 i2c_base = (struct i2c *)I2C_BASE1;
 435
 436         current_bus = bus;
 437
 438         if(!bus_initialized[current_bus])
 439                 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 440
 441         return 0;
 442 }
 443
 444 int i2c_get_bus_num(void)
 445 {
 446         return (int) current_bus;
 447 }
 448