drivers/i2c/omap24xx_i2c.h

   1 /*
   2  * (C) Copyright 2004-2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #ifndef _OMAP2PLUS_I2C_H_
   8 #define _OMAP2PLUS_I2C_H_
   9
  10 /* I2C masks */
  11
  12 /* I2C Interrupt Enable Register (I2C_IE): */
  13 #define I2C_IE_GC_IE    (1 << 5)
  14 #define I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
  15 #define I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
  16 #define I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
  17 #define I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
  18 #define I2C_IE_AL_IE    (1 << 0) /* Arbitration lost interrupt enable */
  19
  20 /* I2C Status Register (I2C_STAT): */
  21
  22 #define I2C_STAT_SBD    (1 << 15) /* Single byte data */
  23 #define I2C_STAT_BB     (1 << 12) /* Bus busy */
  24 #define I2C_STAT_ROVR   (1 << 11) /* Receive overrun */
  25 #define I2C_STAT_XUDF   (1 << 10) /* Transmit underflow */
  26 #define I2C_STAT_AAS    (1 << 9)  /* Address as slave */
  27 #define I2C_STAT_GC     (1 << 5)
  28 #define I2C_STAT_XRDY   (1 << 4)  /* Transmit data ready */
  29 #define I2C_STAT_RRDY   (1 << 3)  /* Receive data ready */
  30 #define I2C_STAT_ARDY   (1 << 2)  /* Register access ready */
  31 #define I2C_STAT_NACK   (1 << 1)  /* No acknowledgment interrupt enable */
  32 #define I2C_STAT_AL     (1 << 0)  /* Arbitration lost interrupt enable */
  33
  34 /* I2C Interrupt Code Register (I2C_INTCODE): */
  35
  36 #define I2C_INTCODE_MASK        7
  37 #define I2C_INTCODE_NONE        0
  38 #define I2C_INTCODE_AL          1       /* Arbitration lost */
  39 #define I2C_INTCODE_NAK         2       /* No acknowledgement/general call */
  40 #define I2C_INTCODE_ARDY        3       /* Register access ready */
  41 #define I2C_INTCODE_RRDY        4       /* Rcv data ready */
  42 #define I2C_INTCODE_XRDY        5       /* Xmit data ready */
  43
  44 /* I2C Buffer Configuration Register (I2C_BUF): */
  45
  46 #define I2C_BUF_RDMA_EN         (1 << 15) /* Receive DMA channel enable */
  47 #define I2C_BUF_XDMA_EN         (1 << 7)  /* Transmit DMA channel enable */
  48
  49 /* I2C Configuration Register (I2C_CON): */
  50
  51 #define I2C_CON_EN      (1 << 15)  /* I2C module enable */
  52 #define I2C_CON_BE      (1 << 14)  /* Big endian mode */
  53 #define I2C_CON_STB     (1 << 11)  /* Start byte mode (master mode only) */
  54 #define I2C_CON_MST     (1 << 10)  /* Master/slave mode */
  55 #define I2C_CON_TRX     (1 << 9)   /* Transmitter/receiver mode */
  56                                    /* (master mode only) */
  57 #define I2C_CON_XA      (1 << 8)   /* Expand address */
  58 #define I2C_CON_STP     (1 << 1)   /* Stop condition (master mode only) */
  59 #define I2C_CON_STT     (1 << 0)   /* Start condition (master mode only) */
  60
  61 /* I2C System Test Register (I2C_SYSTEST): */
  62
  63 #define I2C_SYSTEST_ST_EN       (1 << 15) /* System test enable */
  64 #define I2C_SYSTEST_FREE        (1 << 14) /* Free running mode, on brkpoint) */
  65 #define I2C_SYSTEST_TMODE_MASK  (3 << 12) /* Test mode select */
  66 #define I2C_SYSTEST_TMODE_SHIFT (12)      /* Test mode select */
  67 #define I2C_SYSTEST_SCL_I       (1 << 3)  /* SCL line sense input value */
  68 #define I2C_SYSTEST_SCL_O       (1 << 2)  /* SCL line drive output value */
  69 #define I2C_SYSTEST_SDA_I       (1 << 1)  /* SDA line sense input value */
  70 #define I2C_SYSTEST_SDA_O       (1 << 0)  /* SDA line drive output value */
  71
  72 /* I2C System Status Register (I2C_SYSS): */
  73
  74 #define I2C_SYSS_RDONE          (1 << 0)  /* Internel reset monitoring */
  75
  76 #define I2C_SCLL_SCLL           0
  77 #define I2C_SCLL_SCLL_M         0xFF
  78 #define I2C_SCLL_HSSCLL         8
  79 #define I2C_SCLH_HSSCLL_M       0xFF
  80 #define I2C_SCLH_SCLH           0
  81 #define I2C_SCLH_SCLH_M         0xFF
  82 #define I2C_SCLH_HSSCLH         8
  83 #define I2C_SCLH_HSSCLH_M       0xFF
  84
  85 #define OMAP_I2C_STANDARD       100000
  86 #define OMAP_I2C_FAST_MODE      400000
  87 #define OMAP_I2C_HIGH_SPEED     3400000
  88
  89 #define SYSTEM_CLOCK_12         12000000
  90 #define SYSTEM_CLOCK_13         13000000
  91 #define SYSTEM_CLOCK_192        19200000
  92 #define SYSTEM_CLOCK_96         96000000
  93
  94 /* Use the reference value of 96MHz if not explicitly set by the board */
  95 #ifndef I2C_IP_CLK
  96 #define I2C_IP_CLK              SYSTEM_CLOCK_96
  97 #endif
  98
  99 /*
 100  * The reference minimum clock for high speed is 19.2MHz.
 101  * The linux 2.6.30 kernel uses this value.
 102  * The reference minimum clock for fast mode is 9.6MHz
 103  * The reference minimum clock for standard mode is 4MHz
 104  * In TRM, the value of 12MHz is used.
 105  */
 106 #ifndef I2C_INTERNAL_SAMPLING_CLK
 107 #define I2C_INTERNAL_SAMPLING_CLK       19200000
 108 #endif
 109
 110 /*
 111  * The equation for the low and high time is
 112  * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
 113  * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
 114  *
 115  * If the duty cycle is 50%
 116  *
 117  * tlow = scll + scll_trim = sampling clock / (2 * speed)
 118  * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
 119  *
 120  * In TRM
 121  * scll_trim = 7
 122  * sclh_trim = 5
 123  *
 124  * The linux 4.9 kernel uses
 125  * scll_trim = 7
 126  * sclh_trim = 5
 127  *
 128  * These are the trim values for standard and fast speed
 129  */
 130 #ifndef I2C_FASTSPEED_SCLL_TRIM
 131 #define I2C_FASTSPEED_SCLL_TRIM         7
 132 #endif
 133 #ifndef I2C_FASTSPEED_SCLH_TRIM
 134 #define I2C_FASTSPEED_SCLH_TRIM         5
 135 #endif
 136
 137 /* These are the trim values for high speed */
 138 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
 139 #define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM       I2C_FASTSPEED_SCLL_TRIM
 140 #endif
 141 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
 142 #define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM       I2C_FASTSPEED_SCLH_TRIM
 143 #endif
 144 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
 145 #define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM       I2C_FASTSPEED_SCLL_TRIM
 146 #endif
 147 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
 148 #define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM       I2C_FASTSPEED_SCLH_TRIM
 149 #endif
 150
 151 #define I2C_PSC_MAX             0x0f
 152 #define I2C_PSC_MIN             0x00
 153
 154 #endif /* _OMAP24XX_I2C_H_ */