drivers/i2c/ppc4xx_i2c.c

   1 /*
   2  * (C) Copyright 2007-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
   6  *
   7  * (C) Copyright 2001
   8  * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/ppc4xx.h>
  15 #include <asm/ppc4xx-i2c.h>
  16 #include <i2c.h>
  17 #include <asm/io.h>
  18
  19 #ifdef CONFIG_HARD_I2C
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if defined(CONFIG_I2C_MULTI_BUS)
  24 /*
  25  * Initialize the bus pointer to whatever one the SPD EEPROM is on.
  26  * Default is bus 0.  This is necessary because the DDR initialization
  27  * runs from ROM, and we can't switch buses because we can't modify
  28  * the global variables.
  29  */
  30 #ifndef CONFIG_SYS_SPD_BUS_NUM
  31 #define CONFIG_SYS_SPD_BUS_NUM  0
  32 #endif
  33 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) =
  34         CONFIG_SYS_SPD_BUS_NUM;
  35 #endif /* CONFIG_I2C_MULTI_BUS */
  36
  37 static void _i2c_bus_reset(void)
  38 {
  39         struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
  40         int i;
  41         u8 dc;
  42
  43         /* Reset status register */
  44         /* write 1 in SCMP and IRQA to clear these fields */
  45         out_8(&i2c->sts, 0x0A);
  46
  47         /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
  48         out_8(&i2c->extsts, 0x8F);
  49
  50         /* Place chip in the reset state */
  51         out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
  52
  53         /* Check if bus is free */
  54         dc = in_8(&i2c->directcntl);
  55         if (!DIRCTNL_FREE(dc)){
  56                 /* Try to set bus free state */
  57                 out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
  58
  59                 /* Wait until we regain bus control */
  60                 for (i = 0; i < 100; ++i) {
  61                         dc = in_8(&i2c->directcntl);
  62                         if (DIRCTNL_FREE(dc))
  63                                 break;
  64
  65                         /* Toggle SCL line */
  66                         dc ^= IIC_DIRCNTL_SCC;
  67                         out_8(&i2c->directcntl, dc);
  68                         udelay(10);
  69                         dc ^= IIC_DIRCNTL_SCC;
  70                         out_8(&i2c->directcntl, dc);
  71                 }
  72         }
  73
  74         /* Remove reset */
  75         out_8(&i2c->xtcntlss, 0);
  76 }
  77
  78 void i2c_init(int speed, int slaveaddr)
  79 {
  80         struct ppc4xx_i2c *i2c;
  81         int val, divisor;
  82         int bus;
  83
  84 #ifdef CONFIG_SYS_I2C_INIT_BOARD
  85         /*
  86          * Call board specific i2c bus reset routine before accessing the
  87          * environment, which might be in a chip on that bus. For details
  88          * about this problem see doc/I2C_Edge_Conditions.
  89          */
  90         i2c_init_board();
  91 #endif
  92
  93         for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
  94                 I2C_SET_BUS(bus);
  95
  96                 /* Set i2c pointer after calling I2C_SET_BUS() */
  97                 i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
  98
  99                 /* Handle possible failed I2C state */
 100                 /* FIXME: put this into i2c_init_board()? */
 101                 _i2c_bus_reset();
 102
 103                 /* clear lo master address */
 104                 out_8(&i2c->lmadr, 0);
 105
 106                 /* clear hi master address */
 107                 out_8(&i2c->hmadr, 0);
 108
 109                 /* clear lo slave address */
 110                 out_8(&i2c->lsadr, 0);
 111
 112                 /* clear hi slave address */
 113                 out_8(&i2c->hsadr, 0);
 114
 115                 /* Clock divide Register */
 116                 /* set divisor according to freq_opb */
 117                 divisor = (get_OPB_freq() - 1) / 10000000;
 118                 if (divisor == 0)
 119                         divisor = 1;
 120                 out_8(&i2c->clkdiv, divisor);
 121
 122                 /* no interrupts */
 123                 out_8(&i2c->intrmsk, 0);
 124
 125                 /* clear transfer count */
 126                 out_8(&i2c->xfrcnt, 0);
 127
 128                 /* clear extended control & stat */
 129                 /* write 1 in SRC SRS SWC SWS to clear these fields */
 130                 out_8(&i2c->xtcntlss, 0xF0);
 131
 132                 /* Mode Control Register
 133                    Flush Slave/Master data buffer */
 134                 out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 135
 136                 val = in_8(&i2c->mdcntl);
 137
 138                 /* Ignore General Call, slave transfers are ignored,
 139                  * disable interrupts, exit unknown bus state, enable hold
 140                  * SCL 100kHz normaly or FastMode for 400kHz and above
 141                  */
 142
 143                 val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
 144                 if (speed >= 400000)
 145                         val |= IIC_MDCNTL_FSM;
 146                 out_8(&i2c->mdcntl, val);
 147
 148                 /* clear control reg */
 149                 out_8(&i2c->cntl, 0x00);
 150         }
 151
 152         /* set to SPD bus as default bus upon powerup */
 153         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 154 }
 155
 156 /*
 157  * This code tries to use the features of the 405GP i2c
 158  * controller. It will transfer up to 4 bytes in one pass
 159  * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
 160  * is possible to do out16(lhz) transfers.
 161  *
 162  * cmd_type is 0 for write 1 for read.
 163  *
 164  * addr_len can take any value from 0-255, it is only limited
 165  * by the char, we could make it larger if needed. If it is
 166  * 0 we skip the address write cycle.
 167  *
 168  * Typical case is a Write of an addr followd by a Read. The
 169  * IBM FAQ does not cover this. On the last byte of the write
 170  * we don't set the creg CHT bit, and on the first bytes of the
 171  * read we set the RPST bit.
 172  *
 173  * It does not support address only transfers, there must be
 174  * a data part. If you want to write the address yourself, put
 175  * it in the data pointer.
 176  *
 177  * It does not support transfer to/from address 0.
 178  *
 179  * It does not check XFRCNT.
 180  */
 181 static int i2c_transfer(unsigned char cmd_type,
 182                         unsigned char chip,
 183                         unsigned char addr[],
 184                         unsigned char addr_len,
 185                         unsigned char data[],
 186                         unsigned short data_len)
 187 {
 188         struct ppc4xx_i2c *i2c = (struct ppc4xx_i2c *)I2C_BASE_ADDR;
 189         u8 *ptr;
 190         int reading;
 191         int tran, cnt;
 192         int result;
 193         int status;
 194         int i;
 195         u8 creg;
 196
 197         if (data == 0 || data_len == 0) {
 198                 /* Don't support data transfer of no length or to address 0 */
 199                 printf( "i2c_transfer: bad call\n" );
 200                 return IIC_NOK;
 201         }
 202         if (addr && addr_len) {
 203                 ptr = addr;
 204                 cnt = addr_len;
 205                 reading = 0;
 206         } else {
 207                 ptr = data;
 208                 cnt = data_len;
 209                 reading = cmd_type;
 210         }
 211
 212         /* Clear Stop Complete Bit */
 213         out_8(&i2c->sts, IIC_STS_SCMP);
 214
 215         /* Check init */
 216         i = 10;
 217         do {
 218                 /* Get status */
 219                 status = in_8(&i2c->sts);
 220                 i--;
 221         } while ((status & IIC_STS_PT) && (i > 0));
 222
 223         if (status & IIC_STS_PT) {
 224                 result = IIC_NOK_TOUT;
 225                 return(result);
 226         }
 227
 228         /* flush the Master/Slave Databuffers */
 229         out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
 230               IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
 231
 232         /* need to wait 4 OPB clocks? code below should take that long */
 233
 234         /* 7-bit adressing */
 235         out_8(&i2c->hmadr, 0);
 236         out_8(&i2c->lmadr, chip);
 237
 238         tran = 0;
 239         result = IIC_OK;
 240         creg = 0;
 241
 242         while (tran != cnt && (result == IIC_OK)) {
 243                 int  bc,j;
 244
 245                 /*
 246                  * Control register =
 247                  * Normal transfer, 7-bits adressing, Transfer up to
 248                  * bc bytes, Normal start, Transfer is a sequence of transfers
 249                  */
 250                 creg |= IIC_CNTL_PT;
 251
 252                 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
 253                 creg |= (bc - 1) << 4;
 254                 /* if the real cmd type is write continue trans */
 255                 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 256                         creg |= IIC_CNTL_CHT;
 257
 258                 if (reading) {
 259                         creg |= IIC_CNTL_READ;
 260                 } else {
 261                         for(j = 0; j < bc; j++) {
 262                                 /* Set buffer */
 263                                 out_8(&i2c->mdbuf, ptr[tran + j]);
 264                         }
 265                 }
 266                 out_8(&i2c->cntl, creg);
 267
 268                 /*
 269                  * Transfer is in progress
 270                  * we have to wait for upto 5 bytes of data
 271                  * 1 byte chip address+r/w bit then bc bytes
 272                  * of data.
 273                  * udelay(10) is 1 bit time at 100khz
 274                  * Doubled for slop. 20 is too small.
 275                  */
 276                 i = 2 * 5 * 8;
 277                 do {
 278                         /* Get status */
 279                         status = in_8(&i2c->sts);
 280                         udelay(10);
 281                         i--;
 282                 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
 283                          (i > 0));
 284
 285                 if (status & IIC_STS_ERR) {
 286                         result = IIC_NOK;
 287                         status = in_8(&i2c->extsts);
 288                         /* Lost arbitration? */
 289                         if (status & IIC_EXTSTS_LA)
 290                                 result = IIC_NOK_LA;
 291                         /* Incomplete transfer? */
 292                         if (status & IIC_EXTSTS_ICT)
 293                                 result = IIC_NOK_ICT;
 294                         /* Transfer aborted? */
 295                         if (status & IIC_EXTSTS_XFRA)
 296                                 result = IIC_NOK_XFRA;
 297                 } else if ( status & IIC_STS_PT) {
 298                         result = IIC_NOK_TOUT;
 299                 }
 300
 301                 /* Command is reading => get buffer */
 302                 if ((reading) && (result == IIC_OK)) {
 303                         /* Are there data in buffer */
 304                         if (status & IIC_STS_MDBS) {
 305                                 /*
 306                                  * even if we have data we have to wait 4OPB
 307                                  * clocks for it to hit the front of the FIFO,
 308                                  * after that we can just read. We should check
 309                                  * XFCNT here and if the FIFO is full there is
 310                                  * no need to wait.
 311                                  */
 312                                 udelay(1);
 313                                 for (j = 0; j < bc; j++)
 314                                         ptr[tran + j] = in_8(&i2c->mdbuf);
 315                         } else
 316                                 result = IIC_NOK_DATA;
 317                 }
 318                 creg = 0;
 319                 tran += bc;
 320                 if (ptr == addr && tran == cnt) {
 321                         ptr = data;
 322                         cnt = data_len;
 323                         tran = 0;
 324                         reading = cmd_type;
 325                         if (reading)
 326                                 creg = IIC_CNTL_RPST;
 327                 }
 328         }
 329         return result;
 330 }
 331
 332 int i2c_probe(uchar chip)
 333 {
 334         uchar buf[1];
 335
 336         buf[0] = 0;
 337
 338         /*
 339          * What is needed is to send the chip address and verify that the
 340          * address was <ACK>ed (i.e. there was a chip at that address which
 341          * drove the data line low).
 342          */
 343         return (i2c_transfer(1, chip << 1, 0, 0, buf, 1) != 0);
 344 }
 345
 346 static int ppc4xx_i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer,
 347                                int len, int read)
 348 {
 349         uchar xaddr[4];
 350         int ret;
 351
 352         if (alen > 4) {
 353                 printf("I2C: addr len %d not supported\n", alen);
 354                 return 1;
 355         }
 356
 357         if (alen > 0) {
 358                 xaddr[0] = (addr >> 24) & 0xFF;
 359                 xaddr[1] = (addr >> 16) & 0xFF;
 360                 xaddr[2] = (addr >> 8) & 0xFF;
 361                 xaddr[3] = addr & 0xFF;
 362         }
 363
 364
 365 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 366         /*
 367          * EEPROM chips that implement "address overflow" are ones
 368          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 369          * address and the extra bits end up in the "chip address"
 370          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 371          * four 256 byte chips.
 372          *
 373          * Note that we consider the length of the address field to
 374          * still be one byte because the extra address bits are
 375          * hidden in the chip address.
 376          */
 377         if (alen > 0)
 378                 chip |= ((addr >> (alen * 8)) &
 379                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 380 #endif
 381         if ((ret = i2c_transfer(read, chip << 1, &xaddr[4 - alen], alen,
 382                                 buffer, len)) != 0) {
 383                 printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
 384
 385                 return 1;
 386         }
 387
 388         return 0;
 389 }
 390
 391 int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
 392 {
 393         return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 1);
 394 }
 395
 396 int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
 397 {
 398         return ppc4xx_i2c_transfer(chip, addr, alen, buffer, len, 0);
 399 }
 400
 401 #if defined(CONFIG_I2C_MULTI_BUS)
 402 /*
 403  * Functions for multiple I2C bus handling
 404  */
 405 unsigned int i2c_get_bus_num(void)
 406 {
 407         return i2c_bus_num;
 408 }
 409
 410 int i2c_set_bus_num(unsigned int bus)
 411 {
 412         if (bus >= CONFIG_SYS_MAX_I2C_BUS)
 413                 return -1;
 414
 415         i2c_bus_num = bus;
 416
 417         return 0;
 418 }
 419 #endif  /* CONFIG_I2C_MULTI_BUS */
 420 #endif  /* CONFIG_HARD_I2C */