2 * (C) Copyright 2007-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/ppc4xx.h>
31 #include <asm/ppc4xx-i2c.h>
35 DECLARE_GLOBAL_DATA_PTR
;
37 static inline struct ppc4xx_i2c
*ppc4xx_get_i2c(int hwadapnr
)
41 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
42 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
43 defined(CONFIG_460EX) || defined(CONFIG_460GT)
44 base
= CONFIG_SYS_PERIPHERAL_BASE
+ 0x00000700 + (hwadapnr
* 0x100);
45 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
46 /* all remaining 440 variants */
47 base
= CONFIG_SYS_PERIPHERAL_BASE
+ 0x00000400 + (hwadapnr
* 0x100);
49 /* all 405 variants */
50 base
= 0xEF600500 + (hwadapnr
* 0x100);
52 return (struct ppc4xx_i2c
*)base
;
55 static void _i2c_bus_reset(struct i2c_adapter
*adap
)
57 struct ppc4xx_i2c
*i2c
= ppc4xx_get_i2c(adap
->hwadapnr
);
61 /* Reset status register */
62 /* write 1 in SCMP and IRQA to clear these fields */
63 out_8(&i2c
->sts
, 0x0A);
65 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
66 out_8(&i2c
->extsts
, 0x8F);
68 /* Place chip in the reset state */
69 out_8(&i2c
->xtcntlss
, IIC_XTCNTLSS_SRST
);
71 /* Check if bus is free */
72 dc
= in_8(&i2c
->directcntl
);
73 if (!DIRCTNL_FREE(dc
)){
74 /* Try to set bus free state */
75 out_8(&i2c
->directcntl
, IIC_DIRCNTL_SDAC
| IIC_DIRCNTL_SCC
);
77 /* Wait until we regain bus control */
78 for (i
= 0; i
< 100; ++i
) {
79 dc
= in_8(&i2c
->directcntl
);
84 dc
^= IIC_DIRCNTL_SCC
;
85 out_8(&i2c
->directcntl
, dc
);
87 dc
^= IIC_DIRCNTL_SCC
;
88 out_8(&i2c
->directcntl
, dc
);
93 out_8(&i2c
->xtcntlss
, 0);
96 static void ppc4xx_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveaddr
)
98 struct ppc4xx_i2c
*i2c
= ppc4xx_get_i2c(adap
->hwadapnr
);
101 #ifdef CONFIG_SYS_I2C_INIT_BOARD
103 * Call board specific i2c bus reset routine before accessing the
104 * environment, which might be in a chip on that bus. For details
105 * about this problem see doc/I2C_Edge_Conditions.
110 /* Handle possible failed I2C state */
111 /* FIXME: put this into i2c_init_board()? */
112 _i2c_bus_reset(adap
);
114 /* clear lo master address */
115 out_8(&i2c
->lmadr
, 0);
117 /* clear hi master address */
118 out_8(&i2c
->hmadr
, 0);
120 /* clear lo slave address */
121 out_8(&i2c
->lsadr
, 0);
123 /* clear hi slave address */
124 out_8(&i2c
->hsadr
, 0);
126 /* Clock divide Register */
127 /* set divisor according to freq_opb */
128 divisor
= (get_OPB_freq() - 1) / 10000000;
131 out_8(&i2c
->clkdiv
, divisor
);
134 out_8(&i2c
->intrmsk
, 0);
136 /* clear transfer count */
137 out_8(&i2c
->xfrcnt
, 0);
139 /* clear extended control & stat */
140 /* write 1 in SRC SRS SWC SWS to clear these fields */
141 out_8(&i2c
->xtcntlss
, 0xF0);
143 /* Mode Control Register
144 Flush Slave/Master data buffer */
145 out_8(&i2c
->mdcntl
, IIC_MDCNTL_FSDB
| IIC_MDCNTL_FMDB
);
147 val
= in_8(&i2c
->mdcntl
);
149 /* Ignore General Call, slave transfers are ignored,
150 * disable interrupts, exit unknown bus state, enable hold
151 * SCL 100kHz normaly or FastMode for 400kHz and above
154 val
|= IIC_MDCNTL_EUBS
| IIC_MDCNTL_HSCL
;
156 val
|= IIC_MDCNTL_FSM
;
157 out_8(&i2c
->mdcntl
, val
);
159 /* clear control reg */
160 out_8(&i2c
->cntl
, 0x00);
164 * This code tries to use the features of the 405GP i2c
165 * controller. It will transfer up to 4 bytes in one pass
166 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
167 * is possible to do out16(lhz) transfers.
169 * cmd_type is 0 for write 1 for read.
171 * addr_len can take any value from 0-255, it is only limited
172 * by the char, we could make it larger if needed. If it is
173 * 0 we skip the address write cycle.
175 * Typical case is a Write of an addr followd by a Read. The
176 * IBM FAQ does not cover this. On the last byte of the write
177 * we don't set the creg CHT bit, and on the first bytes of the
178 * read we set the RPST bit.
180 * It does not support address only transfers, there must be
181 * a data part. If you want to write the address yourself, put
182 * it in the data pointer.
184 * It does not support transfer to/from address 0.
186 * It does not check XFRCNT.
188 static int _i2c_transfer(struct i2c_adapter
*adap
,
189 unsigned char cmd_type
,
191 unsigned char addr
[],
192 unsigned char addr_len
,
193 unsigned char data
[],
194 unsigned short data_len
)
196 struct ppc4xx_i2c
*i2c
= ppc4xx_get_i2c(adap
->hwadapnr
);
205 if (data
== 0 || data_len
== 0) {
206 /* Don't support data transfer of no length or to address 0 */
207 printf( "i2c_transfer: bad call\n" );
210 if (addr
&& addr_len
) {
220 /* Clear Stop Complete Bit */
221 out_8(&i2c
->sts
, IIC_STS_SCMP
);
227 status
= in_8(&i2c
->sts
);
229 } while ((status
& IIC_STS_PT
) && (i
> 0));
231 if (status
& IIC_STS_PT
) {
232 result
= IIC_NOK_TOUT
;
236 /* flush the Master/Slave Databuffers */
237 out_8(&i2c
->mdcntl
, in_8(&i2c
->mdcntl
) |
238 IIC_MDCNTL_FMDB
| IIC_MDCNTL_FSDB
);
240 /* need to wait 4 OPB clocks? code below should take that long */
242 /* 7-bit adressing */
243 out_8(&i2c
->hmadr
, 0);
244 out_8(&i2c
->lmadr
, chip
);
250 while (tran
!= cnt
&& (result
== IIC_OK
)) {
255 * Normal transfer, 7-bits adressing, Transfer up to
256 * bc bytes, Normal start, Transfer is a sequence of transfers
260 bc
= (cnt
- tran
) > 4 ? 4 : cnt
- tran
;
261 creg
|= (bc
- 1) << 4;
262 /* if the real cmd type is write continue trans */
263 if ((!cmd_type
&& (ptr
== addr
)) || ((tran
+ bc
) != cnt
))
264 creg
|= IIC_CNTL_CHT
;
267 creg
|= IIC_CNTL_READ
;
269 for(j
= 0; j
< bc
; j
++) {
271 out_8(&i2c
->mdbuf
, ptr
[tran
+ j
]);
274 out_8(&i2c
->cntl
, creg
);
277 * Transfer is in progress
278 * we have to wait for upto 5 bytes of data
279 * 1 byte chip address+r/w bit then bc bytes
281 * udelay(10) is 1 bit time at 100khz
282 * Doubled for slop. 20 is too small.
287 status
= in_8(&i2c
->sts
);
290 } while ((status
& IIC_STS_PT
) && !(status
& IIC_STS_ERR
) &&
293 if (status
& IIC_STS_ERR
) {
295 status
= in_8(&i2c
->extsts
);
296 /* Lost arbitration? */
297 if (status
& IIC_EXTSTS_LA
)
299 /* Incomplete transfer? */
300 if (status
& IIC_EXTSTS_ICT
)
301 result
= IIC_NOK_ICT
;
302 /* Transfer aborted? */
303 if (status
& IIC_EXTSTS_XFRA
)
304 result
= IIC_NOK_XFRA
;
305 } else if ( status
& IIC_STS_PT
) {
306 result
= IIC_NOK_TOUT
;
309 /* Command is reading => get buffer */
310 if ((reading
) && (result
== IIC_OK
)) {
311 /* Are there data in buffer */
312 if (status
& IIC_STS_MDBS
) {
314 * even if we have data we have to wait 4OPB
315 * clocks for it to hit the front of the FIFO,
316 * after that we can just read. We should check
317 * XFCNT here and if the FIFO is full there is
321 for (j
= 0; j
< bc
; j
++)
322 ptr
[tran
+ j
] = in_8(&i2c
->mdbuf
);
324 result
= IIC_NOK_DATA
;
328 if (ptr
== addr
&& tran
== cnt
) {
334 creg
= IIC_CNTL_RPST
;
340 static int ppc4xx_i2c_probe(struct i2c_adapter
*adap
, uchar chip
)
347 * What is needed is to send the chip address and verify that the
348 * address was <ACK>ed (i.e. there was a chip at that address which
349 * drove the data line low).
351 return (_i2c_transfer(adap
, 1, chip
<< 1, 0, 0, buf
, 1) != 0);
354 static int ppc4xx_i2c_transfer(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
355 int alen
, uchar
*buffer
, int len
, int read
)
361 printf("I2C: addr len %d not supported\n", alen
);
366 xaddr
[0] = (addr
>> 24) & 0xFF;
367 xaddr
[1] = (addr
>> 16) & 0xFF;
368 xaddr
[2] = (addr
>> 8) & 0xFF;
369 xaddr
[3] = addr
& 0xFF;
373 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
375 * EEPROM chips that implement "address overflow" are ones
376 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
377 * address and the extra bits end up in the "chip address"
378 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
379 * four 256 byte chips.
381 * Note that we consider the length of the address field to
382 * still be one byte because the extra address bits are
383 * hidden in the chip address.
386 chip
|= ((addr
>> (alen
* 8)) &
387 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
389 ret
= _i2c_transfer(adap
, read
, chip
<< 1, &xaddr
[4 - alen
], alen
,
392 printf("I2C %s: failed %d\n", read
? "read" : "write", ret
);
399 static int ppc4xx_i2c_read(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
400 int alen
, uchar
*buffer
, int len
)
402 return ppc4xx_i2c_transfer(adap
, chip
, addr
, alen
, buffer
, len
, 1);
405 static int ppc4xx_i2c_write(struct i2c_adapter
*adap
, uchar chip
, uint addr
,
406 int alen
, uchar
*buffer
, int len
)
408 return ppc4xx_i2c_transfer(adap
, chip
, addr
, alen
, buffer
, len
, 0);
411 static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter
*adap
,
414 if (speed
!= adap
->speed
)
420 * Register ppc4xx i2c adapters
422 #ifdef CONFIG_SYS_I2C_PPC4XX_CH0
423 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0
, ppc4xx_i2c_init
, ppc4xx_i2c_probe
,
424 ppc4xx_i2c_read
, ppc4xx_i2c_write
,
425 ppc4xx_i2c_set_bus_speed
,
426 CONFIG_SYS_I2C_PPC4XX_SPEED_0
,
427 CONFIG_SYS_I2C_PPC4XX_SLAVE_0
, 0)
429 #ifdef CONFIG_SYS_I2C_PPC4XX_CH1
430 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1
, ppc4xx_i2c_init
, ppc4xx_i2c_probe
,
431 ppc4xx_i2c_read
, ppc4xx_i2c_write
,
432 ppc4xx_i2c_set_bus_speed
,
433 CONFIG_SYS_I2C_PPC4XX_SPEED_1
,
434 CONFIG_SYS_I2C_PPC4XX_SLAVE_1
, 1)