2 * (C) Copyright 2007-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 #ifdef CONFIG_HARD_I2C
37 DECLARE_GLOBAL_DATA_PTR
;
39 #if defined(CONFIG_I2C_MULTI_BUS)
41 * Initialize the bus pointer to whatever one the SPD EEPROM is on.
42 * Default is bus 0. This is necessary because the DDR initialization
43 * runs from ROM, and we can't switch buses because we can't modify
44 * the global variables.
46 #ifndef CONFIG_SYS_SPD_BUS_NUM
47 #define CONFIG_SYS_SPD_BUS_NUM 0
49 static unsigned int i2c_bus_num
__attribute__ ((section (".data"))) =
50 CONFIG_SYS_SPD_BUS_NUM
;
51 #endif /* CONFIG_I2C_MULTI_BUS */
53 static void _i2c_bus_reset(void)
55 struct ppc4xx_i2c
*i2c
= (struct ppc4xx_i2c
*)I2C_BASE_ADDR
;
59 /* Reset status register */
60 /* write 1 in SCMP and IRQA to clear these fields */
61 out_8(&i2c
->sts
, 0x0A);
63 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
64 out_8(&i2c
->extsts
, 0x8F);
66 /* Place chip in the reset state */
67 out_8(&i2c
->xtcntlss
, IIC_XTCNTLSS_SRST
);
69 /* Check if bus is free */
70 dc
= in_8(&i2c
->directcntl
);
71 if (!DIRCTNL_FREE(dc
)){
72 /* Try to set bus free state */
73 out_8(&i2c
->directcntl
, IIC_DIRCNTL_SDAC
| IIC_DIRCNTL_SCC
);
75 /* Wait until we regain bus control */
76 for (i
= 0; i
< 100; ++i
) {
77 dc
= in_8(&i2c
->directcntl
);
82 dc
^= IIC_DIRCNTL_SCC
;
83 out_8(&i2c
->directcntl
, dc
);
85 dc
^= IIC_DIRCNTL_SCC
;
86 out_8(&i2c
->directcntl
, dc
);
91 out_8(&i2c
->xtcntlss
, 0);
94 void i2c_init(int speed
, int slaveaddr
)
96 struct ppc4xx_i2c
*i2c
;
100 #ifdef CONFIG_SYS_I2C_INIT_BOARD
102 * Call board specific i2c bus reset routine before accessing the
103 * environment, which might be in a chip on that bus. For details
104 * about this problem see doc/I2C_Edge_Conditions.
109 for (bus
= 0; bus
< CONFIG_SYS_MAX_I2C_BUS
; bus
++) {
112 /* Set i2c pointer after calling I2C_SET_BUS() */
113 i2c
= (struct ppc4xx_i2c
*)I2C_BASE_ADDR
;
115 /* Handle possible failed I2C state */
116 /* FIXME: put this into i2c_init_board()? */
119 /* clear lo master address */
120 out_8(&i2c
->lmadr
, 0);
122 /* clear hi master address */
123 out_8(&i2c
->hmadr
, 0);
125 /* clear lo slave address */
126 out_8(&i2c
->lsadr
, 0);
128 /* clear hi slave address */
129 out_8(&i2c
->hsadr
, 0);
131 /* Clock divide Register */
132 /* set divisor according to freq_opb */
133 divisor
= (get_OPB_freq() - 1) / 10000000;
136 out_8(&i2c
->clkdiv
, divisor
);
139 out_8(&i2c
->intrmsk
, 0);
141 /* clear transfer count */
142 out_8(&i2c
->xfrcnt
, 0);
144 /* clear extended control & stat */
145 /* write 1 in SRC SRS SWC SWS to clear these fields */
146 out_8(&i2c
->xtcntlss
, 0xF0);
148 /* Mode Control Register
149 Flush Slave/Master data buffer */
150 out_8(&i2c
->mdcntl
, IIC_MDCNTL_FSDB
| IIC_MDCNTL_FMDB
);
152 val
= in_8(&i2c
->mdcntl
);
154 /* Ignore General Call, slave transfers are ignored,
155 * disable interrupts, exit unknown bus state, enable hold
156 * SCL 100kHz normaly or FastMode for 400kHz and above
159 val
|= IIC_MDCNTL_EUBS
| IIC_MDCNTL_HSCL
;
161 val
|= IIC_MDCNTL_FSM
;
162 out_8(&i2c
->mdcntl
, val
);
164 /* clear control reg */
165 out_8(&i2c
->cntl
, 0x00);
168 /* set to SPD bus as default bus upon powerup */
169 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM
);
173 * This code tries to use the features of the 405GP i2c
174 * controller. It will transfer up to 4 bytes in one pass
175 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
176 * is possible to do out16(lhz) transfers.
178 * cmd_type is 0 for write 1 for read.
180 * addr_len can take any value from 0-255, it is only limited
181 * by the char, we could make it larger if needed. If it is
182 * 0 we skip the address write cycle.
184 * Typical case is a Write of an addr followd by a Read. The
185 * IBM FAQ does not cover this. On the last byte of the write
186 * we don't set the creg CHT bit, and on the first bytes of the
187 * read we set the RPST bit.
189 * It does not support address only transfers, there must be
190 * a data part. If you want to write the address yourself, put
191 * it in the data pointer.
193 * It does not support transfer to/from address 0.
195 * It does not check XFRCNT.
197 static int i2c_transfer(unsigned char cmd_type
,
199 unsigned char addr
[],
200 unsigned char addr_len
,
201 unsigned char data
[],
202 unsigned short data_len
)
204 struct ppc4xx_i2c
*i2c
= (struct ppc4xx_i2c
*)I2C_BASE_ADDR
;
213 if (data
== 0 || data_len
== 0) {
214 /* Don't support data transfer of no length or to address 0 */
215 printf( "i2c_transfer: bad call\n" );
218 if (addr
&& addr_len
) {
228 /* Clear Stop Complete Bit */
229 out_8(&i2c
->sts
, IIC_STS_SCMP
);
235 status
= in_8(&i2c
->sts
);
237 } while ((status
& IIC_STS_PT
) && (i
> 0));
239 if (status
& IIC_STS_PT
) {
240 result
= IIC_NOK_TOUT
;
244 /* flush the Master/Slave Databuffers */
245 out_8(&i2c
->mdcntl
, in_8(&i2c
->mdcntl
) |
246 IIC_MDCNTL_FMDB
| IIC_MDCNTL_FSDB
);
248 /* need to wait 4 OPB clocks? code below should take that long */
250 /* 7-bit adressing */
251 out_8(&i2c
->hmadr
, 0);
252 out_8(&i2c
->lmadr
, chip
);
258 while (tran
!= cnt
&& (result
== IIC_OK
)) {
263 * Normal transfer, 7-bits adressing, Transfer up to
264 * bc bytes, Normal start, Transfer is a sequence of transfers
268 bc
= (cnt
- tran
) > 4 ? 4 : cnt
- tran
;
269 creg
|= (bc
- 1) << 4;
270 /* if the real cmd type is write continue trans */
271 if ((!cmd_type
&& (ptr
== addr
)) || ((tran
+ bc
) != cnt
))
272 creg
|= IIC_CNTL_CHT
;
275 creg
|= IIC_CNTL_READ
;
277 for(j
= 0; j
< bc
; j
++) {
279 out_8(&i2c
->mdbuf
, ptr
[tran
+ j
]);
282 out_8(&i2c
->cntl
, creg
);
285 * Transfer is in progress
286 * we have to wait for upto 5 bytes of data
287 * 1 byte chip address+r/w bit then bc bytes
289 * udelay(10) is 1 bit time at 100khz
290 * Doubled for slop. 20 is too small.
295 status
= in_8(&i2c
->sts
);
298 } while ((status
& IIC_STS_PT
) && !(status
& IIC_STS_ERR
) &&
301 if (status
& IIC_STS_ERR
) {
303 status
= in_8(&i2c
->extsts
);
304 /* Lost arbitration? */
305 if (status
& IIC_EXTSTS_LA
)
307 /* Incomplete transfer? */
308 if (status
& IIC_EXTSTS_ICT
)
309 result
= IIC_NOK_ICT
;
310 /* Transfer aborted? */
311 if (status
& IIC_EXTSTS_XFRA
)
312 result
= IIC_NOK_XFRA
;
313 } else if ( status
& IIC_STS_PT
) {
314 result
= IIC_NOK_TOUT
;
317 /* Command is reading => get buffer */
318 if ((reading
) && (result
== IIC_OK
)) {
319 /* Are there data in buffer */
320 if (status
& IIC_STS_MDBS
) {
322 * even if we have data we have to wait 4OPB
323 * clocks for it to hit the front of the FIFO,
324 * after that we can just read. We should check
325 * XFCNT here and if the FIFO is full there is
329 for (j
= 0; j
< bc
; j
++)
330 ptr
[tran
+ j
] = in_8(&i2c
->mdbuf
);
332 result
= IIC_NOK_DATA
;
336 if (ptr
== addr
&& tran
== cnt
) {
342 creg
= IIC_CNTL_RPST
;
348 int i2c_probe(uchar chip
)
355 * What is needed is to send the chip address and verify that the
356 * address was <ACK>ed (i.e. there was a chip at that address which
357 * drove the data line low).
359 return (i2c_transfer(1, chip
<< 1, 0, 0, buf
, 1) != 0);
362 static int ppc4xx_i2c_transfer(uchar chip
, uint addr
, int alen
, uchar
*buffer
,
369 printf("I2C: addr len %d not supported\n", alen
);
374 xaddr
[0] = (addr
>> 24) & 0xFF;
375 xaddr
[1] = (addr
>> 16) & 0xFF;
376 xaddr
[2] = (addr
>> 8) & 0xFF;
377 xaddr
[3] = addr
& 0xFF;
381 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
383 * EEPROM chips that implement "address overflow" are ones
384 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
385 * address and the extra bits end up in the "chip address"
386 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
387 * four 256 byte chips.
389 * Note that we consider the length of the address field to
390 * still be one byte because the extra address bits are
391 * hidden in the chip address.
394 chip
|= ((addr
>> (alen
* 8)) &
395 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
);
397 if ((ret
= i2c_transfer(read
, chip
<< 1, &xaddr
[4 - alen
], alen
,
398 buffer
, len
)) != 0) {
399 if (gd
->have_console
) {
400 printf("I2C %s: failed %d\n",
401 read
? "read" : "write", ret
);
410 int i2c_read(uchar chip
, uint addr
, int alen
, uchar
* buffer
, int len
)
412 return ppc4xx_i2c_transfer(chip
, addr
, alen
, buffer
, len
, 1);
415 int i2c_write(uchar chip
, uint addr
, int alen
, uchar
* buffer
, int len
)
417 return ppc4xx_i2c_transfer(chip
, addr
, alen
, buffer
, len
, 0);
420 #if defined(CONFIG_I2C_MULTI_BUS)
422 * Functions for multiple I2C bus handling
424 unsigned int i2c_get_bus_num(void)
429 int i2c_set_bus_num(unsigned int bus
)
431 if (bus
>= CONFIG_SYS_MAX_I2C_BUS
)
438 #endif /* CONFIG_I2C_MULTI_BUS */
439 #endif /* CONFIG_HARD_I2C */