2 * drivers/i2c/rcar_i2c.c
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
7 * SPDX-License-Identifier: GPL-2.0
9 * NOTE: This driver should be converted to driver model before June 2017.
10 * Please see doc/driver-model/i2c-howto.txt for instructions.
17 DECLARE_GLOBAL_DATA_PTR
;
36 #define MCR_MDBS 0x80 /* non-fifo mode switch */
37 #define MCR_FSCL 0x40 /* override SCL pin */
38 #define MCR_FSDA 0x20 /* override SDA pin */
39 #define MCR_OBPC 0x10 /* override pins */
40 #define MCR_MIE 0x08 /* master if enable */
42 #define MCR_FSB 0x02 /* force stop bit */
43 #define MCR_ESG 0x01 /* en startbit gen. */
46 #define MSR_MNR 0x40 /* nack received */
47 #define MSR_MAL 0x20 /* arbitration lost */
48 #define MSR_MST 0x10 /* sent a stop */
52 #define MSR_MAT 0x01 /* slave addr xfer done */
54 static const struct rcar_i2c
*i2c_dev
[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS
] = {
55 (struct rcar_i2c
*)CONFIG_SYS_RCAR_I2C0_BASE
,
56 (struct rcar_i2c
*)CONFIG_SYS_RCAR_I2C1_BASE
,
57 (struct rcar_i2c
*)CONFIG_SYS_RCAR_I2C2_BASE
,
58 (struct rcar_i2c
*)CONFIG_SYS_RCAR_I2C3_BASE
,
61 static void rcar_i2c_raw_rw_common(struct rcar_i2c
*dev
, u8 chip
, uint addr
)
63 /* set slave address */
64 writel(chip
<< 1, &dev
->icmar
);
65 /* set register address */
66 writel(addr
, &dev
->icrxdtxd
);
68 writel(0, &dev
->icmsr
);
69 /* start master send */
70 writel(MCR_MDBS
| MCR_MIE
| MCR_ESG
, &dev
->icmcr
);
72 while ((readl(&dev
->icmsr
) & (MSR_MAT
| MSR_MDE
))
73 != (MSR_MAT
| MSR_MDE
))
77 writel(MCR_MDBS
| MCR_MIE
, &dev
->icmcr
);
79 writel(~(MSR_MAT
| MSR_MDE
), &dev
->icmsr
);
81 while (!(readl(&dev
->icmsr
) & MSR_MDE
))
85 static void rcar_i2c_raw_rw_finish(struct rcar_i2c
*dev
)
87 while (!(readl(&dev
->icmsr
) & MSR_MST
))
90 writel(0, &dev
->icmcr
);
94 rcar_i2c_raw_write(struct rcar_i2c
*dev
, u8 chip
, uint addr
, u8
*val
, int size
)
96 rcar_i2c_raw_rw_common(dev
, chip
, addr
);
99 writel(*val
, &dev
->icrxdtxd
);
101 writel(~MSR_MDE
, &dev
->icmsr
);
103 while (!(readl(&dev
->icmsr
) & MSR_MDE
))
106 /* set stop condition */
107 writel(MCR_MDBS
| MCR_MIE
| MCR_FSB
, &dev
->icmcr
);
109 writel(~MSR_MDE
, &dev
->icmsr
);
111 rcar_i2c_raw_rw_finish(dev
);
117 rcar_i2c_raw_read(struct rcar_i2c
*dev
, u8 chip
, uint addr
)
121 rcar_i2c_raw_rw_common(dev
, chip
, addr
);
123 /* set slave address, receive */
124 writel((chip
<< 1) | 1, &dev
->icmar
);
125 /* start master receive */
126 writel(MCR_MDBS
| MCR_MIE
| MCR_ESG
, &dev
->icmcr
);
128 writel(0, &dev
->icmsr
);
130 while ((readl(&dev
->icmsr
) & (MSR_MAT
| MSR_MDR
))
131 != (MSR_MAT
| MSR_MDR
))
135 writel(MCR_MDBS
| MCR_MIE
, &dev
->icmcr
);
136 /* prepare stop condition */
137 writel(MCR_MDBS
| MCR_MIE
| MCR_FSB
, &dev
->icmcr
);
139 writel(~(MSR_MAT
| MSR_MDR
), &dev
->icmsr
);
141 while (!(readl(&dev
->icmsr
) & MSR_MDR
))
144 /* get receive data */
145 ret
= (u8
)readl(&dev
->icrxdtxd
);
147 writel(~MSR_MDR
, &dev
->icmsr
);
149 rcar_i2c_raw_rw_finish(dev
);
155 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck])
156 * iicck : I2C internal clock < 20 MHz
157 * ticf : I2C SCL falling time: 35 ns
158 * tr : I2C SCL rising time: 200 ns
159 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5
160 * F[n] : n rounded up to an integer
162 static u32
rcar_clock_gen(int i2c_no
, u32 bus_speed
)
164 u32 iicck
, f
, scl
, scgd
;
167 int bit
= 0, cdf_width
= 3;
168 for (bit
= 0; bit
< (1 << cdf_width
); bit
++) {
169 iicck
= CONFIG_HP_CLK_FREQ
/ (1 + bit
);
170 if (iicck
< 20000000)
174 if (bit
> (1 << cdf_width
)) {
175 puts("rcar-i2c: Can not get CDF\n");
182 f
= (35 + 200 + intd
) * (iicck
/ 1000000000);
184 for (scgd
= 0; scgd
< 0x40; scgd
++) {
185 scl
= iicck
/ (20 + (scgd
* 8) + f
);
186 if (scl
<= bus_speed
)
191 puts("rcar-i2c: Can not get SDGB\n");
195 debug("%s: scl: %d\n", __func__
, scl
);
196 debug("%s: bit %x\n", __func__
, bit
);
197 debug("%s: scgd %x\n", __func__
, scgd
);
198 debug("%s: iccr %x\n", __func__
, (scgd
<< (cdf_width
) | bit
));
200 return scgd
<< (cdf_width
) | bit
;
204 rcar_i2c_init(struct i2c_adapter
*adap
, int speed
, int slaveadd
)
206 struct rcar_i2c
*dev
= (struct rcar_i2c
*)i2c_dev
[adap
->hwadapnr
];
209 /* No i2c support prior to relocation */
210 if (!(gd
->flags
& GD_FLG_RELOC
))
215 * slave mode is not used on this driver
217 writel(0, &dev
->icsier
);
218 writel(0, &dev
->icsar
);
219 writel(0, &dev
->icscr
);
220 writel(0, &dev
->icssr
);
222 /* reset master mode */
223 writel(0, &dev
->icmier
);
224 writel(0, &dev
->icmcr
);
225 writel(0, &dev
->icmsr
);
226 writel(0, &dev
->icmar
);
228 icccr
= rcar_clock_gen(adap
->hwadapnr
, adap
->speed
);
230 puts("I2C: Init failed\n");
232 writel(icccr
, &dev
->icccr
);
235 static int rcar_i2c_read(struct i2c_adapter
*adap
, uint8_t chip
,
236 uint addr
, int alen
, u8
*data
, int len
)
238 struct rcar_i2c
*dev
= (struct rcar_i2c
*)i2c_dev
[adap
->hwadapnr
];
241 for (i
= 0; i
< len
; i
++)
242 data
[i
] = rcar_i2c_raw_read(dev
, chip
, addr
+ i
);
247 static int rcar_i2c_write(struct i2c_adapter
*adap
, uint8_t chip
, uint addr
,
248 int alen
, u8
*data
, int len
)
250 struct rcar_i2c
*dev
= (struct rcar_i2c
*)i2c_dev
[adap
->hwadapnr
];
251 return rcar_i2c_raw_write(dev
, chip
, addr
, data
, len
);
255 rcar_i2c_probe(struct i2c_adapter
*adap
, u8 dev
)
257 return rcar_i2c_read(adap
, dev
, 0, 0, NULL
, 0);
260 static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter
*adap
,
263 struct rcar_i2c
*dev
= (struct rcar_i2c
*)i2c_dev
[adap
->hwadapnr
];
267 rcar_i2c_raw_rw_finish(dev
);
269 icccr
= rcar_clock_gen(adap
->hwadapnr
, speed
);
271 puts("I2C: Init failed\n");
274 writel(icccr
, &dev
->icccr
);
280 * Register RCAR i2c adapters
282 U_BOOT_I2C_ADAP_COMPLETE(rcar_0
, rcar_i2c_init
, rcar_i2c_probe
, rcar_i2c_read
,
283 rcar_i2c_write
, rcar_i2c_set_bus_speed
,
284 CONFIG_SYS_RCAR_I2C0_SPEED
, 0, 0)
285 U_BOOT_I2C_ADAP_COMPLETE(rcar_1
, rcar_i2c_init
, rcar_i2c_probe
, rcar_i2c_read
,
286 rcar_i2c_write
, rcar_i2c_set_bus_speed
,
287 CONFIG_SYS_RCAR_I2C1_SPEED
, 0, 1)
288 U_BOOT_I2C_ADAP_COMPLETE(rcar_2
, rcar_i2c_init
, rcar_i2c_probe
, rcar_i2c_read
,
289 rcar_i2c_write
, rcar_i2c_set_bus_speed
,
290 CONFIG_SYS_RCAR_I2C2_SPEED
, 0, 2)
291 U_BOOT_I2C_ADAP_COMPLETE(rcar_3
, rcar_i2c_init
, rcar_i2c_probe
, rcar_i2c_read
,
292 rcar_i2c_write
, rcar_i2c_set_bus_speed
,
293 CONFIG_SYS_RCAR_I2C3_SPEED
, 0, 3)