]> git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/i2c/soft_i2c.c
Merge branch 'next' of ../next
[people/ms/u-boot.git] / drivers / i2c / soft_i2c.c
1 /*
2 * (C) Copyright 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 * This has been changed substantially by Gerald Van Baren, Custom IDEAS,
24 * vanbaren@cideas.com. It was heavily influenced by LiMon, written by
25 * Neil Russell.
26 */
27
28 #include <common.h>
29 #ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
30 #include <ioports.h>
31 #include <asm/io.h>
32 #endif
33 #ifdef CONFIG_AT91RM9200 /* need this for the at91rm9200 */
34 #include <asm/io.h>
35 #include <asm/arch/hardware.h>
36 #endif
37 #ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */
38 #include <asm/arch/at91_pmc.h>
39 #include <asm/arch/gpio.h>
40 #include <asm/arch/io.h>
41 #endif
42 #ifdef CONFIG_IXP425 /* only valid for IXP425 */
43 #include <asm/arch/ixp425.h>
44 #endif
45 #ifdef CONFIG_LPC2292
46 #include <asm/arch/hardware.h>
47 #endif
48 #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866)
49 #include <asm/io.h>
50 #endif
51 #include <i2c.h>
52
53 /* #define DEBUG_I2C */
54
55 #ifdef DEBUG_I2C
56 DECLARE_GLOBAL_DATA_PTR;
57 #endif
58
59 /*-----------------------------------------------------------------------
60 * Definitions
61 */
62
63 #define RETRIES 0
64
65 #define I2C_ACK 0 /* PD_SDA level to ack a byte */
66 #define I2C_NOACK 1 /* PD_SDA level to noack a byte */
67
68
69 #ifdef DEBUG_I2C
70 #define PRINTD(fmt,args...) do { \
71 if (gd->have_console) \
72 printf (fmt ,##args); \
73 } while (0)
74 #else
75 #define PRINTD(fmt,args...)
76 #endif
77
78 #if defined(CONFIG_I2C_MULTI_BUS)
79 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0;
80 #endif /* CONFIG_I2C_MULTI_BUS */
81
82 /*-----------------------------------------------------------------------
83 * Local functions
84 */
85 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
86 static void send_reset (void);
87 #endif
88 static void send_start (void);
89 static void send_stop (void);
90 static void send_ack (int);
91 static int write_byte (uchar byte);
92 static uchar read_byte (int);
93
94 #if !defined(CONFIG_SYS_I2C_INIT_BOARD)
95 /*-----------------------------------------------------------------------
96 * Send a reset sequence consisting of 9 clocks with the data signal high
97 * to clock any confused device back into an idle state. Also send a
98 * <stop> at the end of the sequence for belts & suspenders.
99 */
100 static void send_reset(void)
101 {
102 I2C_SOFT_DECLARATIONS /* intentional without ';' */
103 int j;
104
105 I2C_SCL(1);
106 I2C_SDA(1);
107 #ifdef I2C_INIT
108 I2C_INIT;
109 #endif
110 I2C_TRISTATE;
111 for(j = 0; j < 9; j++) {
112 I2C_SCL(0);
113 I2C_DELAY;
114 I2C_DELAY;
115 I2C_SCL(1);
116 I2C_DELAY;
117 I2C_DELAY;
118 }
119 send_stop();
120 I2C_TRISTATE;
121 }
122 #endif
123
124 /*-----------------------------------------------------------------------
125 * START: High -> Low on SDA while SCL is High
126 */
127 static void send_start(void)
128 {
129 I2C_SOFT_DECLARATIONS /* intentional without ';' */
130
131 I2C_DELAY;
132 I2C_SDA(1);
133 I2C_ACTIVE;
134 I2C_DELAY;
135 I2C_SCL(1);
136 I2C_DELAY;
137 I2C_SDA(0);
138 I2C_DELAY;
139 }
140
141 /*-----------------------------------------------------------------------
142 * STOP: Low -> High on SDA while SCL is High
143 */
144 static void send_stop(void)
145 {
146 I2C_SOFT_DECLARATIONS /* intentional without ';' */
147
148 I2C_SCL(0);
149 I2C_DELAY;
150 I2C_SDA(0);
151 I2C_ACTIVE;
152 I2C_DELAY;
153 I2C_SCL(1);
154 I2C_DELAY;
155 I2C_SDA(1);
156 I2C_DELAY;
157 I2C_TRISTATE;
158 }
159
160 /*-----------------------------------------------------------------------
161 * ack should be I2C_ACK or I2C_NOACK
162 */
163 static void send_ack(int ack)
164 {
165 I2C_SOFT_DECLARATIONS /* intentional without ';' */
166
167 I2C_SCL(0);
168 I2C_DELAY;
169 I2C_ACTIVE;
170 I2C_SDA(ack);
171 I2C_DELAY;
172 I2C_SCL(1);
173 I2C_DELAY;
174 I2C_DELAY;
175 I2C_SCL(0);
176 I2C_DELAY;
177 }
178
179 /*-----------------------------------------------------------------------
180 * Send 8 bits and look for an acknowledgement.
181 */
182 static int write_byte(uchar data)
183 {
184 I2C_SOFT_DECLARATIONS /* intentional without ';' */
185 int j;
186 int nack;
187
188 I2C_ACTIVE;
189 for(j = 0; j < 8; j++) {
190 I2C_SCL(0);
191 I2C_DELAY;
192 I2C_SDA(data & 0x80);
193 I2C_DELAY;
194 I2C_SCL(1);
195 I2C_DELAY;
196 I2C_DELAY;
197
198 data <<= 1;
199 }
200
201 /*
202 * Look for an <ACK>(negative logic) and return it.
203 */
204 I2C_SCL(0);
205 I2C_DELAY;
206 I2C_SDA(1);
207 I2C_TRISTATE;
208 I2C_DELAY;
209 I2C_SCL(1);
210 I2C_DELAY;
211 I2C_DELAY;
212 nack = I2C_READ;
213 I2C_SCL(0);
214 I2C_DELAY;
215 I2C_ACTIVE;
216
217 return(nack); /* not a nack is an ack */
218 }
219
220 #if defined(CONFIG_I2C_MULTI_BUS)
221 /*
222 * Functions for multiple I2C bus handling
223 */
224 unsigned int i2c_get_bus_num(void)
225 {
226 return i2c_bus_num;
227 }
228
229 int i2c_set_bus_num(unsigned int bus)
230 {
231 #if defined(CONFIG_I2C_MUX)
232 if (bus < CONFIG_SYS_MAX_I2C_BUS) {
233 i2c_bus_num = bus;
234 } else {
235 int ret;
236
237 ret = i2x_mux_select_mux(bus);
238 if (ret == 0)
239 i2c_bus_num = bus;
240 else
241 return ret;
242 }
243 #else
244 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
245 return -1;
246 i2c_bus_num = bus;
247 #endif
248 return 0;
249 }
250 #endif
251
252 /*-----------------------------------------------------------------------
253 * if ack == I2C_ACK, ACK the byte so can continue reading, else
254 * send I2C_NOACK to end the read.
255 */
256 static uchar read_byte(int ack)
257 {
258 I2C_SOFT_DECLARATIONS /* intentional without ';' */
259 int data;
260 int j;
261
262 /*
263 * Read 8 bits, MSB first.
264 */
265 I2C_TRISTATE;
266 I2C_SDA(1);
267 data = 0;
268 for(j = 0; j < 8; j++) {
269 I2C_SCL(0);
270 I2C_DELAY;
271 I2C_SCL(1);
272 I2C_DELAY;
273 data <<= 1;
274 data |= I2C_READ;
275 I2C_DELAY;
276 }
277 send_ack(ack);
278
279 return(data);
280 }
281
282 /*=====================================================================*/
283 /* Public Functions */
284 /*=====================================================================*/
285
286 /*-----------------------------------------------------------------------
287 * Initialization
288 */
289 void i2c_init (int speed, int slaveaddr)
290 {
291 #if defined(CONFIG_SYS_I2C_INIT_BOARD)
292 /* call board specific i2c bus reset routine before accessing the */
293 /* environment, which might be in a chip on that bus. For details */
294 /* about this problem see doc/I2C_Edge_Conditions. */
295 i2c_init_board();
296 #else
297 /*
298 * WARNING: Do NOT save speed in a static variable: if the
299 * I2C routines are called before RAM is initialized (to read
300 * the DIMM SPD, for instance), RAM won't be usable and your
301 * system will crash.
302 */
303 send_reset ();
304 #endif
305 }
306
307 /*-----------------------------------------------------------------------
308 * Probe to see if a chip is present. Also good for checking for the
309 * completion of EEPROM writes since the chip stops responding until
310 * the write completes (typically 10mSec).
311 */
312 int i2c_probe(uchar addr)
313 {
314 int rc;
315
316 /*
317 * perform 1 byte write transaction with just address byte
318 * (fake write)
319 */
320 send_start();
321 rc = write_byte ((addr << 1) | 0);
322 send_stop();
323
324 return (rc ? 1 : 0);
325 }
326
327 /*-----------------------------------------------------------------------
328 * Read bytes
329 */
330 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
331 {
332 int shift;
333 PRINTD("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
334 chip, addr, alen, buffer, len);
335
336 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
337 /*
338 * EEPROM chips that implement "address overflow" are ones
339 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
340 * address and the extra bits end up in the "chip address"
341 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
342 * four 256 byte chips.
343 *
344 * Note that we consider the length of the address field to
345 * still be one byte because the extra address bits are
346 * hidden in the chip address.
347 */
348 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
349
350 PRINTD("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
351 chip, addr);
352 #endif
353
354 /*
355 * Do the addressing portion of a write cycle to set the
356 * chip's address pointer. If the address length is zero,
357 * don't do the normal write cycle to set the address pointer,
358 * there is no address pointer in this chip.
359 */
360 send_start();
361 if(alen > 0) {
362 if(write_byte(chip << 1)) { /* write cycle */
363 send_stop();
364 PRINTD("i2c_read, no chip responded %02X\n", chip);
365 return(1);
366 }
367 shift = (alen-1) * 8;
368 while(alen-- > 0) {
369 if(write_byte(addr >> shift)) {
370 PRINTD("i2c_read, address not <ACK>ed\n");
371 return(1);
372 }
373 shift -= 8;
374 }
375
376 /* Some I2C chips need a stop/start sequence here,
377 * other chips don't work with a full stop and need
378 * only a start. Default behaviour is to send the
379 * stop/start sequence.
380 */
381 #ifdef CONFIG_SOFT_I2C_READ_REPEATED_START
382 send_start();
383 #else
384 send_stop();
385 send_start();
386 #endif
387 }
388 /*
389 * Send the chip address again, this time for a read cycle.
390 * Then read the data. On the last byte, we do a NACK instead
391 * of an ACK(len == 0) to terminate the read.
392 */
393 write_byte((chip << 1) | 1); /* read cycle */
394 while(len-- > 0) {
395 *buffer++ = read_byte(len == 0);
396 }
397 send_stop();
398 return(0);
399 }
400
401 /*-----------------------------------------------------------------------
402 * Write bytes
403 */
404 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
405 {
406 int shift, failures = 0;
407
408 PRINTD("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
409 chip, addr, alen, buffer, len);
410
411 send_start();
412 if(write_byte(chip << 1)) { /* write cycle */
413 send_stop();
414 PRINTD("i2c_write, no chip responded %02X\n", chip);
415 return(1);
416 }
417 shift = (alen-1) * 8;
418 while(alen-- > 0) {
419 if(write_byte(addr >> shift)) {
420 PRINTD("i2c_write, address not <ACK>ed\n");
421 return(1);
422 }
423 shift -= 8;
424 }
425
426 while(len-- > 0) {
427 if(write_byte(*buffer++)) {
428 failures++;
429 }
430 }
431 send_stop();
432 return(failures);
433 }