2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
17 #ifndef CONFIG_TEGRA186
18 #include <asm/arch/clock.h>
19 #include <asm/arch/funcmux.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch-tegra/tegra_i2c.h>
24 DECLARE_GLOBAL_DATA_PTR
;
32 /* Information about i2c controller */
35 struct reset_ctl reset_ctl
;
39 struct i2c_control
*control
;
40 struct i2c_ctlr
*regs
;
42 int inited
; /* bus is inited */
45 static void set_packet_mode(struct i2c_bus
*i2c_bus
)
49 config
= I2C_CNFG_NEW_MASTER_FSM_MASK
| I2C_CNFG_PACKET_MODE_MASK
;
51 if (i2c_bus
->type
== TYPE_DVC
) {
52 struct dvc_ctlr
*dvc
= (struct dvc_ctlr
*)i2c_bus
->regs
;
54 writel(config
, &dvc
->cnfg
);
56 writel(config
, &i2c_bus
->regs
->cnfg
);
58 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
59 * issues, i.e., some slaves may be wrongly detected.
61 setbits_le32(&i2c_bus
->regs
->sl_cnfg
, I2C_SL_CNFG_NEWSL_MASK
);
65 static void i2c_reset_controller(struct i2c_bus
*i2c_bus
)
67 /* Reset I2C controller. */
68 reset_assert(&i2c_bus
->reset_ctl
);
70 reset_deassert(&i2c_bus
->reset_ctl
);
73 /* re-program config register to packet mode */
74 set_packet_mode(i2c_bus
);
77 static int i2c_init_clock(struct i2c_bus
*i2c_bus
, unsigned rate
)
81 ret
= reset_assert(&i2c_bus
->reset_ctl
);
84 ret
= clk_enable(&i2c_bus
->clk
);
87 ret
= clk_set_rate(&i2c_bus
->clk
, rate
);
88 if (IS_ERR_VALUE(ret
))
90 ret
= reset_deassert(&i2c_bus
->reset_ctl
);
97 static void i2c_init_controller(struct i2c_bus
*i2c_bus
)
101 debug("%s: speed=%d\n", __func__
, i2c_bus
->speed
);
103 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
104 * here, in section 23.3.1, but in fact we seem to need a factor of
105 * 16 to get the right frequency.
107 i2c_init_clock(i2c_bus
, i2c_bus
->speed
* 2 * 8);
109 if (i2c_bus
->type
== TYPE_114
) {
111 * T114 I2C went to a single clock source for standard/fast and
112 * HS clock speeds. The new clock rate setting calculation is:
113 * SCL = CLK_SOURCE.I2C /
114 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
115 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
117 * NOTE: We do this here, after the initial clock/pll start,
118 * because if we read the clk_div reg before the controller
119 * is running, we hang, and we need it for the new calc.
121 int clk_div_stdfst_mode
= readl(&i2c_bus
->regs
->clk_div
) >> 16;
122 unsigned rate
= CLK_MULT_STD_FAST_MODE
*
123 (clk_div_stdfst_mode
+ 1) * i2c_bus
->speed
* 2;
124 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__
,
125 clk_div_stdfst_mode
);
127 i2c_init_clock(i2c_bus
, rate
);
130 /* Reset I2C controller. */
131 i2c_reset_controller(i2c_bus
);
133 /* Configure I2C controller. */
134 if (i2c_bus
->type
== TYPE_DVC
) { /* only for DVC I2C */
135 struct dvc_ctlr
*dvc
= (struct dvc_ctlr
*)i2c_bus
->regs
;
137 setbits_le32(&dvc
->ctrl3
, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK
);
140 #ifndef CONFIG_TEGRA186
141 funcmux_select(i2c_bus
->clk
.id
, i2c_bus
->pinmux_config
);
145 static void send_packet_headers(
146 struct i2c_bus
*i2c_bus
,
147 struct i2c_trans_info
*trans
,
149 bool end_with_repeated_start
)
153 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
154 data
= PROTOCOL_TYPE_I2C
<< PKT_HDR1_PROTOCOL_SHIFT
;
155 data
|= packet_id
<< PKT_HDR1_PKT_ID_SHIFT
;
156 data
|= i2c_bus
->id
<< PKT_HDR1_CTLR_ID_SHIFT
;
157 writel(data
, &i2c_bus
->control
->tx_fifo
);
158 debug("pkt header 1 sent (0x%x)\n", data
);
160 /* prepare header2 */
161 data
= (trans
->num_bytes
- 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT
;
162 writel(data
, &i2c_bus
->control
->tx_fifo
);
163 debug("pkt header 2 sent (0x%x)\n", data
);
165 /* prepare IO specific header: configure the slave address */
166 data
= trans
->address
<< PKT_HDR3_SLAVE_ADDR_SHIFT
;
168 /* Enable Read if it is not a write transaction */
169 if (!(trans
->flags
& I2C_IS_WRITE
))
170 data
|= PKT_HDR3_READ_MODE_MASK
;
171 if (end_with_repeated_start
)
172 data
|= PKT_HDR3_REPEAT_START_MASK
;
174 /* Write I2C specific header */
175 writel(data
, &i2c_bus
->control
->tx_fifo
);
176 debug("pkt header 3 sent (0x%x)\n", data
);
179 static int wait_for_tx_fifo_empty(struct i2c_control
*control
)
182 int timeout_us
= I2C_TIMEOUT_USEC
;
184 while (timeout_us
>= 0) {
185 count
= (readl(&control
->fifo_status
) & TX_FIFO_EMPTY_CNT_MASK
)
186 >> TX_FIFO_EMPTY_CNT_SHIFT
;
187 if (count
== I2C_FIFO_DEPTH
)
196 static int wait_for_rx_fifo_notempty(struct i2c_control
*control
)
199 int timeout_us
= I2C_TIMEOUT_USEC
;
201 while (timeout_us
>= 0) {
202 count
= (readl(&control
->fifo_status
) & TX_FIFO_FULL_CNT_MASK
)
203 >> TX_FIFO_FULL_CNT_SHIFT
;
213 static int wait_for_transfer_complete(struct i2c_control
*control
)
216 int timeout_us
= I2C_TIMEOUT_USEC
;
218 while (timeout_us
>= 0) {
219 int_status
= readl(&control
->int_status
);
220 if (int_status
& I2C_INT_NO_ACK_MASK
)
222 if (int_status
& I2C_INT_ARBITRATION_LOST_MASK
)
224 if (int_status
& I2C_INT_XFER_COMPLETE_MASK
)
234 static int send_recv_packets(struct i2c_bus
*i2c_bus
,
235 struct i2c_trans_info
*trans
)
237 struct i2c_control
*control
= i2c_bus
->control
;
244 int is_write
= trans
->flags
& I2C_IS_WRITE
;
246 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
247 int_status
= readl(&control
->int_status
);
248 writel(int_status
, &control
->int_status
);
250 send_packet_headers(i2c_bus
, trans
, 1,
251 trans
->flags
& I2C_USE_REPEATED_START
);
253 words
= DIV_ROUND_UP(trans
->num_bytes
, 4);
254 last_bytes
= trans
->num_bytes
& 3;
258 u32
*wptr
= (u32
*)dptr
;
261 /* deal with word alignment */
262 if ((words
== 1) && last_bytes
) {
264 memcpy(&local
, dptr
, last_bytes
);
265 } else if ((unsigned long)dptr
& 3) {
266 memcpy(&local
, dptr
, sizeof(u32
));
270 writel(local
, &control
->tx_fifo
);
271 debug("pkt data sent (0x%x)\n", local
);
272 if (!wait_for_tx_fifo_empty(control
)) {
277 if (!wait_for_rx_fifo_notempty(control
)) {
282 * for the last word, we read into our local buffer,
283 * in case that caller did not provide enough buffer.
285 local
= readl(&control
->rx_fifo
);
286 if ((words
== 1) && last_bytes
)
287 memcpy(dptr
, (char *)&local
, last_bytes
);
288 else if ((unsigned long)dptr
& 3)
289 memcpy(dptr
, &local
, sizeof(u32
));
292 debug("pkt data received (0x%x)\n", local
);
298 if (wait_for_transfer_complete(control
)) {
304 /* error, reset the controller. */
305 i2c_reset_controller(i2c_bus
);
310 static int tegra_i2c_write_data(struct i2c_bus
*i2c_bus
, u32 addr
, u8
*data
,
311 u32 len
, bool end_with_repeated_start
)
314 struct i2c_trans_info trans_info
;
316 trans_info
.address
= addr
;
317 trans_info
.buf
= data
;
318 trans_info
.flags
= I2C_IS_WRITE
;
319 if (end_with_repeated_start
)
320 trans_info
.flags
|= I2C_USE_REPEATED_START
;
321 trans_info
.num_bytes
= len
;
322 trans_info
.is_10bit_address
= 0;
324 error
= send_recv_packets(i2c_bus
, &trans_info
);
326 debug("tegra_i2c_write_data: Error (%d) !!!\n", error
);
331 static int tegra_i2c_read_data(struct i2c_bus
*i2c_bus
, u32 addr
, u8
*data
,
335 struct i2c_trans_info trans_info
;
337 trans_info
.address
= addr
| 1;
338 trans_info
.buf
= data
;
339 trans_info
.flags
= 0;
340 trans_info
.num_bytes
= len
;
341 trans_info
.is_10bit_address
= 0;
343 error
= send_recv_packets(i2c_bus
, &trans_info
);
345 debug("tegra_i2c_read_data: Error (%d) !!!\n", error
);
350 static int tegra_i2c_set_bus_speed(struct udevice
*dev
, unsigned int speed
)
352 struct i2c_bus
*i2c_bus
= dev_get_priv(dev
);
354 i2c_bus
->speed
= speed
;
355 i2c_init_controller(i2c_bus
);
360 static int tegra_i2c_probe(struct udevice
*dev
)
362 struct i2c_bus
*i2c_bus
= dev_get_priv(dev
);
366 i2c_bus
->id
= dev
->seq
;
367 i2c_bus
->type
= dev_get_driver_data(dev
);
368 i2c_bus
->regs
= (struct i2c_ctlr
*)devfdt_get_addr(dev
);
370 ret
= reset_get_by_name(dev
, "i2c", &i2c_bus
->reset_ctl
);
372 error("reset_get_by_name() failed: %d\n", ret
);
375 ret
= clk_get_by_name(dev
, "div-clk", &i2c_bus
->clk
);
377 error("clk_get_by_name() failed: %d\n", ret
);
381 #ifndef CONFIG_TEGRA186
383 * We don't have a binding for pinmux yet. Leave it out for now. So
384 * far no one needs anything other than the default.
386 i2c_bus
->pinmux_config
= FUNCMUX_DEFAULT
;
389 * We can't specify the pinmux config in the fdt, so I2C2 will not
390 * work on Seaboard. It normally has no devices on it anyway.
391 * You could add in this little hack if you need to use it.
392 * The correct solution is a pinmux binding in the fdt.
394 * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
395 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
399 is_dvc
= dev_get_driver_data(dev
) == TYPE_DVC
;
402 &((struct dvc_ctlr
*)i2c_bus
->regs
)->control
;
404 i2c_bus
->control
= &i2c_bus
->regs
->control
;
406 i2c_init_controller(i2c_bus
);
407 debug("%s: controller bus %d at %p, speed %d: ",
408 is_dvc
? "dvc" : "i2c", dev
->seq
, i2c_bus
->regs
, i2c_bus
->speed
);
413 /* i2c write version without the register address */
414 static int i2c_write_data(struct i2c_bus
*i2c_bus
, uchar chip
, uchar
*buffer
,
415 int len
, bool end_with_repeated_start
)
419 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip
, len
);
420 debug("write_data: ");
421 /* use rc for counter */
422 for (rc
= 0; rc
< len
; ++rc
)
423 debug(" 0x%02x", buffer
[rc
]);
426 /* Shift 7-bit address over for lower-level i2c functions */
427 rc
= tegra_i2c_write_data(i2c_bus
, chip
<< 1, buffer
, len
,
428 end_with_repeated_start
);
430 debug("i2c_write_data(): rc=%d\n", rc
);
435 /* i2c read version without the register address */
436 static int i2c_read_data(struct i2c_bus
*i2c_bus
, uchar chip
, uchar
*buffer
,
441 debug("inside i2c_read_data():\n");
442 /* Shift 7-bit address over for lower-level i2c functions */
443 rc
= tegra_i2c_read_data(i2c_bus
, chip
<< 1, buffer
, len
);
445 debug("i2c_read_data(): rc=%d\n", rc
);
449 debug("i2c_read_data: ");
450 /* reuse rc for counter*/
451 for (rc
= 0; rc
< len
; ++rc
)
452 debug(" 0x%02x", buffer
[rc
]);
458 /* Probe to see if a chip is present. */
459 static int tegra_i2c_probe_chip(struct udevice
*bus
, uint chip_addr
,
462 struct i2c_bus
*i2c_bus
= dev_get_priv(bus
);
466 /* Shift 7-bit address over for lower-level i2c functions */
467 rc
= tegra_i2c_write_data(i2c_bus
, chip_addr
<< 1, ®
, sizeof(reg
),
473 static int tegra_i2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
,
476 struct i2c_bus
*i2c_bus
= dev_get_priv(bus
);
479 debug("i2c_xfer: %d messages\n", nmsgs
);
480 for (; nmsgs
> 0; nmsgs
--, msg
++) {
481 bool next_is_read
= nmsgs
> 1 && (msg
[1].flags
& I2C_M_RD
);
483 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
484 if (msg
->flags
& I2C_M_RD
) {
485 ret
= i2c_read_data(i2c_bus
, msg
->addr
, msg
->buf
,
488 ret
= i2c_write_data(i2c_bus
, msg
->addr
, msg
->buf
,
489 msg
->len
, next_is_read
);
492 debug("i2c_write: error sending\n");
500 int tegra_i2c_get_dvc_bus(struct udevice
**busp
)
504 for (uclass_first_device(UCLASS_I2C
, &bus
);
506 uclass_next_device(&bus
)) {
507 if (dev_get_driver_data(bus
) == TYPE_DVC
) {
516 static const struct dm_i2c_ops tegra_i2c_ops
= {
517 .xfer
= tegra_i2c_xfer
,
518 .probe_chip
= tegra_i2c_probe_chip
,
519 .set_bus_speed
= tegra_i2c_set_bus_speed
,
522 static const struct udevice_id tegra_i2c_ids
[] = {
523 { .compatible
= "nvidia,tegra114-i2c", .data
= TYPE_114
},
524 { .compatible
= "nvidia,tegra20-i2c", .data
= TYPE_STD
},
525 { .compatible
= "nvidia,tegra20-i2c-dvc", .data
= TYPE_DVC
},
529 U_BOOT_DRIVER(i2c_tegra
) = {
532 .of_match
= tegra_i2c_ids
,
533 .probe
= tegra_i2c_probe
,
534 .priv_auto_alloc_size
= sizeof(struct i2c_bus
),
535 .ops
= &tegra_i2c_ops
,