2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
3 * Copyright (c) 2010-2011 NVIDIA Corporation
4 * NVIDIA Corporation <www.nvidia.com>
6 * SPDX-License-Identifier: GPL-2.0+
16 #ifndef CONFIG_TEGRA186
17 #include <asm/arch/clock.h>
18 #include <asm/arch/funcmux.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch-tegra/tegra_i2c.h>
23 DECLARE_GLOBAL_DATA_PTR
;
31 /* Information about i2c controller */
34 struct reset_ctl reset_ctl
;
38 struct i2c_control
*control
;
39 struct i2c_ctlr
*regs
;
41 int inited
; /* bus is inited */
44 static void set_packet_mode(struct i2c_bus
*i2c_bus
)
48 config
= I2C_CNFG_NEW_MASTER_FSM_MASK
| I2C_CNFG_PACKET_MODE_MASK
;
50 if (i2c_bus
->type
== TYPE_DVC
) {
51 struct dvc_ctlr
*dvc
= (struct dvc_ctlr
*)i2c_bus
->regs
;
53 writel(config
, &dvc
->cnfg
);
55 writel(config
, &i2c_bus
->regs
->cnfg
);
57 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
58 * issues, i.e., some slaves may be wrongly detected.
60 setbits_le32(&i2c_bus
->regs
->sl_cnfg
, I2C_SL_CNFG_NEWSL_MASK
);
64 static void i2c_reset_controller(struct i2c_bus
*i2c_bus
)
66 /* Reset I2C controller. */
67 reset_assert(&i2c_bus
->reset_ctl
);
69 reset_deassert(&i2c_bus
->reset_ctl
);
72 /* re-program config register to packet mode */
73 set_packet_mode(i2c_bus
);
76 static int i2c_init_clock(struct i2c_bus
*i2c_bus
, unsigned rate
)
80 ret
= reset_assert(&i2c_bus
->reset_ctl
);
83 ret
= clk_enable(&i2c_bus
->clk
);
86 ret
= clk_set_rate(&i2c_bus
->clk
, rate
);
87 if (IS_ERR_VALUE(ret
))
89 ret
= reset_deassert(&i2c_bus
->reset_ctl
);
96 static void i2c_init_controller(struct i2c_bus
*i2c_bus
)
100 debug("%s: speed=%d\n", __func__
, i2c_bus
->speed
);
102 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
103 * here, in section 23.3.1, but in fact we seem to need a factor of
104 * 16 to get the right frequency.
106 i2c_init_clock(i2c_bus
, i2c_bus
->speed
* 2 * 8);
108 if (i2c_bus
->type
== TYPE_114
) {
110 * T114 I2C went to a single clock source for standard/fast and
111 * HS clock speeds. The new clock rate setting calculation is:
112 * SCL = CLK_SOURCE.I2C /
113 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
114 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
116 * NOTE: We do this here, after the initial clock/pll start,
117 * because if we read the clk_div reg before the controller
118 * is running, we hang, and we need it for the new calc.
120 int clk_div_stdfst_mode
= readl(&i2c_bus
->regs
->clk_div
) >> 16;
121 unsigned rate
= CLK_MULT_STD_FAST_MODE
*
122 (clk_div_stdfst_mode
+ 1) * i2c_bus
->speed
* 2;
123 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__
,
124 clk_div_stdfst_mode
);
126 i2c_init_clock(i2c_bus
, rate
);
129 /* Reset I2C controller. */
130 i2c_reset_controller(i2c_bus
);
132 /* Configure I2C controller. */
133 if (i2c_bus
->type
== TYPE_DVC
) { /* only for DVC I2C */
134 struct dvc_ctlr
*dvc
= (struct dvc_ctlr
*)i2c_bus
->regs
;
136 setbits_le32(&dvc
->ctrl3
, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK
);
139 #ifndef CONFIG_TEGRA186
140 funcmux_select(i2c_bus
->clk
.id
, i2c_bus
->pinmux_config
);
144 static void send_packet_headers(
145 struct i2c_bus
*i2c_bus
,
146 struct i2c_trans_info
*trans
,
148 bool end_with_repeated_start
)
152 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
153 data
= PROTOCOL_TYPE_I2C
<< PKT_HDR1_PROTOCOL_SHIFT
;
154 data
|= packet_id
<< PKT_HDR1_PKT_ID_SHIFT
;
155 data
|= i2c_bus
->id
<< PKT_HDR1_CTLR_ID_SHIFT
;
156 writel(data
, &i2c_bus
->control
->tx_fifo
);
157 debug("pkt header 1 sent (0x%x)\n", data
);
159 /* prepare header2 */
160 data
= (trans
->num_bytes
- 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT
;
161 writel(data
, &i2c_bus
->control
->tx_fifo
);
162 debug("pkt header 2 sent (0x%x)\n", data
);
164 /* prepare IO specific header: configure the slave address */
165 data
= trans
->address
<< PKT_HDR3_SLAVE_ADDR_SHIFT
;
167 /* Enable Read if it is not a write transaction */
168 if (!(trans
->flags
& I2C_IS_WRITE
))
169 data
|= PKT_HDR3_READ_MODE_MASK
;
170 if (end_with_repeated_start
)
171 data
|= PKT_HDR3_REPEAT_START_MASK
;
173 /* Write I2C specific header */
174 writel(data
, &i2c_bus
->control
->tx_fifo
);
175 debug("pkt header 3 sent (0x%x)\n", data
);
178 static int wait_for_tx_fifo_empty(struct i2c_control
*control
)
181 int timeout_us
= I2C_TIMEOUT_USEC
;
183 while (timeout_us
>= 0) {
184 count
= (readl(&control
->fifo_status
) & TX_FIFO_EMPTY_CNT_MASK
)
185 >> TX_FIFO_EMPTY_CNT_SHIFT
;
186 if (count
== I2C_FIFO_DEPTH
)
195 static int wait_for_rx_fifo_notempty(struct i2c_control
*control
)
198 int timeout_us
= I2C_TIMEOUT_USEC
;
200 while (timeout_us
>= 0) {
201 count
= (readl(&control
->fifo_status
) & TX_FIFO_FULL_CNT_MASK
)
202 >> TX_FIFO_FULL_CNT_SHIFT
;
212 static int wait_for_transfer_complete(struct i2c_control
*control
)
215 int timeout_us
= I2C_TIMEOUT_USEC
;
217 while (timeout_us
>= 0) {
218 int_status
= readl(&control
->int_status
);
219 if (int_status
& I2C_INT_NO_ACK_MASK
)
221 if (int_status
& I2C_INT_ARBITRATION_LOST_MASK
)
223 if (int_status
& I2C_INT_XFER_COMPLETE_MASK
)
233 static int send_recv_packets(struct i2c_bus
*i2c_bus
,
234 struct i2c_trans_info
*trans
)
236 struct i2c_control
*control
= i2c_bus
->control
;
243 int is_write
= trans
->flags
& I2C_IS_WRITE
;
245 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
246 int_status
= readl(&control
->int_status
);
247 writel(int_status
, &control
->int_status
);
249 send_packet_headers(i2c_bus
, trans
, 1,
250 trans
->flags
& I2C_USE_REPEATED_START
);
252 words
= DIV_ROUND_UP(trans
->num_bytes
, 4);
253 last_bytes
= trans
->num_bytes
& 3;
257 u32
*wptr
= (u32
*)dptr
;
260 /* deal with word alignment */
261 if ((words
== 1) && last_bytes
) {
263 memcpy(&local
, dptr
, last_bytes
);
264 } else if ((unsigned long)dptr
& 3) {
265 memcpy(&local
, dptr
, sizeof(u32
));
269 writel(local
, &control
->tx_fifo
);
270 debug("pkt data sent (0x%x)\n", local
);
271 if (!wait_for_tx_fifo_empty(control
)) {
276 if (!wait_for_rx_fifo_notempty(control
)) {
281 * for the last word, we read into our local buffer,
282 * in case that caller did not provide enough buffer.
284 local
= readl(&control
->rx_fifo
);
285 if ((words
== 1) && last_bytes
)
286 memcpy(dptr
, (char *)&local
, last_bytes
);
287 else if ((unsigned long)dptr
& 3)
288 memcpy(dptr
, &local
, sizeof(u32
));
291 debug("pkt data received (0x%x)\n", local
);
297 if (wait_for_transfer_complete(control
)) {
303 /* error, reset the controller. */
304 i2c_reset_controller(i2c_bus
);
309 static int tegra_i2c_write_data(struct i2c_bus
*i2c_bus
, u32 addr
, u8
*data
,
310 u32 len
, bool end_with_repeated_start
)
313 struct i2c_trans_info trans_info
;
315 trans_info
.address
= addr
;
316 trans_info
.buf
= data
;
317 trans_info
.flags
= I2C_IS_WRITE
;
318 if (end_with_repeated_start
)
319 trans_info
.flags
|= I2C_USE_REPEATED_START
;
320 trans_info
.num_bytes
= len
;
321 trans_info
.is_10bit_address
= 0;
323 error
= send_recv_packets(i2c_bus
, &trans_info
);
325 debug("tegra_i2c_write_data: Error (%d) !!!\n", error
);
330 static int tegra_i2c_read_data(struct i2c_bus
*i2c_bus
, u32 addr
, u8
*data
,
334 struct i2c_trans_info trans_info
;
336 trans_info
.address
= addr
| 1;
337 trans_info
.buf
= data
;
338 trans_info
.flags
= 0;
339 trans_info
.num_bytes
= len
;
340 trans_info
.is_10bit_address
= 0;
342 error
= send_recv_packets(i2c_bus
, &trans_info
);
344 debug("tegra_i2c_read_data: Error (%d) !!!\n", error
);
349 static int tegra_i2c_set_bus_speed(struct udevice
*dev
, unsigned int speed
)
351 struct i2c_bus
*i2c_bus
= dev_get_priv(dev
);
353 i2c_bus
->speed
= speed
;
354 i2c_init_controller(i2c_bus
);
359 static int tegra_i2c_probe(struct udevice
*dev
)
361 struct i2c_bus
*i2c_bus
= dev_get_priv(dev
);
365 i2c_bus
->id
= dev
->seq
;
366 i2c_bus
->type
= dev_get_driver_data(dev
);
367 i2c_bus
->regs
= (struct i2c_ctlr
*)dev_read_addr(dev
);
368 if ((ulong
)i2c_bus
->regs
== FDT_ADDR_T_NONE
) {
369 debug("%s: Cannot get regs address\n", __func__
);
373 ret
= reset_get_by_name(dev
, "i2c", &i2c_bus
->reset_ctl
);
375 pr_err("reset_get_by_name() failed: %d\n", ret
);
378 ret
= clk_get_by_name(dev
, "div-clk", &i2c_bus
->clk
);
380 pr_err("clk_get_by_name() failed: %d\n", ret
);
384 #ifndef CONFIG_TEGRA186
386 * We don't have a binding for pinmux yet. Leave it out for now. So
387 * far no one needs anything other than the default.
389 i2c_bus
->pinmux_config
= FUNCMUX_DEFAULT
;
392 * We can't specify the pinmux config in the fdt, so I2C2 will not
393 * work on Seaboard. It normally has no devices on it anyway.
394 * You could add in this little hack if you need to use it.
395 * The correct solution is a pinmux binding in the fdt.
397 * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
398 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
402 is_dvc
= dev_get_driver_data(dev
) == TYPE_DVC
;
405 &((struct dvc_ctlr
*)i2c_bus
->regs
)->control
;
407 i2c_bus
->control
= &i2c_bus
->regs
->control
;
409 i2c_init_controller(i2c_bus
);
410 debug("%s: controller bus %d at %p, speed %d: ",
411 is_dvc
? "dvc" : "i2c", dev
->seq
, i2c_bus
->regs
, i2c_bus
->speed
);
416 /* i2c write version without the register address */
417 static int i2c_write_data(struct i2c_bus
*i2c_bus
, uchar chip
, uchar
*buffer
,
418 int len
, bool end_with_repeated_start
)
422 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip
, len
);
423 debug("write_data: ");
424 /* use rc for counter */
425 for (rc
= 0; rc
< len
; ++rc
)
426 debug(" 0x%02x", buffer
[rc
]);
429 /* Shift 7-bit address over for lower-level i2c functions */
430 rc
= tegra_i2c_write_data(i2c_bus
, chip
<< 1, buffer
, len
,
431 end_with_repeated_start
);
433 debug("i2c_write_data(): rc=%d\n", rc
);
438 /* i2c read version without the register address */
439 static int i2c_read_data(struct i2c_bus
*i2c_bus
, uchar chip
, uchar
*buffer
,
444 debug("inside i2c_read_data():\n");
445 /* Shift 7-bit address over for lower-level i2c functions */
446 rc
= tegra_i2c_read_data(i2c_bus
, chip
<< 1, buffer
, len
);
448 debug("i2c_read_data(): rc=%d\n", rc
);
452 debug("i2c_read_data: ");
453 /* reuse rc for counter*/
454 for (rc
= 0; rc
< len
; ++rc
)
455 debug(" 0x%02x", buffer
[rc
]);
461 /* Probe to see if a chip is present. */
462 static int tegra_i2c_probe_chip(struct udevice
*bus
, uint chip_addr
,
465 struct i2c_bus
*i2c_bus
= dev_get_priv(bus
);
469 /* Shift 7-bit address over for lower-level i2c functions */
470 rc
= tegra_i2c_write_data(i2c_bus
, chip_addr
<< 1, ®
, sizeof(reg
),
476 static int tegra_i2c_xfer(struct udevice
*bus
, struct i2c_msg
*msg
,
479 struct i2c_bus
*i2c_bus
= dev_get_priv(bus
);
482 debug("i2c_xfer: %d messages\n", nmsgs
);
483 for (; nmsgs
> 0; nmsgs
--, msg
++) {
484 bool next_is_read
= nmsgs
> 1 && (msg
[1].flags
& I2C_M_RD
);
486 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg
->addr
, msg
->len
);
487 if (msg
->flags
& I2C_M_RD
) {
488 ret
= i2c_read_data(i2c_bus
, msg
->addr
, msg
->buf
,
491 ret
= i2c_write_data(i2c_bus
, msg
->addr
, msg
->buf
,
492 msg
->len
, next_is_read
);
495 debug("i2c_write: error sending\n");
503 int tegra_i2c_get_dvc_bus(struct udevice
**busp
)
507 for (uclass_first_device(UCLASS_I2C
, &bus
);
509 uclass_next_device(&bus
)) {
510 if (dev_get_driver_data(bus
) == TYPE_DVC
) {
519 static const struct dm_i2c_ops tegra_i2c_ops
= {
520 .xfer
= tegra_i2c_xfer
,
521 .probe_chip
= tegra_i2c_probe_chip
,
522 .set_bus_speed
= tegra_i2c_set_bus_speed
,
525 static const struct udevice_id tegra_i2c_ids
[] = {
526 { .compatible
= "nvidia,tegra114-i2c", .data
= TYPE_114
},
527 { .compatible
= "nvidia,tegra20-i2c", .data
= TYPE_STD
},
528 { .compatible
= "nvidia,tegra20-i2c-dvc", .data
= TYPE_DVC
},
532 U_BOOT_DRIVER(i2c_tegra
) = {
535 .of_match
= tegra_i2c_ids
,
536 .probe
= tegra_i2c_probe
,
537 .priv_auto_alloc_size
= sizeof(struct i2c_bus
),
538 .ops
= &tegra_i2c_ops
,