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[thirdparty/linux.git] / drivers / iio / adc / ad7192.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver
4 *
5 * Copyright 2011-2015 Analog Devices Inc.
6 */
7
8 #include <linux/interrupt.h>
9 #include <linux/clk.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19 #include <linux/of_device.h>
20
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/adc/ad_sigma_delta.h>
28
29 /* Registers */
30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
38 /* (AD7792)/24-bit (AD7192)) */
39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */
40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */
41
42 /* Communications Register Bit Designations (AD7192_REG_COMM) */
43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */
44 #define AD7192_COMM_WRITE 0 /* Write Operation */
45 #define AD7192_COMM_READ BIT(6) /* Read Operation */
46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */
48
49 /* Status Register Bit Designations (AD7192_REG_STAT) */
50 #define AD7192_STAT_RDY BIT(7) /* Ready */
51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */
52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */
53 #define AD7192_STAT_PARITY BIT(4) /* Parity */
54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */
55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
57
58 /* Mode Register Bit Designations (AD7192_REG_MODE) */
59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */
60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */
61 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */
62 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */
63 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */
64 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/
65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */
66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/
67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */
68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */
69 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */
70
71 /* Mode Register: AD7192_MODE_SEL options */
72 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */
73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
74 #define AD7192_MODE_IDLE 2 /* Idle Mode */
75 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */
76 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
77 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
78 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
79 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
80
81 /* Mode Register: AD7192_MODE_CLKSRC options */
82 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/
83 /* from MCLK1 to MCLK2 */
84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
85 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */
86 /* available at the MCLK2 pin */
87 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/
88 /* at the MCLK2 pin */
89
90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */
91
92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */
93 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */
94 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */
95 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */
96 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */
97 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */
98 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */
99 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */
100 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */
101
102 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */
103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
104 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */
105 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */
106 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */
107 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */
108 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */
109 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */
110
111 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */
112 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */
113 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */
114 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */
115 #define AD7193_CH_TEMP 0x100 /* Temp senseor */
116 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */
117 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */
118 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */
119 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */
120 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */
121 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */
122 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */
123 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */
124 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */
125 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */
126
127 /* ID Register Bit Designations (AD7192_REG_ID) */
128 #define ID_AD7190 0x4
129 #define ID_AD7192 0x0
130 #define ID_AD7193 0x2
131 #define ID_AD7195 0x6
132 #define AD7192_ID_MASK 0x0F
133
134 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */
135 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */
136 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */
137 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */
138 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */
139 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */
140 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
141 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */
142
143 #define AD7192_EXT_FREQ_MHZ_MIN 2457600
144 #define AD7192_EXT_FREQ_MHZ_MAX 5120000
145 #define AD7192_INT_FREQ_MHZ 4915200
146
147 #define AD7192_NO_SYNC_FILTER 1
148 #define AD7192_SYNC3_FILTER 3
149 #define AD7192_SYNC4_FILTER 4
150
151 /* NOTE:
152 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output.
153 * In order to avoid contentions on the SPI bus, it's therefore necessary
154 * to use spi bus locking.
155 *
156 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
157 */
158
159 enum {
160 AD7192_SYSCALIB_ZERO_SCALE,
161 AD7192_SYSCALIB_FULL_SCALE,
162 };
163
164 struct ad7192_state {
165 struct regulator *avdd;
166 struct regulator *dvdd;
167 struct clk *mclk;
168 u16 int_vref_mv;
169 u32 fclk;
170 u32 f_order;
171 u32 mode;
172 u32 conf;
173 u32 scale_avail[8][2];
174 u8 gpocon;
175 u8 devid;
176 u8 clock_sel;
177 struct mutex lock; /* protect sensor state */
178 u8 syscalib_mode[8];
179
180 struct ad_sigma_delta sd;
181 };
182
183 static const char * const ad7192_syscalib_modes[] = {
184 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale",
185 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale",
186 };
187
188 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev,
189 const struct iio_chan_spec *chan,
190 unsigned int mode)
191 {
192 struct ad7192_state *st = iio_priv(indio_dev);
193
194 st->syscalib_mode[chan->channel] = mode;
195
196 return 0;
197 }
198
199 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev,
200 const struct iio_chan_spec *chan)
201 {
202 struct ad7192_state *st = iio_priv(indio_dev);
203
204 return st->syscalib_mode[chan->channel];
205 }
206
207 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev,
208 uintptr_t private,
209 const struct iio_chan_spec *chan,
210 const char *buf, size_t len)
211 {
212 struct ad7192_state *st = iio_priv(indio_dev);
213 bool sys_calib;
214 int ret, temp;
215
216 ret = strtobool(buf, &sys_calib);
217 if (ret)
218 return ret;
219
220 temp = st->syscalib_mode[chan->channel];
221 if (sys_calib) {
222 if (temp == AD7192_SYSCALIB_ZERO_SCALE)
223 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO,
224 chan->address);
225 else
226 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL,
227 chan->address);
228 }
229
230 return ret ? ret : len;
231 }
232
233 static const struct iio_enum ad7192_syscalib_mode_enum = {
234 .items = ad7192_syscalib_modes,
235 .num_items = ARRAY_SIZE(ad7192_syscalib_modes),
236 .set = ad7192_set_syscalib_mode,
237 .get = ad7192_get_syscalib_mode
238 };
239
240 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = {
241 {
242 .name = "sys_calibration",
243 .write = ad7192_write_syscalib,
244 .shared = IIO_SEPARATE,
245 },
246 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
247 &ad7192_syscalib_mode_enum),
248 IIO_ENUM_AVAILABLE("sys_calibration_mode", &ad7192_syscalib_mode_enum),
249 {}
250 };
251
252 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
253 {
254 return container_of(sd, struct ad7192_state, sd);
255 }
256
257 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
258 {
259 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
260
261 st->conf &= ~AD7192_CONF_CHAN_MASK;
262 st->conf |= AD7192_CONF_CHAN(channel);
263
264 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
265 }
266
267 static int ad7192_set_mode(struct ad_sigma_delta *sd,
268 enum ad_sigma_delta_mode mode)
269 {
270 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
271
272 st->mode &= ~AD7192_MODE_SEL_MASK;
273 st->mode |= AD7192_MODE_SEL(mode);
274
275 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
276 }
277
278 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
279 .set_channel = ad7192_set_channel,
280 .set_mode = ad7192_set_mode,
281 .has_registers = true,
282 .addr_shift = 3,
283 .read_mask = BIT(6),
284 };
285
286 static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
287 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
288 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
289 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
290 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
291 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
292 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
293 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
294 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
295 };
296
297 static int ad7192_calibrate_all(struct ad7192_state *st)
298 {
299 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
300 ARRAY_SIZE(ad7192_calib_arr));
301 }
302
303 static inline bool ad7192_valid_external_frequency(u32 freq)
304 {
305 return (freq >= AD7192_EXT_FREQ_MHZ_MIN &&
306 freq <= AD7192_EXT_FREQ_MHZ_MAX);
307 }
308
309 static int ad7192_of_clock_select(struct ad7192_state *st)
310 {
311 struct device_node *np = st->sd.spi->dev.of_node;
312 unsigned int clock_sel;
313
314 clock_sel = AD7192_CLK_INT;
315
316 /* use internal clock */
317 if (PTR_ERR(st->mclk) == -ENOENT) {
318 if (of_property_read_bool(np, "adi,int-clock-output-enable"))
319 clock_sel = AD7192_CLK_INT_CO;
320 } else {
321 if (of_property_read_bool(np, "adi,clock-xtal"))
322 clock_sel = AD7192_CLK_EXT_MCLK1_2;
323 else
324 clock_sel = AD7192_CLK_EXT_MCLK2;
325 }
326
327 return clock_sel;
328 }
329
330 static int ad7192_setup(struct ad7192_state *st, struct device_node *np)
331 {
332 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
333 bool rej60_en, refin2_en;
334 bool buf_en, bipolar, burnout_curr_en;
335 unsigned long long scale_uv;
336 int i, ret, id;
337
338 /* reset the serial interface */
339 ret = ad_sd_reset(&st->sd, 48);
340 if (ret < 0)
341 return ret;
342 usleep_range(500, 1000); /* Wait for at least 500us */
343
344 /* write/read test for device presence */
345 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
346 if (ret)
347 return ret;
348
349 id &= AD7192_ID_MASK;
350
351 if (id != st->devid)
352 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
353 id);
354
355 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
356 AD7192_MODE_CLKSRC(st->clock_sel) |
357 AD7192_MODE_RATE(480);
358
359 st->conf = AD7192_CONF_GAIN(0);
360
361 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable");
362 if (rej60_en)
363 st->mode |= AD7192_MODE_REJ60;
364
365 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable");
366 if (refin2_en && st->devid != ID_AD7195)
367 st->conf |= AD7192_CONF_REFSEL;
368
369 st->conf &= ~AD7192_CONF_CHOP;
370 st->f_order = AD7192_NO_SYNC_FILTER;
371
372 buf_en = of_property_read_bool(np, "adi,buffer-enable");
373 if (buf_en)
374 st->conf |= AD7192_CONF_BUF;
375
376 bipolar = of_property_read_bool(np, "bipolar");
377 if (!bipolar)
378 st->conf |= AD7192_CONF_UNIPOLAR;
379
380 burnout_curr_en = of_property_read_bool(np,
381 "adi,burnout-currents-enable");
382 if (burnout_curr_en && buf_en) {
383 st->conf |= AD7192_CONF_BURN;
384 } else if (burnout_curr_en) {
385 dev_warn(&st->sd.spi->dev,
386 "Can't enable burnout currents: see CHOP or buffer\n");
387 }
388
389 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
390 if (ret)
391 return ret;
392
393 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
394 if (ret)
395 return ret;
396
397 ret = ad7192_calibrate_all(st);
398 if (ret)
399 return ret;
400
401 /* Populate available ADC input ranges */
402 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
403 scale_uv = ((u64)st->int_vref_mv * 100000000)
404 >> (indio_dev->channels[0].scan_type.realbits -
405 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
406 scale_uv >>= i;
407
408 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
409 st->scale_avail[i][0] = scale_uv;
410 }
411
412 return 0;
413 }
414
415 static ssize_t ad7192_show_ac_excitation(struct device *dev,
416 struct device_attribute *attr,
417 char *buf)
418 {
419 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
420 struct ad7192_state *st = iio_priv(indio_dev);
421
422 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
423 }
424
425 static ssize_t ad7192_show_bridge_switch(struct device *dev,
426 struct device_attribute *attr,
427 char *buf)
428 {
429 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
430 struct ad7192_state *st = iio_priv(indio_dev);
431
432 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
433 }
434
435 static ssize_t ad7192_set(struct device *dev,
436 struct device_attribute *attr,
437 const char *buf,
438 size_t len)
439 {
440 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
441 struct ad7192_state *st = iio_priv(indio_dev);
442 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
443 int ret;
444 bool val;
445
446 ret = strtobool(buf, &val);
447 if (ret < 0)
448 return ret;
449
450 ret = iio_device_claim_direct_mode(indio_dev);
451 if (ret)
452 return ret;
453
454 switch ((u32)this_attr->address) {
455 case AD7192_REG_GPOCON:
456 if (val)
457 st->gpocon |= AD7192_GPOCON_BPDSW;
458 else
459 st->gpocon &= ~AD7192_GPOCON_BPDSW;
460
461 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
462 break;
463 case AD7192_REG_MODE:
464 if (val)
465 st->mode |= AD7192_MODE_ACX;
466 else
467 st->mode &= ~AD7192_MODE_ACX;
468
469 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
470 break;
471 default:
472 ret = -EINVAL;
473 }
474
475 iio_device_release_direct_mode(indio_dev);
476
477 return ret ? ret : len;
478 }
479
480 static void ad7192_get_available_filter_freq(struct ad7192_state *st,
481 int *freq)
482 {
483 unsigned int fadc;
484
485 /* Formulas for filter at page 25 of the datasheet */
486 fadc = DIV_ROUND_CLOSEST(st->fclk,
487 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode));
488 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
489
490 fadc = DIV_ROUND_CLOSEST(st->fclk,
491 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode));
492 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024);
493
494 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode));
495 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024);
496 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024);
497 }
498
499 static ssize_t ad7192_show_filter_avail(struct device *dev,
500 struct device_attribute *attr,
501 char *buf)
502 {
503 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
504 struct ad7192_state *st = iio_priv(indio_dev);
505 unsigned int freq_avail[4], i;
506 size_t len = 0;
507
508 ad7192_get_available_filter_freq(st, freq_avail);
509
510 for (i = 0; i < ARRAY_SIZE(freq_avail); i++)
511 len += scnprintf(buf + len, PAGE_SIZE - len,
512 "%d.%d ", freq_avail[i] / 1000,
513 freq_avail[i] % 1000);
514
515 buf[len - 1] = '\n';
516
517 return len;
518 }
519
520 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available,
521 0444, ad7192_show_filter_avail, NULL, 0);
522
523 static IIO_DEVICE_ATTR(bridge_switch_en, 0644,
524 ad7192_show_bridge_switch, ad7192_set,
525 AD7192_REG_GPOCON);
526
527 static IIO_DEVICE_ATTR(ac_excitation_en, 0644,
528 ad7192_show_ac_excitation, ad7192_set,
529 AD7192_REG_MODE);
530
531 static struct attribute *ad7192_attributes[] = {
532 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
533 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
534 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
535 NULL
536 };
537
538 static const struct attribute_group ad7192_attribute_group = {
539 .attrs = ad7192_attributes,
540 };
541
542 static struct attribute *ad7195_attributes[] = {
543 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr,
544 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
545 NULL
546 };
547
548 static const struct attribute_group ad7195_attribute_group = {
549 .attrs = ad7195_attributes,
550 };
551
552 static unsigned int ad7192_get_temp_scale(bool unipolar)
553 {
554 return unipolar ? 2815 * 2 : 2815;
555 }
556
557 static int ad7192_set_3db_filter_freq(struct ad7192_state *st,
558 int val, int val2)
559 {
560 int freq_avail[4], i, ret, freq;
561 unsigned int diff_new, diff_old;
562 int idx = 0;
563
564 diff_old = U32_MAX;
565 freq = val * 1000 + val2;
566
567 ad7192_get_available_filter_freq(st, freq_avail);
568
569 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) {
570 diff_new = abs(freq - freq_avail[i]);
571 if (diff_new < diff_old) {
572 diff_old = diff_new;
573 idx = i;
574 }
575 }
576
577 switch (idx) {
578 case 0:
579 st->f_order = AD7192_SYNC4_FILTER;
580 st->mode &= ~AD7192_MODE_SINC3;
581
582 st->conf |= AD7192_CONF_CHOP;
583 break;
584 case 1:
585 st->f_order = AD7192_SYNC3_FILTER;
586 st->mode |= AD7192_MODE_SINC3;
587
588 st->conf |= AD7192_CONF_CHOP;
589 break;
590 case 2:
591 st->f_order = AD7192_NO_SYNC_FILTER;
592 st->mode &= ~AD7192_MODE_SINC3;
593
594 st->conf &= ~AD7192_CONF_CHOP;
595 break;
596 case 3:
597 st->f_order = AD7192_NO_SYNC_FILTER;
598 st->mode |= AD7192_MODE_SINC3;
599
600 st->conf &= ~AD7192_CONF_CHOP;
601 break;
602 }
603
604 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
605 if (ret < 0)
606 return ret;
607
608 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
609 }
610
611 static int ad7192_get_3db_filter_freq(struct ad7192_state *st)
612 {
613 unsigned int fadc;
614
615 fadc = DIV_ROUND_CLOSEST(st->fclk,
616 st->f_order * AD7192_MODE_RATE(st->mode));
617
618 if (st->conf & AD7192_CONF_CHOP)
619 return DIV_ROUND_CLOSEST(fadc * 240, 1024);
620 if (st->mode & AD7192_MODE_SINC3)
621 return DIV_ROUND_CLOSEST(fadc * 272, 1024);
622 else
623 return DIV_ROUND_CLOSEST(fadc * 230, 1024);
624 }
625
626 static int ad7192_read_raw(struct iio_dev *indio_dev,
627 struct iio_chan_spec const *chan,
628 int *val,
629 int *val2,
630 long m)
631 {
632 struct ad7192_state *st = iio_priv(indio_dev);
633 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
634
635 switch (m) {
636 case IIO_CHAN_INFO_RAW:
637 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
638 case IIO_CHAN_INFO_SCALE:
639 switch (chan->type) {
640 case IIO_VOLTAGE:
641 mutex_lock(&st->lock);
642 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
643 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
644 mutex_unlock(&st->lock);
645 return IIO_VAL_INT_PLUS_NANO;
646 case IIO_TEMP:
647 *val = 0;
648 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
649 return IIO_VAL_INT_PLUS_NANO;
650 default:
651 return -EINVAL;
652 }
653 case IIO_CHAN_INFO_OFFSET:
654 if (!unipolar)
655 *val = -(1 << (chan->scan_type.realbits - 1));
656 else
657 *val = 0;
658 /* Kelvin to Celsius */
659 if (chan->type == IIO_TEMP)
660 *val -= 273 * ad7192_get_temp_scale(unipolar);
661 return IIO_VAL_INT;
662 case IIO_CHAN_INFO_SAMP_FREQ:
663 *val = st->fclk /
664 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode));
665 return IIO_VAL_INT;
666 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
667 *val = ad7192_get_3db_filter_freq(st);
668 *val2 = 1000;
669 return IIO_VAL_FRACTIONAL;
670 }
671
672 return -EINVAL;
673 }
674
675 static int ad7192_write_raw(struct iio_dev *indio_dev,
676 struct iio_chan_spec const *chan,
677 int val,
678 int val2,
679 long mask)
680 {
681 struct ad7192_state *st = iio_priv(indio_dev);
682 int ret, i, div;
683 unsigned int tmp;
684
685 ret = iio_device_claim_direct_mode(indio_dev);
686 if (ret)
687 return ret;
688
689 switch (mask) {
690 case IIO_CHAN_INFO_SCALE:
691 ret = -EINVAL;
692 mutex_lock(&st->lock);
693 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
694 if (val2 == st->scale_avail[i][1]) {
695 ret = 0;
696 tmp = st->conf;
697 st->conf &= ~AD7192_CONF_GAIN(-1);
698 st->conf |= AD7192_CONF_GAIN(i);
699 if (tmp == st->conf)
700 break;
701 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
702 3, st->conf);
703 ad7192_calibrate_all(st);
704 break;
705 }
706 mutex_unlock(&st->lock);
707 break;
708 case IIO_CHAN_INFO_SAMP_FREQ:
709 if (!val) {
710 ret = -EINVAL;
711 break;
712 }
713
714 div = st->fclk / (val * st->f_order * 1024);
715 if (div < 1 || div > 1023) {
716 ret = -EINVAL;
717 break;
718 }
719
720 st->mode &= ~AD7192_MODE_RATE(-1);
721 st->mode |= AD7192_MODE_RATE(div);
722 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
723 break;
724 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
725 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000);
726 break;
727 default:
728 ret = -EINVAL;
729 }
730
731 iio_device_release_direct_mode(indio_dev);
732
733 return ret;
734 }
735
736 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
737 struct iio_chan_spec const *chan,
738 long mask)
739 {
740 switch (mask) {
741 case IIO_CHAN_INFO_SCALE:
742 return IIO_VAL_INT_PLUS_NANO;
743 case IIO_CHAN_INFO_SAMP_FREQ:
744 return IIO_VAL_INT;
745 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
746 return IIO_VAL_INT_PLUS_MICRO;
747 default:
748 return -EINVAL;
749 }
750 }
751
752 static int ad7192_read_avail(struct iio_dev *indio_dev,
753 struct iio_chan_spec const *chan,
754 const int **vals, int *type, int *length,
755 long mask)
756 {
757 struct ad7192_state *st = iio_priv(indio_dev);
758
759 switch (mask) {
760 case IIO_CHAN_INFO_SCALE:
761 *vals = (int *)st->scale_avail;
762 *type = IIO_VAL_INT_PLUS_NANO;
763 /* Values are stored in a 2D matrix */
764 *length = ARRAY_SIZE(st->scale_avail) * 2;
765
766 return IIO_AVAIL_LIST;
767 }
768
769 return -EINVAL;
770 }
771
772 static const struct iio_info ad7192_info = {
773 .read_raw = ad7192_read_raw,
774 .write_raw = ad7192_write_raw,
775 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
776 .read_avail = ad7192_read_avail,
777 .attrs = &ad7192_attribute_group,
778 .validate_trigger = ad_sd_validate_trigger,
779 };
780
781 static const struct iio_info ad7195_info = {
782 .read_raw = ad7192_read_raw,
783 .write_raw = ad7192_write_raw,
784 .write_raw_get_fmt = ad7192_write_raw_get_fmt,
785 .read_avail = ad7192_read_avail,
786 .attrs = &ad7195_attribute_group,
787 .validate_trigger = ad_sd_validate_trigger,
788 };
789
790 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \
791 _type, _mask_type_av, _ext_info) \
792 { \
793 .type = (_type), \
794 .differential = ((_channel2) == -1 ? 0 : 1), \
795 .indexed = 1, \
796 .channel = (_channel1), \
797 .channel2 = (_channel2), \
798 .address = (_address), \
799 .extend_name = (_extend_name), \
800 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
801 BIT(IIO_CHAN_INFO_OFFSET), \
802 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
803 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
804 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
805 .info_mask_shared_by_type_available = (_mask_type_av), \
806 .ext_info = (_ext_info), \
807 .scan_index = (_si), \
808 .scan_type = { \
809 .sign = 'u', \
810 .realbits = 24, \
811 .storagebits = 32, \
812 .endianness = IIO_BE, \
813 }, \
814 }
815
816 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \
817 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \
818 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \
819 ad7192_calibsys_ext_info)
820
821 #define AD719x_CHANNEL(_si, _channel1, _address) \
822 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \
823 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
824
825 #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \
826 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \
827 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info)
828
829 #define AD719x_TEMP_CHANNEL(_si, _address) \
830 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL)
831
832 static const struct iio_chan_spec ad7192_channels[] = {
833 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
834 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
835 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP),
836 AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M),
837 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
838 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2),
839 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3),
840 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4),
841 IIO_CHAN_SOFT_TIMESTAMP(8),
842 };
843
844 static const struct iio_chan_spec ad7193_channels[] = {
845 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
846 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
847 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M),
848 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M),
849 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP),
850 AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M),
851 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1),
852 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2),
853 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3),
854 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4),
855 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5),
856 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6),
857 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7),
858 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8),
859 IIO_CHAN_SOFT_TIMESTAMP(14),
860 };
861
862 static int ad7192_channels_config(struct iio_dev *indio_dev)
863 {
864 struct ad7192_state *st = iio_priv(indio_dev);
865
866 switch (st->devid) {
867 case ID_AD7193:
868 indio_dev->channels = ad7193_channels;
869 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
870 break;
871 default:
872 indio_dev->channels = ad7192_channels;
873 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
874 break;
875 }
876
877 return 0;
878 }
879
880 static const struct of_device_id ad7192_of_match[] = {
881 { .compatible = "adi,ad7190", .data = (void *)ID_AD7190 },
882 { .compatible = "adi,ad7192", .data = (void *)ID_AD7192 },
883 { .compatible = "adi,ad7193", .data = (void *)ID_AD7193 },
884 { .compatible = "adi,ad7195", .data = (void *)ID_AD7195 },
885 {}
886 };
887 MODULE_DEVICE_TABLE(of, ad7192_of_match);
888
889 static int ad7192_probe(struct spi_device *spi)
890 {
891 struct ad7192_state *st;
892 struct iio_dev *indio_dev;
893 int ret, voltage_uv = 0;
894
895 if (!spi->irq) {
896 dev_err(&spi->dev, "no IRQ?\n");
897 return -ENODEV;
898 }
899
900 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
901 if (!indio_dev)
902 return -ENOMEM;
903
904 st = iio_priv(indio_dev);
905
906 mutex_init(&st->lock);
907
908 st->avdd = devm_regulator_get(&spi->dev, "avdd");
909 if (IS_ERR(st->avdd))
910 return PTR_ERR(st->avdd);
911
912 ret = regulator_enable(st->avdd);
913 if (ret) {
914 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
915 return ret;
916 }
917
918 st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
919 if (IS_ERR(st->dvdd)) {
920 ret = PTR_ERR(st->dvdd);
921 goto error_disable_avdd;
922 }
923
924 ret = regulator_enable(st->dvdd);
925 if (ret) {
926 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n");
927 goto error_disable_avdd;
928 }
929
930 voltage_uv = regulator_get_voltage(st->avdd);
931
932 if (voltage_uv > 0) {
933 st->int_vref_mv = voltage_uv / 1000;
934 } else {
935 ret = voltage_uv;
936 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n");
937 goto error_disable_avdd;
938 }
939
940 spi_set_drvdata(spi, indio_dev);
941 st->devid = (unsigned long)of_device_get_match_data(&spi->dev);
942 indio_dev->dev.parent = &spi->dev;
943 indio_dev->name = spi_get_device_id(spi)->name;
944 indio_dev->modes = INDIO_DIRECT_MODE;
945
946 ret = ad7192_channels_config(indio_dev);
947 if (ret < 0)
948 goto error_disable_dvdd;
949
950 if (st->devid == ID_AD7195)
951 indio_dev->info = &ad7195_info;
952 else
953 indio_dev->info = &ad7192_info;
954
955 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
956
957 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
958 if (ret)
959 goto error_disable_dvdd;
960
961 st->fclk = AD7192_INT_FREQ_MHZ;
962
963 st->mclk = devm_clk_get(&st->sd.spi->dev, "mclk");
964 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT) {
965 ret = PTR_ERR(st->mclk);
966 goto error_remove_trigger;
967 }
968
969 st->clock_sel = ad7192_of_clock_select(st);
970
971 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 ||
972 st->clock_sel == AD7192_CLK_EXT_MCLK2) {
973 ret = clk_prepare_enable(st->mclk);
974 if (ret < 0)
975 goto error_remove_trigger;
976
977 st->fclk = clk_get_rate(st->mclk);
978 if (!ad7192_valid_external_frequency(st->fclk)) {
979 ret = -EINVAL;
980 dev_err(&spi->dev,
981 "External clock frequency out of bounds\n");
982 goto error_disable_clk;
983 }
984 }
985
986 ret = ad7192_setup(st, spi->dev.of_node);
987 if (ret)
988 goto error_disable_clk;
989
990 ret = iio_device_register(indio_dev);
991 if (ret < 0)
992 goto error_disable_clk;
993 return 0;
994
995 error_disable_clk:
996 clk_disable_unprepare(st->mclk);
997 error_remove_trigger:
998 ad_sd_cleanup_buffer_and_trigger(indio_dev);
999 error_disable_dvdd:
1000 regulator_disable(st->dvdd);
1001 error_disable_avdd:
1002 regulator_disable(st->avdd);
1003
1004 return ret;
1005 }
1006
1007 static int ad7192_remove(struct spi_device *spi)
1008 {
1009 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1010 struct ad7192_state *st = iio_priv(indio_dev);
1011
1012 iio_device_unregister(indio_dev);
1013 clk_disable_unprepare(st->mclk);
1014 ad_sd_cleanup_buffer_and_trigger(indio_dev);
1015
1016 regulator_disable(st->dvdd);
1017 regulator_disable(st->avdd);
1018
1019 return 0;
1020 }
1021
1022 static struct spi_driver ad7192_driver = {
1023 .driver = {
1024 .name = "ad7192",
1025 .of_match_table = ad7192_of_match,
1026 },
1027 .probe = ad7192_probe,
1028 .remove = ad7192_remove,
1029 };
1030 module_spi_driver(ad7192_driver);
1031
1032 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
1033 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
1034 MODULE_LICENSE("GPL v2");
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