1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2014 Philippe Reynes
6 * based on linux/drivers/iio/ad7923.c
7 * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
8 * Copyright 2012 CS Systemes d'Information
12 * Partial support for max1027 and similar chips.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spi/spi.h>
18 #include <linux/delay.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/buffer.h>
22 #include <linux/iio/trigger.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
26 #define MAX1027_CONV_REG BIT(7)
27 #define MAX1027_SETUP_REG BIT(6)
28 #define MAX1027_AVG_REG BIT(5)
29 #define MAX1027_RST_REG BIT(4)
31 /* conversion register */
32 #define MAX1027_TEMP BIT(0)
33 #define MAX1027_SCAN_0_N (0x00 << 1)
34 #define MAX1027_SCAN_N_M (0x01 << 1)
35 #define MAX1027_SCAN_N (0x02 << 1)
36 #define MAX1027_NOSCAN (0x03 << 1)
37 #define MAX1027_CHAN(n) ((n) << 3)
40 #define MAX1027_UNIPOLAR 0x02
41 #define MAX1027_BIPOLAR 0x03
42 #define MAX1027_REF_MODE0 (0x00 << 2)
43 #define MAX1027_REF_MODE1 (0x01 << 2)
44 #define MAX1027_REF_MODE2 (0x02 << 2)
45 #define MAX1027_REF_MODE3 (0x03 << 2)
46 #define MAX1027_CKS_MODE0 (0x00 << 4)
47 #define MAX1027_CKS_MODE1 (0x01 << 4)
48 #define MAX1027_CKS_MODE2 (0x02 << 4)
49 #define MAX1027_CKS_MODE3 (0x03 << 4)
51 /* averaging register */
52 #define MAX1027_NSCAN_4 0x00
53 #define MAX1027_NSCAN_8 0x01
54 #define MAX1027_NSCAN_12 0x02
55 #define MAX1027_NSCAN_16 0x03
56 #define MAX1027_NAVG_4 (0x00 << 2)
57 #define MAX1027_NAVG_8 (0x01 << 2)
58 #define MAX1027_NAVG_16 (0x02 << 2)
59 #define MAX1027_NAVG_32 (0x03 << 2)
60 #define MAX1027_AVG_EN BIT(4)
68 static const struct spi_device_id max1027_id
[] = {
74 MODULE_DEVICE_TABLE(spi
, max1027_id
);
77 static const struct of_device_id max1027_adc_dt_ids
[] = {
78 { .compatible
= "maxim,max1027" },
79 { .compatible
= "maxim,max1029" },
80 { .compatible
= "maxim,max1031" },
83 MODULE_DEVICE_TABLE(of
, max1027_adc_dt_ids
);
86 #define MAX1027_V_CHAN(index) \
88 .type = IIO_VOLTAGE, \
91 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
92 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
93 .scan_index = index + 1, \
99 .endianness = IIO_BE, \
103 #define MAX1027_T_CHAN \
107 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
108 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
114 .endianness = IIO_BE, \
118 static const struct iio_chan_spec max1027_channels
[] = {
130 static const struct iio_chan_spec max1029_channels
[] = {
146 static const struct iio_chan_spec max1031_channels
[] = {
166 static const unsigned long max1027_available_scan_masks
[] = {
171 static const unsigned long max1029_available_scan_masks
[] = {
176 static const unsigned long max1031_available_scan_masks
[] = {
181 struct max1027_chip_info
{
182 const struct iio_chan_spec
*channels
;
183 unsigned int num_channels
;
184 const unsigned long *available_scan_masks
;
187 static const struct max1027_chip_info max1027_chip_info_tbl
[] = {
189 .channels
= max1027_channels
,
190 .num_channels
= ARRAY_SIZE(max1027_channels
),
191 .available_scan_masks
= max1027_available_scan_masks
,
194 .channels
= max1029_channels
,
195 .num_channels
= ARRAY_SIZE(max1029_channels
),
196 .available_scan_masks
= max1029_available_scan_masks
,
199 .channels
= max1031_channels
,
200 .num_channels
= ARRAY_SIZE(max1031_channels
),
201 .available_scan_masks
= max1031_available_scan_masks
,
205 struct max1027_state
{
206 const struct max1027_chip_info
*info
;
207 struct spi_device
*spi
;
208 struct iio_trigger
*trig
;
212 u8 reg ____cacheline_aligned
;
215 static int max1027_read_single_value(struct iio_dev
*indio_dev
,
216 struct iio_chan_spec
const *chan
,
220 struct max1027_state
*st
= iio_priv(indio_dev
);
222 if (iio_buffer_enabled(indio_dev
)) {
223 dev_warn(&indio_dev
->dev
, "trigger mode already enabled");
227 /* Start acquisition on conversion register write */
228 st
->reg
= MAX1027_SETUP_REG
| MAX1027_REF_MODE2
| MAX1027_CKS_MODE2
;
229 ret
= spi_write(st
->spi
, &st
->reg
, 1);
231 dev_err(&indio_dev
->dev
,
232 "Failed to configure setup register\n");
236 /* Configure conversion register with the requested chan */
237 st
->reg
= MAX1027_CONV_REG
| MAX1027_CHAN(chan
->channel
) |
239 if (chan
->type
== IIO_TEMP
)
240 st
->reg
|= MAX1027_TEMP
;
241 ret
= spi_write(st
->spi
, &st
->reg
, 1);
243 dev_err(&indio_dev
->dev
,
244 "Failed to configure conversion register\n");
249 * For an unknown reason, when we use the mode "10" (write
250 * conversion register), the interrupt doesn't occur every time.
251 * So we just wait 1 ms.
256 ret
= spi_read(st
->spi
, st
->buffer
, (chan
->type
== IIO_TEMP
) ? 4 : 2);
260 *val
= be16_to_cpu(st
->buffer
[0]);
265 static int max1027_read_raw(struct iio_dev
*indio_dev
,
266 struct iio_chan_spec
const *chan
,
267 int *val
, int *val2
, long mask
)
270 struct max1027_state
*st
= iio_priv(indio_dev
);
272 mutex_lock(&st
->lock
);
275 case IIO_CHAN_INFO_RAW
:
276 ret
= max1027_read_single_value(indio_dev
, chan
, val
);
278 case IIO_CHAN_INFO_SCALE
:
279 switch (chan
->type
) {
283 ret
= IIO_VAL_FRACTIONAL
;
288 ret
= IIO_VAL_FRACTIONAL_LOG2
;
300 mutex_unlock(&st
->lock
);
305 static int max1027_debugfs_reg_access(struct iio_dev
*indio_dev
,
306 unsigned reg
, unsigned writeval
,
309 struct max1027_state
*st
= iio_priv(indio_dev
);
310 u8
*val
= (u8
*)st
->buffer
;
316 return spi_write(st
->spi
, val
, 1);
319 static int max1027_validate_trigger(struct iio_dev
*indio_dev
,
320 struct iio_trigger
*trig
)
322 struct max1027_state
*st
= iio_priv(indio_dev
);
324 if (st
->trig
!= trig
)
330 static int max1027_set_trigger_state(struct iio_trigger
*trig
, bool state
)
332 struct iio_dev
*indio_dev
= iio_trigger_get_drvdata(trig
);
333 struct max1027_state
*st
= iio_priv(indio_dev
);
337 /* Start acquisition on cnvst */
338 st
->reg
= MAX1027_SETUP_REG
| MAX1027_CKS_MODE0
|
340 ret
= spi_write(st
->spi
, &st
->reg
, 1);
344 /* Scan from 0 to max */
345 st
->reg
= MAX1027_CONV_REG
| MAX1027_CHAN(0) |
346 MAX1027_SCAN_N_M
| MAX1027_TEMP
;
347 ret
= spi_write(st
->spi
, &st
->reg
, 1);
351 /* Start acquisition on conversion register write */
352 st
->reg
= MAX1027_SETUP_REG
| MAX1027_CKS_MODE2
|
354 ret
= spi_write(st
->spi
, &st
->reg
, 1);
362 static irqreturn_t
max1027_trigger_handler(int irq
, void *private)
364 struct iio_poll_func
*pf
= private;
365 struct iio_dev
*indio_dev
= pf
->indio_dev
;
366 struct max1027_state
*st
= iio_priv(indio_dev
);
368 pr_debug("%s(irq=%d, private=0x%p)\n", __func__
, irq
, private);
370 /* fill buffer with all channel */
371 spi_read(st
->spi
, st
->buffer
, indio_dev
->masklength
* 2);
373 iio_push_to_buffers(indio_dev
, st
->buffer
);
375 iio_trigger_notify_done(indio_dev
->trig
);
380 static const struct iio_trigger_ops max1027_trigger_ops
= {
381 .validate_device
= &iio_trigger_validate_own_device
,
382 .set_trigger_state
= &max1027_set_trigger_state
,
385 static const struct iio_info max1027_info
= {
386 .read_raw
= &max1027_read_raw
,
387 .validate_trigger
= &max1027_validate_trigger
,
388 .debugfs_reg_access
= &max1027_debugfs_reg_access
,
391 static int max1027_probe(struct spi_device
*spi
)
394 struct iio_dev
*indio_dev
;
395 struct max1027_state
*st
;
397 pr_debug("%s: probe(spi = 0x%p)\n", __func__
, spi
);
399 indio_dev
= devm_iio_device_alloc(&spi
->dev
, sizeof(*st
));
400 if (indio_dev
== NULL
) {
401 pr_err("Can't allocate iio device\n");
405 spi_set_drvdata(spi
, indio_dev
);
407 st
= iio_priv(indio_dev
);
409 st
->info
= &max1027_chip_info_tbl
[spi_get_device_id(spi
)->driver_data
];
411 mutex_init(&st
->lock
);
413 indio_dev
->name
= spi_get_device_id(spi
)->name
;
414 indio_dev
->dev
.parent
= &spi
->dev
;
415 indio_dev
->dev
.of_node
= spi
->dev
.of_node
;
416 indio_dev
->info
= &max1027_info
;
417 indio_dev
->modes
= INDIO_DIRECT_MODE
;
418 indio_dev
->channels
= st
->info
->channels
;
419 indio_dev
->num_channels
= st
->info
->num_channels
;
420 indio_dev
->available_scan_masks
= st
->info
->available_scan_masks
;
422 st
->buffer
= devm_kmalloc_array(&indio_dev
->dev
,
423 indio_dev
->num_channels
, 2,
425 if (st
->buffer
== NULL
) {
426 dev_err(&indio_dev
->dev
, "Can't allocate buffer\n");
430 ret
= iio_triggered_buffer_setup(indio_dev
, &iio_pollfunc_store_time
,
431 &max1027_trigger_handler
, NULL
);
433 dev_err(&indio_dev
->dev
, "Failed to setup buffer\n");
437 st
->trig
= devm_iio_trigger_alloc(&spi
->dev
, "%s-trigger",
439 if (st
->trig
== NULL
) {
441 dev_err(&indio_dev
->dev
, "Failed to allocate iio trigger\n");
442 goto fail_trigger_alloc
;
445 st
->trig
->ops
= &max1027_trigger_ops
;
446 st
->trig
->dev
.parent
= &spi
->dev
;
447 iio_trigger_set_drvdata(st
->trig
, indio_dev
);
448 iio_trigger_register(st
->trig
);
450 ret
= devm_request_threaded_irq(&spi
->dev
, spi
->irq
,
451 iio_trigger_generic_data_rdy_poll
,
453 IRQF_TRIGGER_FALLING
,
454 spi
->dev
.driver
->name
, st
->trig
);
456 dev_err(&indio_dev
->dev
, "Failed to allocate IRQ.\n");
457 goto fail_dev_register
;
460 /* Disable averaging */
461 st
->reg
= MAX1027_AVG_REG
;
462 ret
= spi_write(st
->spi
, &st
->reg
, 1);
464 dev_err(&indio_dev
->dev
, "Failed to configure averaging register\n");
465 goto fail_dev_register
;
468 ret
= iio_device_register(indio_dev
);
470 dev_err(&indio_dev
->dev
, "Failed to register iio device\n");
471 goto fail_dev_register
;
478 iio_triggered_buffer_cleanup(indio_dev
);
483 static int max1027_remove(struct spi_device
*spi
)
485 struct iio_dev
*indio_dev
= spi_get_drvdata(spi
);
487 pr_debug("%s: remove(spi = 0x%p)\n", __func__
, spi
);
489 iio_device_unregister(indio_dev
);
490 iio_triggered_buffer_cleanup(indio_dev
);
495 static struct spi_driver max1027_driver
= {
498 .of_match_table
= of_match_ptr(max1027_adc_dt_ids
),
500 .probe
= max1027_probe
,
501 .remove
= max1027_remove
,
502 .id_table
= max1027_id
,
504 module_spi_driver(max1027_driver
);
506 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
507 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
508 MODULE_LICENSE("GPL v2");