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Merge tag 'x86-fpu-2020-06-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
[thirdparty/linux.git] / drivers / iio / adc / stm32-dfsdm-adc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is the ADC part of the STM32 DFSDM driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
7 */
8
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
12 #include <linux/iio/buffer.h>
13 #include <linux/iio/hw-consumer.h>
14 #include <linux/iio/sysfs.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26
27 #include "stm32-dfsdm.h"
28
29 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
30
31 /* Conversion timeout */
32 #define DFSDM_TIMEOUT_US 100000
33 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
34
35 /* Oversampling attribute default */
36 #define DFSDM_DEFAULT_OVERSAMPLING 100
37
38 /* Oversampling max values */
39 #define DFSDM_MAX_INT_OVERSAMPLING 256
40 #define DFSDM_MAX_FL_OVERSAMPLING 1024
41
42 /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
43 #define DFSDM_DATA_MAX BIT(30)
44 /*
45 * Data are output as two's complement data in a 24 bit field.
46 * Data from filters are in the range +/-2^(n-1)
47 * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
48 * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
49 * So, the resolution of samples from filter is actually limited to 23 bits
50 */
51 #define DFSDM_DATA_RES 24
52
53 /* Filter configuration */
54 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
55 DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
56 DFSDM_CR1_JSCAN_MASK)
57
58 enum sd_converter_type {
59 DFSDM_AUDIO,
60 DFSDM_IIO,
61 };
62
63 struct stm32_dfsdm_dev_data {
64 int type;
65 int (*init)(struct device *dev, struct iio_dev *indio_dev);
66 unsigned int num_channels;
67 const struct regmap_config *regmap_cfg;
68 };
69
70 struct stm32_dfsdm_adc {
71 struct stm32_dfsdm *dfsdm;
72 const struct stm32_dfsdm_dev_data *dev_data;
73 unsigned int fl_id;
74 unsigned int nconv;
75 unsigned long smask;
76
77 /* ADC specific */
78 unsigned int oversamp;
79 struct iio_hw_consumer *hwc;
80 struct completion completion;
81 u32 *buffer;
82
83 /* Audio specific */
84 unsigned int spi_freq; /* SPI bus clock frequency */
85 unsigned int sample_freq; /* Sample frequency after filter decimation */
86 int (*cb)(const void *data, size_t size, void *cb_priv);
87 void *cb_priv;
88
89 /* DMA */
90 u8 *rx_buf;
91 unsigned int bufi; /* Buffer current position */
92 unsigned int buf_sz; /* Buffer size */
93 struct dma_chan *dma_chan;
94 dma_addr_t dma_buf;
95 };
96
97 struct stm32_dfsdm_str2field {
98 const char *name;
99 unsigned int val;
100 };
101
102 /* DFSDM channel serial interface type */
103 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
104 { "SPI_R", 0 }, /* SPI with data on rising edge */
105 { "SPI_F", 1 }, /* SPI with data on falling edge */
106 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
107 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
108 {},
109 };
110
111 /* DFSDM channel clock source */
112 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
113 /* External SPI clock (CLKIN x) */
114 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
115 /* Internal SPI clock (CLKOUT) */
116 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
117 /* Internal SPI clock divided by 2 (falling edge) */
118 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
119 /* Internal SPI clock divided by 2 (falling edge) */
120 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
121 {},
122 };
123
124 static int stm32_dfsdm_str2val(const char *str,
125 const struct stm32_dfsdm_str2field *list)
126 {
127 const struct stm32_dfsdm_str2field *p = list;
128
129 for (p = list; p && p->name; p++)
130 if (!strcmp(p->name, str))
131 return p->val;
132
133 return -EINVAL;
134 }
135
136 /**
137 * struct stm32_dfsdm_trig_info - DFSDM trigger info
138 * @name: name of the trigger, corresponding to its source
139 * @jextsel: trigger signal selection
140 */
141 struct stm32_dfsdm_trig_info {
142 const char *name;
143 unsigned int jextsel;
144 };
145
146 /* hardware injected trigger enable, edge selection */
147 enum stm32_dfsdm_jexten {
148 STM32_DFSDM_JEXTEN_DISABLED,
149 STM32_DFSDM_JEXTEN_RISING_EDGE,
150 STM32_DFSDM_JEXTEN_FALLING_EDGE,
151 STM32_DFSDM_EXTEN_BOTH_EDGES,
152 };
153
154 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
155 { TIM1_TRGO, 0 },
156 { TIM1_TRGO2, 1 },
157 { TIM8_TRGO, 2 },
158 { TIM8_TRGO2, 3 },
159 { TIM3_TRGO, 4 },
160 { TIM4_TRGO, 5 },
161 { TIM16_OC1, 6 },
162 { TIM6_TRGO, 7 },
163 { TIM7_TRGO, 8 },
164 { LPTIM1_OUT, 26 },
165 { LPTIM2_OUT, 27 },
166 { LPTIM3_OUT, 28 },
167 {},
168 };
169
170 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
171 struct iio_trigger *trig)
172 {
173 int i;
174
175 /* lookup triggers registered by stm32 timer trigger driver */
176 for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
177 /**
178 * Checking both stm32 timer trigger type and trig name
179 * should be safe against arbitrary trigger names.
180 */
181 if ((is_stm32_timer_trigger(trig) ||
182 is_stm32_lptim_trigger(trig)) &&
183 !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
184 return stm32_dfsdm_trigs[i].jextsel;
185 }
186 }
187
188 return -EINVAL;
189 }
190
191 static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
192 unsigned int fast, unsigned int oversamp)
193 {
194 unsigned int i, d, fosr, iosr;
195 u64 res, max;
196 int bits, shift;
197 unsigned int m = 1; /* multiplication factor */
198 unsigned int p = fl->ford; /* filter order (ford) */
199 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
200
201 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
202 /*
203 * This function tries to compute filter oversampling and integrator
204 * oversampling, base on oversampling ratio requested by user.
205 *
206 * Decimation d depends on the filter order and the oversampling ratios.
207 * ford: filter order
208 * fosr: filter over sampling ratio
209 * iosr: integrator over sampling ratio
210 */
211 if (fl->ford == DFSDM_FASTSINC_ORDER) {
212 m = 2;
213 p = 2;
214 }
215
216 /*
217 * Look for filter and integrator oversampling ratios which allows
218 * to maximize data output resolution.
219 */
220 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
221 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
222 if (fast)
223 d = fosr * iosr;
224 else if (fl->ford == DFSDM_FASTSINC_ORDER)
225 d = fosr * (iosr + 3) + 2;
226 else
227 d = fosr * (iosr - 1 + p) + p;
228
229 if (d > oversamp)
230 break;
231 else if (d != oversamp)
232 continue;
233 /*
234 * Check resolution (limited to signed 32 bits)
235 * res <= 2^31
236 * Sincx filters:
237 * res = m * fosr^p x iosr (with m=1, p=ford)
238 * FastSinc filter
239 * res = m * fosr^p x iosr (with m=2, p=2)
240 */
241 res = fosr;
242 for (i = p - 1; i > 0; i--) {
243 res = res * (u64)fosr;
244 if (res > DFSDM_DATA_MAX)
245 break;
246 }
247 if (res > DFSDM_DATA_MAX)
248 continue;
249
250 res = res * (u64)m * (u64)iosr;
251 if (res > DFSDM_DATA_MAX)
252 continue;
253
254 if (res >= flo->res) {
255 flo->res = res;
256 flo->fosr = fosr;
257 flo->iosr = iosr;
258
259 bits = fls(flo->res);
260 /* 8 LBSs in data register contain chan info */
261 max = flo->res << 8;
262
263 /* if resolution is not a power of two */
264 if (flo->res > BIT(bits - 1))
265 bits++;
266 else
267 max--;
268
269 shift = DFSDM_DATA_RES - bits;
270 /*
271 * Compute right/left shift
272 * Right shift is performed by hardware
273 * when transferring samples to data register.
274 * Left shift is done by software on buffer
275 */
276 if (shift > 0) {
277 /* Resolution is lower than 24 bits */
278 flo->rshift = 0;
279 flo->lshift = shift;
280 } else {
281 /*
282 * If resolution is 24 bits or more,
283 * max positive value may be ambiguous
284 * (equal to max negative value as sign
285 * bit is dropped).
286 * Reduce resolution to 23 bits (rshift)
287 * to keep the sign on bit 23 and treat
288 * saturation before rescaling on 24
289 * bits (lshift).
290 */
291 flo->rshift = 1 - shift;
292 flo->lshift = 1;
293 max >>= flo->rshift;
294 }
295 flo->max = (s32)max;
296
297 pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
298 __func__, fast, flo->fosr, flo->iosr,
299 flo->res, bits, flo->rshift,
300 flo->lshift);
301 }
302 }
303 }
304
305 if (!flo->res)
306 return -EINVAL;
307
308 return 0;
309 }
310
311 static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
312 unsigned int oversamp)
313 {
314 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
315 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
316 int ret0, ret1;
317
318 memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
319 memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
320
321 ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
322 ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
323 if (ret0 < 0 && ret1 < 0) {
324 dev_err(&indio_dev->dev,
325 "Filter parameters not found: errors %d/%d\n",
326 ret0, ret1);
327 return -EINVAL;
328 }
329
330 return 0;
331 }
332
333 static int stm32_dfsdm_start_channel(struct stm32_dfsdm_adc *adc)
334 {
335 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
336 struct regmap *regmap = adc->dfsdm->regmap;
337 const struct iio_chan_spec *chan;
338 unsigned int bit;
339 int ret;
340
341 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
342 chan = indio_dev->channels + bit;
343 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
344 DFSDM_CHCFGR1_CHEN_MASK,
345 DFSDM_CHCFGR1_CHEN(1));
346 if (ret < 0)
347 return ret;
348 }
349
350 return 0;
351 }
352
353 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm_adc *adc)
354 {
355 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
356 struct regmap *regmap = adc->dfsdm->regmap;
357 const struct iio_chan_spec *chan;
358 unsigned int bit;
359
360 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
361 chan = indio_dev->channels + bit;
362 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
363 DFSDM_CHCFGR1_CHEN_MASK,
364 DFSDM_CHCFGR1_CHEN(0));
365 }
366 }
367
368 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
369 struct stm32_dfsdm_channel *ch)
370 {
371 unsigned int id = ch->id;
372 struct regmap *regmap = dfsdm->regmap;
373 int ret;
374
375 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
376 DFSDM_CHCFGR1_SITP_MASK,
377 DFSDM_CHCFGR1_SITP(ch->type));
378 if (ret < 0)
379 return ret;
380 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
381 DFSDM_CHCFGR1_SPICKSEL_MASK,
382 DFSDM_CHCFGR1_SPICKSEL(ch->src));
383 if (ret < 0)
384 return ret;
385 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
386 DFSDM_CHCFGR1_CHINSEL_MASK,
387 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
388 }
389
390 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
391 unsigned int fl_id,
392 struct iio_trigger *trig)
393 {
394 struct stm32_dfsdm *dfsdm = adc->dfsdm;
395 int ret;
396
397 /* Enable filter */
398 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
399 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
400 if (ret < 0)
401 return ret;
402
403 /* Nothing more to do for injected (scan mode/triggered) conversions */
404 if (adc->nconv > 1 || trig)
405 return 0;
406
407 /* Software start (single or continuous) regular conversion */
408 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
409 DFSDM_CR1_RSWSTART_MASK,
410 DFSDM_CR1_RSWSTART(1));
411 }
412
413 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
414 unsigned int fl_id)
415 {
416 /* Disable conversion */
417 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
418 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
419 }
420
421 static int stm32_dfsdm_filter_set_trig(struct stm32_dfsdm_adc *adc,
422 unsigned int fl_id,
423 struct iio_trigger *trig)
424 {
425 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
426 struct regmap *regmap = adc->dfsdm->regmap;
427 u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
428 int ret;
429
430 if (trig) {
431 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
432 if (ret < 0)
433 return ret;
434
435 /* set trigger source and polarity (default to rising edge) */
436 jextsel = ret;
437 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
438 }
439
440 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
441 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
442 DFSDM_CR1_JEXTSEL(jextsel) |
443 DFSDM_CR1_JEXTEN(jexten));
444 if (ret < 0)
445 return ret;
446
447 return 0;
448 }
449
450 static int stm32_dfsdm_channels_configure(struct stm32_dfsdm_adc *adc,
451 unsigned int fl_id,
452 struct iio_trigger *trig)
453 {
454 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
455 struct regmap *regmap = adc->dfsdm->regmap;
456 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
457 struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
458 const struct iio_chan_spec *chan;
459 unsigned int bit;
460 int ret;
461
462 fl->fast = 0;
463
464 /*
465 * In continuous mode, use fast mode configuration,
466 * if it provides a better resolution.
467 */
468 if (adc->nconv == 1 && !trig &&
469 (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
470 if (fl->flo[1].res >= fl->flo[0].res) {
471 fl->fast = 1;
472 flo = &fl->flo[1];
473 }
474 }
475
476 if (!flo->res)
477 return -EINVAL;
478
479 for_each_set_bit(bit, &adc->smask,
480 sizeof(adc->smask) * BITS_PER_BYTE) {
481 chan = indio_dev->channels + bit;
482
483 ret = regmap_update_bits(regmap,
484 DFSDM_CHCFGR2(chan->channel),
485 DFSDM_CHCFGR2_DTRBS_MASK,
486 DFSDM_CHCFGR2_DTRBS(flo->rshift));
487 if (ret)
488 return ret;
489 }
490
491 return 0;
492 }
493
494 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm_adc *adc,
495 unsigned int fl_id,
496 struct iio_trigger *trig)
497 {
498 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
499 struct regmap *regmap = adc->dfsdm->regmap;
500 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
501 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
502 u32 cr1;
503 const struct iio_chan_spec *chan;
504 unsigned int bit, jchg = 0;
505 int ret;
506
507 /* Average integrator oversampling */
508 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
509 DFSDM_FCR_IOSR(flo->iosr - 1));
510 if (ret)
511 return ret;
512
513 /* Filter order and Oversampling */
514 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
515 DFSDM_FCR_FOSR(flo->fosr - 1));
516 if (ret)
517 return ret;
518
519 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
520 DFSDM_FCR_FORD(fl->ford));
521 if (ret)
522 return ret;
523
524 ret = stm32_dfsdm_filter_set_trig(adc, fl_id, trig);
525 if (ret)
526 return ret;
527
528 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
529 DFSDM_CR1_FAST_MASK,
530 DFSDM_CR1_FAST(fl->fast));
531 if (ret)
532 return ret;
533
534 /*
535 * DFSDM modes configuration W.R.T audio/iio type modes
536 * ----------------------------------------------------------------
537 * Modes | regular | regular | injected | injected |
538 * | | continuous | | + scan |
539 * --------------|---------|--------------|----------|------------|
540 * single conv | x | | | |
541 * (1 chan) | | | | |
542 * --------------|---------|--------------|----------|------------|
543 * 1 Audio chan | | sample freq | | |
544 * | | or sync_mode | | |
545 * --------------|---------|--------------|----------|------------|
546 * 1 IIO chan | | sample freq | trigger | |
547 * | | or sync_mode | | |
548 * --------------|---------|--------------|----------|------------|
549 * 2+ IIO chans | | | | trigger or |
550 * | | | | sync_mode |
551 * ----------------------------------------------------------------
552 */
553 if (adc->nconv == 1 && !trig) {
554 bit = __ffs(adc->smask);
555 chan = indio_dev->channels + bit;
556
557 /* Use regular conversion for single channel without trigger */
558 cr1 = DFSDM_CR1_RCH(chan->channel);
559
560 /* Continuous conversions triggered by SPI clk in buffer mode */
561 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
562 cr1 |= DFSDM_CR1_RCONT(1);
563
564 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
565 } else {
566 /* Use injected conversion for multiple channels */
567 for_each_set_bit(bit, &adc->smask,
568 sizeof(adc->smask) * BITS_PER_BYTE) {
569 chan = indio_dev->channels + bit;
570 jchg |= BIT(chan->channel);
571 }
572 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
573 if (ret < 0)
574 return ret;
575
576 /* Use scan mode for multiple channels */
577 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
578
579 /*
580 * Continuous conversions not supported in injected mode,
581 * either use:
582 * - conversions in sync with filter 0
583 * - triggered conversions
584 */
585 if (!fl->sync_mode && !trig)
586 return -EINVAL;
587 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
588 }
589
590 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
591 cr1);
592 }
593
594 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
595 struct iio_dev *indio_dev,
596 struct iio_chan_spec *ch)
597 {
598 struct stm32_dfsdm_channel *df_ch;
599 const char *of_str;
600 int chan_idx = ch->scan_index;
601 int ret, val;
602
603 ret = of_property_read_u32_index(indio_dev->dev.of_node,
604 "st,adc-channels", chan_idx,
605 &ch->channel);
606 if (ret < 0) {
607 dev_err(&indio_dev->dev,
608 " Error parsing 'st,adc-channels' for idx %d\n",
609 chan_idx);
610 return ret;
611 }
612 if (ch->channel >= dfsdm->num_chs) {
613 dev_err(&indio_dev->dev,
614 " Error bad channel number %d (max = %d)\n",
615 ch->channel, dfsdm->num_chs);
616 return -EINVAL;
617 }
618
619 ret = of_property_read_string_index(indio_dev->dev.of_node,
620 "st,adc-channel-names", chan_idx,
621 &ch->datasheet_name);
622 if (ret < 0) {
623 dev_err(&indio_dev->dev,
624 " Error parsing 'st,adc-channel-names' for idx %d\n",
625 chan_idx);
626 return ret;
627 }
628
629 df_ch = &dfsdm->ch_list[ch->channel];
630 df_ch->id = ch->channel;
631
632 ret = of_property_read_string_index(indio_dev->dev.of_node,
633 "st,adc-channel-types", chan_idx,
634 &of_str);
635 if (!ret) {
636 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
637 if (val < 0)
638 return val;
639 } else {
640 val = 0;
641 }
642 df_ch->type = val;
643
644 ret = of_property_read_string_index(indio_dev->dev.of_node,
645 "st,adc-channel-clk-src", chan_idx,
646 &of_str);
647 if (!ret) {
648 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
649 if (val < 0)
650 return val;
651 } else {
652 val = 0;
653 }
654 df_ch->src = val;
655
656 ret = of_property_read_u32_index(indio_dev->dev.of_node,
657 "st,adc-alt-channel", chan_idx,
658 &df_ch->alt_si);
659 if (ret < 0)
660 df_ch->alt_si = 0;
661
662 return 0;
663 }
664
665 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
666 uintptr_t priv,
667 const struct iio_chan_spec *chan,
668 char *buf)
669 {
670 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
671
672 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
673 }
674
675 static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
676 unsigned int sample_freq,
677 unsigned int spi_freq)
678 {
679 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
680 unsigned int oversamp;
681 int ret;
682
683 oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
684 if (spi_freq % sample_freq)
685 dev_dbg(&indio_dev->dev,
686 "Rate not accurate. requested (%u), actual (%u)\n",
687 sample_freq, spi_freq / oversamp);
688
689 ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
690 if (ret < 0)
691 return ret;
692
693 adc->sample_freq = spi_freq / oversamp;
694 adc->oversamp = oversamp;
695
696 return 0;
697 }
698
699 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
700 uintptr_t priv,
701 const struct iio_chan_spec *chan,
702 const char *buf, size_t len)
703 {
704 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
705 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
706 unsigned int sample_freq = adc->sample_freq;
707 unsigned int spi_freq;
708 int ret;
709
710 dev_err(&indio_dev->dev, "enter %s\n", __func__);
711 /* If DFSDM is master on SPI, SPI freq can not be updated */
712 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
713 return -EPERM;
714
715 ret = kstrtoint(buf, 0, &spi_freq);
716 if (ret)
717 return ret;
718
719 if (!spi_freq)
720 return -EINVAL;
721
722 if (sample_freq) {
723 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
724 if (ret < 0)
725 return ret;
726 }
727 adc->spi_freq = spi_freq;
728
729 return len;
730 }
731
732 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
733 struct iio_trigger *trig)
734 {
735 struct regmap *regmap = adc->dfsdm->regmap;
736 int ret;
737
738 ret = stm32_dfsdm_channels_configure(adc, adc->fl_id, trig);
739 if (ret < 0)
740 return ret;
741
742 ret = stm32_dfsdm_start_channel(adc);
743 if (ret < 0)
744 return ret;
745
746 ret = stm32_dfsdm_filter_configure(adc, adc->fl_id, trig);
747 if (ret < 0)
748 goto stop_channels;
749
750 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
751 if (ret < 0)
752 goto filter_unconfigure;
753
754 return 0;
755
756 filter_unconfigure:
757 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
758 DFSDM_CR1_CFG_MASK, 0);
759 stop_channels:
760 stm32_dfsdm_stop_channel(adc);
761
762 return ret;
763 }
764
765 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc)
766 {
767 struct regmap *regmap = adc->dfsdm->regmap;
768
769 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
770
771 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
772 DFSDM_CR1_CFG_MASK, 0);
773
774 stm32_dfsdm_stop_channel(adc);
775 }
776
777 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
778 unsigned int val)
779 {
780 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
781 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
782 unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
783
784 /*
785 * DMA cyclic transfers are used, buffer is split into two periods.
786 * There should be :
787 * - always one buffer (period) DMA is working on
788 * - one buffer (period) driver pushed to ASoC side.
789 */
790 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
791 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
792
793 return 0;
794 }
795
796 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
797 {
798 struct dma_tx_state state;
799 enum dma_status status;
800
801 status = dmaengine_tx_status(adc->dma_chan,
802 adc->dma_chan->cookie,
803 &state);
804 if (status == DMA_IN_PROGRESS) {
805 /* Residue is size in bytes from end of buffer */
806 unsigned int i = adc->buf_sz - state.residue;
807 unsigned int size;
808
809 /* Return available bytes */
810 if (i >= adc->bufi)
811 size = i - adc->bufi;
812 else
813 size = adc->buf_sz + i - adc->bufi;
814
815 return size;
816 }
817
818 return 0;
819 }
820
821 static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
822 s32 *buffer)
823 {
824 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
825 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
826 unsigned int i = adc->nconv;
827 s32 *ptr = buffer;
828
829 while (i--) {
830 /* Mask 8 LSB that contains the channel ID */
831 *ptr &= 0xFFFFFF00;
832 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
833 if (*ptr > flo->max)
834 *ptr -= 1;
835 /*
836 * Samples from filter are retrieved with 23 bits resolution
837 * or less. Shift left to align MSB on 24 bits.
838 */
839 *ptr <<= flo->lshift;
840
841 ptr++;
842 }
843 }
844
845 static void stm32_dfsdm_dma_buffer_done(void *data)
846 {
847 struct iio_dev *indio_dev = data;
848 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
849 int available = stm32_dfsdm_adc_dma_residue(adc);
850 size_t old_pos;
851
852 /*
853 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
854 * offers only an interface to push data samples per samples.
855 * For this reason IIO buffer interface is not used and interface is
856 * bypassed using a private callback registered by ASoC.
857 * This should be a temporary solution waiting a cyclic DMA engine
858 * support in IIO.
859 */
860
861 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
862 adc->bufi, available);
863 old_pos = adc->bufi;
864
865 while (available >= indio_dev->scan_bytes) {
866 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
867
868 stm32_dfsdm_process_data(adc, buffer);
869
870 available -= indio_dev->scan_bytes;
871 adc->bufi += indio_dev->scan_bytes;
872 if (adc->bufi >= adc->buf_sz) {
873 if (adc->cb)
874 adc->cb(&adc->rx_buf[old_pos],
875 adc->buf_sz - old_pos, adc->cb_priv);
876 adc->bufi = 0;
877 old_pos = 0;
878 }
879 /*
880 * In DMA mode the trigger services of IIO are not used
881 * (e.g. no call to iio_trigger_poll).
882 * Calling irq handler associated to the hardware trigger is not
883 * relevant as the conversions have already been done. Data
884 * transfers are performed directly in DMA callback instead.
885 * This implementation avoids to call trigger irq handler that
886 * may sleep, in an atomic context (DMA irq handler context).
887 */
888 if (adc->dev_data->type == DFSDM_IIO)
889 iio_push_to_buffers(indio_dev, buffer);
890 }
891 if (adc->cb)
892 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
893 adc->cb_priv);
894 }
895
896 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
897 {
898 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
899 /*
900 * The DFSDM supports half-word transfers. However, for 16 bits record,
901 * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
902 * shift is required.
903 */
904 struct dma_slave_config config = {
905 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
906 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
907 };
908 struct dma_async_tx_descriptor *desc;
909 dma_cookie_t cookie;
910 int ret;
911
912 if (!adc->dma_chan)
913 return -EINVAL;
914
915 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
916 adc->buf_sz, adc->buf_sz / 2);
917
918 if (adc->nconv == 1 && !indio_dev->trig)
919 config.src_addr += DFSDM_RDATAR(adc->fl_id);
920 else
921 config.src_addr += DFSDM_JDATAR(adc->fl_id);
922 ret = dmaengine_slave_config(adc->dma_chan, &config);
923 if (ret)
924 return ret;
925
926 /* Prepare a DMA cyclic transaction */
927 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
928 adc->dma_buf,
929 adc->buf_sz, adc->buf_sz / 2,
930 DMA_DEV_TO_MEM,
931 DMA_PREP_INTERRUPT);
932 if (!desc)
933 return -EBUSY;
934
935 desc->callback = stm32_dfsdm_dma_buffer_done;
936 desc->callback_param = indio_dev;
937
938 cookie = dmaengine_submit(desc);
939 ret = dma_submit_error(cookie);
940 if (ret)
941 goto err_stop_dma;
942
943 /* Issue pending DMA requests */
944 dma_async_issue_pending(adc->dma_chan);
945
946 if (adc->nconv == 1 && !indio_dev->trig) {
947 /* Enable regular DMA transfer*/
948 ret = regmap_update_bits(adc->dfsdm->regmap,
949 DFSDM_CR1(adc->fl_id),
950 DFSDM_CR1_RDMAEN_MASK,
951 DFSDM_CR1_RDMAEN_MASK);
952 } else {
953 /* Enable injected DMA transfer*/
954 ret = regmap_update_bits(adc->dfsdm->regmap,
955 DFSDM_CR1(adc->fl_id),
956 DFSDM_CR1_JDMAEN_MASK,
957 DFSDM_CR1_JDMAEN_MASK);
958 }
959
960 if (ret < 0)
961 goto err_stop_dma;
962
963 return 0;
964
965 err_stop_dma:
966 dmaengine_terminate_all(adc->dma_chan);
967
968 return ret;
969 }
970
971 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
972 {
973 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
974
975 if (!adc->dma_chan)
976 return;
977
978 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
979 DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
980 dmaengine_terminate_all(adc->dma_chan);
981 }
982
983 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
984 const unsigned long *scan_mask)
985 {
986 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
987
988 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
989 adc->smask = *scan_mask;
990
991 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
992
993 return 0;
994 }
995
996 static int __stm32_dfsdm_postenable(struct iio_dev *indio_dev)
997 {
998 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
999 int ret;
1000
1001 /* Reset adc buffer index */
1002 adc->bufi = 0;
1003
1004 if (adc->hwc) {
1005 ret = iio_hw_consumer_enable(adc->hwc);
1006 if (ret < 0)
1007 return ret;
1008 }
1009
1010 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1011 if (ret < 0)
1012 goto err_stop_hwc;
1013
1014 ret = stm32_dfsdm_adc_dma_start(indio_dev);
1015 if (ret) {
1016 dev_err(&indio_dev->dev, "Can't start DMA\n");
1017 goto stop_dfsdm;
1018 }
1019
1020 ret = stm32_dfsdm_start_conv(adc, indio_dev->trig);
1021 if (ret) {
1022 dev_err(&indio_dev->dev, "Can't start conversion\n");
1023 goto err_stop_dma;
1024 }
1025
1026 return 0;
1027
1028 err_stop_dma:
1029 stm32_dfsdm_adc_dma_stop(indio_dev);
1030 stop_dfsdm:
1031 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1032 err_stop_hwc:
1033 if (adc->hwc)
1034 iio_hw_consumer_disable(adc->hwc);
1035
1036 return ret;
1037 }
1038
1039 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1040 {
1041 int ret;
1042
1043 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
1044 ret = iio_triggered_buffer_postenable(indio_dev);
1045 if (ret < 0)
1046 return ret;
1047 }
1048
1049 ret = __stm32_dfsdm_postenable(indio_dev);
1050 if (ret < 0)
1051 goto err_predisable;
1052
1053 return 0;
1054
1055 err_predisable:
1056 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1057 iio_triggered_buffer_predisable(indio_dev);
1058
1059 return ret;
1060 }
1061
1062 static void __stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1063 {
1064 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1065
1066 stm32_dfsdm_stop_conv(adc);
1067
1068 stm32_dfsdm_adc_dma_stop(indio_dev);
1069
1070 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1071
1072 if (adc->hwc)
1073 iio_hw_consumer_disable(adc->hwc);
1074 }
1075
1076 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1077 {
1078 __stm32_dfsdm_predisable(indio_dev);
1079
1080 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1081 iio_triggered_buffer_predisable(indio_dev);
1082
1083 return 0;
1084 }
1085
1086 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1087 .postenable = &stm32_dfsdm_postenable,
1088 .predisable = &stm32_dfsdm_predisable,
1089 };
1090
1091 /**
1092 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1093 * DMA transfer period is achieved.
1094 *
1095 * @iio_dev: Handle to IIO device.
1096 * @cb: Pointer to callback function:
1097 * - data: pointer to data buffer
1098 * - size: size in byte of the data buffer
1099 * - private: pointer to consumer private structure.
1100 * @private: Pointer to consumer private structure.
1101 */
1102 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1103 int (*cb)(const void *data, size_t size,
1104 void *private),
1105 void *private)
1106 {
1107 struct stm32_dfsdm_adc *adc;
1108
1109 if (!iio_dev)
1110 return -EINVAL;
1111 adc = iio_priv(iio_dev);
1112
1113 adc->cb = cb;
1114 adc->cb_priv = private;
1115
1116 return 0;
1117 }
1118 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1119
1120 /**
1121 * stm32_dfsdm_release_buff_cb - unregister buffer callback
1122 *
1123 * @iio_dev: Handle to IIO device.
1124 */
1125 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1126 {
1127 struct stm32_dfsdm_adc *adc;
1128
1129 if (!iio_dev)
1130 return -EINVAL;
1131 adc = iio_priv(iio_dev);
1132
1133 adc->cb = NULL;
1134 adc->cb_priv = NULL;
1135
1136 return 0;
1137 }
1138 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1139
1140 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1141 const struct iio_chan_spec *chan, int *res)
1142 {
1143 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1144 long timeout;
1145 int ret;
1146
1147 reinit_completion(&adc->completion);
1148
1149 adc->buffer = res;
1150
1151 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1152 if (ret < 0)
1153 return ret;
1154
1155 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1156 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1157 if (ret < 0)
1158 goto stop_dfsdm;
1159
1160 adc->nconv = 1;
1161 adc->smask = BIT(chan->scan_index);
1162 ret = stm32_dfsdm_start_conv(adc, NULL);
1163 if (ret < 0) {
1164 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1165 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1166 goto stop_dfsdm;
1167 }
1168
1169 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1170 DFSDM_TIMEOUT);
1171
1172 /* Mask IRQ for regular conversion achievement*/
1173 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1174 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1175
1176 if (timeout == 0)
1177 ret = -ETIMEDOUT;
1178 else if (timeout < 0)
1179 ret = timeout;
1180 else
1181 ret = IIO_VAL_INT;
1182
1183 stm32_dfsdm_stop_conv(adc);
1184
1185 stm32_dfsdm_process_data(adc, res);
1186
1187 stop_dfsdm:
1188 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1189
1190 return ret;
1191 }
1192
1193 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1194 struct iio_chan_spec const *chan,
1195 int val, int val2, long mask)
1196 {
1197 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1198 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1199 unsigned int spi_freq;
1200 int ret = -EINVAL;
1201
1202 switch (ch->src) {
1203 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1204 spi_freq = adc->dfsdm->spi_master_freq;
1205 break;
1206 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1207 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1208 spi_freq = adc->dfsdm->spi_master_freq / 2;
1209 break;
1210 default:
1211 spi_freq = adc->spi_freq;
1212 }
1213
1214 switch (mask) {
1215 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1216 ret = iio_device_claim_direct_mode(indio_dev);
1217 if (ret)
1218 return ret;
1219
1220 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1221 if (!ret) {
1222 dev_dbg(&indio_dev->dev,
1223 "Sampling rate changed from (%u) to (%u)\n",
1224 adc->sample_freq, spi_freq / val);
1225 adc->oversamp = val;
1226 adc->sample_freq = spi_freq / val;
1227 }
1228 iio_device_release_direct_mode(indio_dev);
1229 return ret;
1230
1231 case IIO_CHAN_INFO_SAMP_FREQ:
1232 if (!val)
1233 return -EINVAL;
1234
1235 ret = iio_device_claim_direct_mode(indio_dev);
1236 if (ret)
1237 return ret;
1238
1239 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1240 iio_device_release_direct_mode(indio_dev);
1241 return ret;
1242 }
1243
1244 return -EINVAL;
1245 }
1246
1247 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1248 struct iio_chan_spec const *chan, int *val,
1249 int *val2, long mask)
1250 {
1251 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1252 int ret;
1253
1254 switch (mask) {
1255 case IIO_CHAN_INFO_RAW:
1256 ret = iio_device_claim_direct_mode(indio_dev);
1257 if (ret)
1258 return ret;
1259 ret = iio_hw_consumer_enable(adc->hwc);
1260 if (ret < 0) {
1261 dev_err(&indio_dev->dev,
1262 "%s: IIO enable failed (channel %d)\n",
1263 __func__, chan->channel);
1264 iio_device_release_direct_mode(indio_dev);
1265 return ret;
1266 }
1267 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1268 iio_hw_consumer_disable(adc->hwc);
1269 if (ret < 0) {
1270 dev_err(&indio_dev->dev,
1271 "%s: Conversion failed (channel %d)\n",
1272 __func__, chan->channel);
1273 iio_device_release_direct_mode(indio_dev);
1274 return ret;
1275 }
1276 iio_device_release_direct_mode(indio_dev);
1277 return IIO_VAL_INT;
1278
1279 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1280 *val = adc->oversamp;
1281
1282 return IIO_VAL_INT;
1283
1284 case IIO_CHAN_INFO_SAMP_FREQ:
1285 *val = adc->sample_freq;
1286
1287 return IIO_VAL_INT;
1288 }
1289
1290 return -EINVAL;
1291 }
1292
1293 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1294 struct iio_trigger *trig)
1295 {
1296 return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1297 }
1298
1299 static const struct iio_info stm32_dfsdm_info_audio = {
1300 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1301 .read_raw = stm32_dfsdm_read_raw,
1302 .write_raw = stm32_dfsdm_write_raw,
1303 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1304 };
1305
1306 static const struct iio_info stm32_dfsdm_info_adc = {
1307 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1308 .read_raw = stm32_dfsdm_read_raw,
1309 .write_raw = stm32_dfsdm_write_raw,
1310 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1311 .validate_trigger = stm32_dfsdm_validate_trigger,
1312 };
1313
1314 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1315 {
1316 struct stm32_dfsdm_adc *adc = arg;
1317 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1318 struct regmap *regmap = adc->dfsdm->regmap;
1319 unsigned int status, int_en;
1320
1321 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1322 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1323
1324 if (status & DFSDM_ISR_REOCF_MASK) {
1325 /* Read the data register clean the IRQ status */
1326 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1327 complete(&adc->completion);
1328 }
1329
1330 if (status & DFSDM_ISR_ROVRF_MASK) {
1331 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1332 dev_warn(&indio_dev->dev, "Overrun detected\n");
1333 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1334 DFSDM_ICR_CLRROVRF_MASK,
1335 DFSDM_ICR_CLRROVRF_MASK);
1336 }
1337
1338 return IRQ_HANDLED;
1339 }
1340
1341 /*
1342 * Define external info for SPI Frequency and audio sampling rate that can be
1343 * configured by ASoC driver through consumer.h API
1344 */
1345 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1346 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1347 {
1348 .name = "spi_clk_freq",
1349 .shared = IIO_SHARED_BY_TYPE,
1350 .read = dfsdm_adc_audio_get_spiclk,
1351 .write = dfsdm_adc_audio_set_spiclk,
1352 },
1353 {},
1354 };
1355
1356 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1357 {
1358 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1359
1360 if (adc->dma_chan) {
1361 dma_free_coherent(adc->dma_chan->device->dev,
1362 DFSDM_DMA_BUFFER_SIZE,
1363 adc->rx_buf, adc->dma_buf);
1364 dma_release_channel(adc->dma_chan);
1365 }
1366 }
1367
1368 static int stm32_dfsdm_dma_request(struct device *dev,
1369 struct iio_dev *indio_dev)
1370 {
1371 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1372
1373 adc->dma_chan = dma_request_chan(dev, "rx");
1374 if (IS_ERR(adc->dma_chan)) {
1375 int ret = PTR_ERR(adc->dma_chan);
1376
1377 adc->dma_chan = NULL;
1378 return ret;
1379 }
1380
1381 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1382 DFSDM_DMA_BUFFER_SIZE,
1383 &adc->dma_buf, GFP_KERNEL);
1384 if (!adc->rx_buf) {
1385 dma_release_channel(adc->dma_chan);
1386 return -ENOMEM;
1387 }
1388
1389 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1390 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1391
1392 return 0;
1393 }
1394
1395 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1396 struct iio_chan_spec *ch)
1397 {
1398 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1399 int ret;
1400
1401 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1402 if (ret < 0)
1403 return ret;
1404
1405 ch->type = IIO_VOLTAGE;
1406 ch->indexed = 1;
1407
1408 /*
1409 * IIO_CHAN_INFO_RAW: used to compute regular conversion
1410 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1411 */
1412 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1413 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1414 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1415
1416 if (adc->dev_data->type == DFSDM_AUDIO) {
1417 ch->ext_info = dfsdm_adc_audio_ext_info;
1418 } else {
1419 ch->scan_type.shift = 8;
1420 }
1421 ch->scan_type.sign = 's';
1422 ch->scan_type.realbits = 24;
1423 ch->scan_type.storagebits = 32;
1424
1425 return stm32_dfsdm_chan_configure(adc->dfsdm,
1426 &adc->dfsdm->ch_list[ch->channel]);
1427 }
1428
1429 static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
1430 {
1431 struct iio_chan_spec *ch;
1432 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1433 struct stm32_dfsdm_channel *d_ch;
1434 int ret;
1435
1436 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1437 if (!ch)
1438 return -ENOMEM;
1439
1440 ch->scan_index = 0;
1441
1442 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1443 if (ret < 0) {
1444 dev_err(&indio_dev->dev, "Channels init failed\n");
1445 return ret;
1446 }
1447 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1448
1449 d_ch = &adc->dfsdm->ch_list[ch->channel];
1450 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1451 adc->spi_freq = adc->dfsdm->spi_master_freq;
1452
1453 indio_dev->num_channels = 1;
1454 indio_dev->channels = ch;
1455
1456 return stm32_dfsdm_dma_request(dev, indio_dev);
1457 }
1458
1459 static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
1460 {
1461 struct iio_chan_spec *ch;
1462 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1463 int num_ch;
1464 int ret, chan_idx;
1465
1466 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1467 ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1468 if (ret < 0)
1469 return ret;
1470
1471 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1472 "st,adc-channels");
1473 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1474 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1475 return num_ch < 0 ? num_ch : -EINVAL;
1476 }
1477
1478 /* Bind to SD modulator IIO device */
1479 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1480 if (IS_ERR(adc->hwc))
1481 return -EPROBE_DEFER;
1482
1483 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1484 GFP_KERNEL);
1485 if (!ch)
1486 return -ENOMEM;
1487
1488 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1489 ch[chan_idx].scan_index = chan_idx;
1490 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1491 if (ret < 0) {
1492 dev_err(&indio_dev->dev, "Channels init failed\n");
1493 return ret;
1494 }
1495 }
1496
1497 indio_dev->num_channels = num_ch;
1498 indio_dev->channels = ch;
1499
1500 init_completion(&adc->completion);
1501
1502 /* Optionally request DMA */
1503 ret = stm32_dfsdm_dma_request(dev, indio_dev);
1504 if (ret) {
1505 if (ret != -ENODEV) {
1506 if (ret != -EPROBE_DEFER)
1507 dev_err(dev,
1508 "DMA channel request failed with %d\n",
1509 ret);
1510 return ret;
1511 }
1512
1513 dev_dbg(dev, "No DMA support\n");
1514 return 0;
1515 }
1516
1517 ret = iio_triggered_buffer_setup(indio_dev,
1518 &iio_pollfunc_store_time, NULL,
1519 &stm32_dfsdm_buffer_setup_ops);
1520 if (ret) {
1521 stm32_dfsdm_dma_release(indio_dev);
1522 dev_err(&indio_dev->dev, "buffer setup failed\n");
1523 return ret;
1524 }
1525
1526 /* lptimer/timer hardware triggers */
1527 indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1528
1529 return 0;
1530 }
1531
1532 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1533 .type = DFSDM_IIO,
1534 .init = stm32_dfsdm_adc_init,
1535 };
1536
1537 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1538 .type = DFSDM_AUDIO,
1539 .init = stm32_dfsdm_audio_init,
1540 };
1541
1542 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1543 {
1544 .compatible = "st,stm32-dfsdm-adc",
1545 .data = &stm32h7_dfsdm_adc_data,
1546 },
1547 {
1548 .compatible = "st,stm32-dfsdm-dmic",
1549 .data = &stm32h7_dfsdm_audio_data,
1550 },
1551 {}
1552 };
1553
1554 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1555 {
1556 struct device *dev = &pdev->dev;
1557 struct stm32_dfsdm_adc *adc;
1558 struct device_node *np = dev->of_node;
1559 const struct stm32_dfsdm_dev_data *dev_data;
1560 struct iio_dev *iio;
1561 char *name;
1562 int ret, irq, val;
1563
1564 dev_data = of_device_get_match_data(dev);
1565 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1566 if (!iio) {
1567 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1568 return -ENOMEM;
1569 }
1570
1571 adc = iio_priv(iio);
1572 adc->dfsdm = dev_get_drvdata(dev->parent);
1573
1574 iio->dev.parent = dev;
1575 iio->dev.of_node = np;
1576 iio->modes = INDIO_DIRECT_MODE;
1577
1578 platform_set_drvdata(pdev, adc);
1579
1580 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1581 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1582 dev_err(dev, "Missing or bad reg property\n");
1583 return -EINVAL;
1584 }
1585
1586 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1587 if (!name)
1588 return -ENOMEM;
1589 if (dev_data->type == DFSDM_AUDIO) {
1590 iio->info = &stm32_dfsdm_info_audio;
1591 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1592 } else {
1593 iio->info = &stm32_dfsdm_info_adc;
1594 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1595 }
1596 iio->name = name;
1597
1598 /*
1599 * In a first step IRQs generated for channels are not treated.
1600 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1601 */
1602 irq = platform_get_irq(pdev, 0);
1603 if (irq < 0)
1604 return irq;
1605
1606 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1607 0, pdev->name, adc);
1608 if (ret < 0) {
1609 dev_err(dev, "Failed to request IRQ\n");
1610 return ret;
1611 }
1612
1613 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1614 if (ret < 0) {
1615 dev_err(dev, "Failed to set filter order\n");
1616 return ret;
1617 }
1618
1619 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1620
1621 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1622 if (!ret)
1623 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1624
1625 adc->dev_data = dev_data;
1626 ret = dev_data->init(dev, iio);
1627 if (ret < 0)
1628 return ret;
1629
1630 ret = iio_device_register(iio);
1631 if (ret < 0)
1632 goto err_cleanup;
1633
1634 if (dev_data->type == DFSDM_AUDIO) {
1635 ret = of_platform_populate(np, NULL, NULL, dev);
1636 if (ret < 0) {
1637 dev_err(dev, "Failed to find an audio DAI\n");
1638 goto err_unregister;
1639 }
1640 }
1641
1642 return 0;
1643
1644 err_unregister:
1645 iio_device_unregister(iio);
1646 err_cleanup:
1647 stm32_dfsdm_dma_release(iio);
1648
1649 return ret;
1650 }
1651
1652 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1653 {
1654 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1655 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1656
1657 if (adc->dev_data->type == DFSDM_AUDIO)
1658 of_platform_depopulate(&pdev->dev);
1659 iio_device_unregister(indio_dev);
1660 stm32_dfsdm_dma_release(indio_dev);
1661
1662 return 0;
1663 }
1664
1665 static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
1666 {
1667 struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1668 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1669
1670 if (iio_buffer_enabled(indio_dev))
1671 __stm32_dfsdm_predisable(indio_dev);
1672
1673 return 0;
1674 }
1675
1676 static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
1677 {
1678 struct stm32_dfsdm_adc *adc = dev_get_drvdata(dev);
1679 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1680 const struct iio_chan_spec *chan;
1681 struct stm32_dfsdm_channel *ch;
1682 int i, ret;
1683
1684 /* restore channels configuration */
1685 for (i = 0; i < indio_dev->num_channels; i++) {
1686 chan = indio_dev->channels + i;
1687 ch = &adc->dfsdm->ch_list[chan->channel];
1688 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1689 if (ret)
1690 return ret;
1691 }
1692
1693 if (iio_buffer_enabled(indio_dev))
1694 __stm32_dfsdm_postenable(indio_dev);
1695
1696 return 0;
1697 }
1698
1699 static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1700 stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
1701
1702 static struct platform_driver stm32_dfsdm_adc_driver = {
1703 .driver = {
1704 .name = "stm32-dfsdm-adc",
1705 .of_match_table = stm32_dfsdm_adc_match,
1706 .pm = &stm32_dfsdm_adc_pm_ops,
1707 },
1708 .probe = stm32_dfsdm_adc_probe,
1709 .remove = stm32_dfsdm_adc_remove,
1710 };
1711 module_platform_driver(stm32_dfsdm_adc_driver);
1712
1713 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1714 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1715 MODULE_LICENSE("GPL v2");
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