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Files include/linux/byteorder/{big,little}_endian.h define
[people/ms/u-boot.git] / drivers / inca-ip_sw.c
1 /*
2 * INCA-IP internal switch ethernet driver.
3 *
4 * (C) Copyright 2003-2004
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26
27 #include <common.h>
28
29 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
30 && defined(CONFIG_INCA_IP_SWITCH)
31
32 #include <malloc.h>
33 #include <net.h>
34 #include <asm/inca-ip.h>
35 #include <asm/addrspace.h>
36
37
38 #define NUM_RX_DESC PKTBUFSRX
39 #define NUM_TX_DESC 3
40 #define TOUT_LOOP 1000000
41
42
43 #define DELAY udelay(10000)
44 /* Sometimes the store word instruction hangs while writing to one
45 * of the Switch registers. Moving the instruction into a separate
46 * function somehow makes the problem go away.
47 */
48 static void SWORD(volatile u32 * reg, u32 value)
49 {
50 *reg = value;
51 }
52
53 #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value;
54 #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg)
55 #define SW_WRITE_REG(reg, value) \
56 SWORD(reg, value);\
57 DELAY;\
58 SWORD(reg, value);
59
60 #define SW_READ_REG(reg, value) \
61 value = (u32)*((volatile u32*)reg);\
62 DELAY;\
63 value = (u32)*((volatile u32*)reg);
64
65 #define INCA_DMA_TX_POLLING_TIME 0x07
66 #define INCA_DMA_RX_POLLING_TIME 0x07
67
68 #define INCA_DMA_TX_HOLD 0x80000000
69 #define INCA_DMA_TX_EOP 0x40000000
70 #define INCA_DMA_TX_SOP 0x20000000
71 #define INCA_DMA_TX_ICPT 0x10000000
72 #define INCA_DMA_TX_IEOP 0x08000000
73
74 #define INCA_DMA_RX_C 0x80000000
75 #define INCA_DMA_RX_SOP 0x40000000
76 #define INCA_DMA_RX_EOP 0x20000000
77
78 #define INCA_SWITCH_PHY_SPEED_10H 0x1
79 #define INCA_SWITCH_PHY_SPEED_10F 0x5
80 #define INCA_SWITCH_PHY_SPEED_100H 0x2
81 #define INCA_SWITCH_PHY_SPEED_100F 0x6
82
83 /************************ Auto MDIX settings ************************/
84 #define INCA_IP_AUTO_MDIX_LAN_PORTS_DIR INCA_IP_Ports_P1_DIR
85 #define INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL INCA_IP_Ports_P1_ALTSEL
86 #define INCA_IP_AUTO_MDIX_LAN_PORTS_OUT INCA_IP_Ports_P1_OUT
87 #define INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX 16
88
89 #define WAIT_SIGNAL_RETRIES 100
90 #define WAIT_LINK_RETRIES 100
91 #define LINK_RETRY_DELAY 2000 /* ms */
92 /********************************************************************/
93
94 typedef struct
95 {
96 union {
97 struct {
98 volatile u32 HOLD :1;
99 volatile u32 ICpt :1;
100 volatile u32 IEop :1;
101 volatile u32 offset :3;
102 volatile u32 reserved0 :4;
103 volatile u32 NFB :22;
104 }field;
105
106 volatile u32 word;
107 }params;
108
109 volatile u32 nextRxDescPtr;
110
111 volatile u32 RxDataPtr;
112
113 union {
114 struct {
115 volatile u32 C :1;
116 volatile u32 Sop :1;
117 volatile u32 Eop :1;
118 volatile u32 reserved3 :12;
119 volatile u32 NBT :17;
120 }field;
121
122 volatile u32 word;
123 }status;
124
125 } inca_rx_descriptor_t;
126
127
128 typedef struct
129 {
130 union {
131 struct {
132 volatile u32 HOLD :1;
133 volatile u32 Eop :1;
134 volatile u32 Sop :1;
135 volatile u32 ICpt :1;
136 volatile u32 IEop :1;
137 volatile u32 reserved0 :5;
138 volatile u32 NBA :22;
139 }field;
140
141 volatile u32 word;
142 }params;
143
144 volatile u32 nextTxDescPtr;
145
146 volatile u32 TxDataPtr;
147
148 volatile u32 C :1;
149 volatile u32 reserved3 :31;
150
151 } inca_tx_descriptor_t;
152
153
154 static inca_rx_descriptor_t rx_ring[NUM_RX_DESC] __attribute__ ((aligned(16)));
155 static inca_tx_descriptor_t tx_ring[NUM_TX_DESC] __attribute__ ((aligned(16)));
156
157 static int tx_new, rx_new, tx_hold, rx_hold;
158 static int tx_old_hold = -1;
159 static int initialized = 0;
160
161
162 static int inca_switch_init(struct eth_device *dev, bd_t * bis);
163 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length);
164 static int inca_switch_recv(struct eth_device *dev);
165 static void inca_switch_halt(struct eth_device *dev);
166 static void inca_init_switch_chip(void);
167 static void inca_dma_init(void);
168 static int inca_amdix(void);
169
170
171 int inca_switch_initialize(bd_t * bis)
172 {
173 struct eth_device *dev;
174
175 #if 0
176 printf("Entered inca_switch_initialize()\n");
177 #endif
178
179 if (!(dev = (struct eth_device *) malloc (sizeof *dev))) {
180 printf("Failed to allocate memory\n");
181 return 0;
182 }
183 memset(dev, 0, sizeof(*dev));
184
185 inca_dma_init();
186
187 inca_init_switch_chip();
188
189 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
190 inca_amdix();
191 #endif
192
193 sprintf(dev->name, "INCA-IP Switch");
194 dev->init = inca_switch_init;
195 dev->halt = inca_switch_halt;
196 dev->send = inca_switch_send;
197 dev->recv = inca_switch_recv;
198
199 eth_register(dev);
200
201 #if 0
202 printf("Leaving inca_switch_initialize()\n");
203 #endif
204
205 return 1;
206 }
207
208
209 static int inca_switch_init(struct eth_device *dev, bd_t * bis)
210 {
211 int i;
212 u32 v, regValue;
213 u16 wTmp;
214
215 #if 0
216 printf("Entering inca_switch_init()\n");
217 #endif
218
219 /* Set MAC address.
220 */
221 wTmp = (u16)dev->enetaddr[0];
222 regValue = (wTmp << 8) | dev->enetaddr[1];
223
224 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA1, regValue);
225
226 wTmp = (u16)dev->enetaddr[2];
227 regValue = (wTmp << 8) | dev->enetaddr[3];
228 regValue = regValue << 16;
229 wTmp = (u16)dev->enetaddr[4];
230 regValue |= (wTmp<<8) | dev->enetaddr[5];
231
232 SW_WRITE_REG(INCA_IP_Switch_PMAC_SA2, regValue);
233
234 /* Initialize the descriptor rings.
235 */
236 for (i = 0; i < NUM_RX_DESC; i++) {
237 inca_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_ring[i]);
238 memset(rx_desc, 0, sizeof(rx_ring[i]));
239
240 /* Set maximum size of receive buffer.
241 */
242 rx_desc->params.field.NFB = PKTSIZE_ALIGN;
243
244 /* Set the offset of the receive buffer. Zero means
245 * that the offset mechanism is not used.
246 */
247 rx_desc->params.field.offset = 0;
248
249 /* Check if it is the last descriptor.
250 */
251 if (i == (NUM_RX_DESC - 1)) {
252 /* Let the last descriptor point to the first
253 * one.
254 */
255 rx_desc->nextRxDescPtr = KSEG1ADDR((u32)rx_ring);
256 } else {
257 /* Set the address of the next descriptor.
258 */
259 rx_desc->nextRxDescPtr = (u32)KSEG1ADDR(&rx_ring[i+1]);
260 }
261
262 rx_desc->RxDataPtr = (u32)KSEG1ADDR(NetRxPackets[i]);
263 }
264
265 #if 0
266 printf("rx_ring = 0x%08X 0x%08X\n", (u32)rx_ring, (u32)&rx_ring[0]);
267 printf("tx_ring = 0x%08X 0x%08X\n", (u32)tx_ring, (u32)&tx_ring[0]);
268 #endif
269
270 for (i = 0; i < NUM_TX_DESC; i++) {
271 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[i]);
272
273 memset(tx_desc, 0, sizeof(tx_ring[i]));
274
275 tx_desc->params.word = 0;
276 tx_desc->params.field.HOLD = 1;
277 tx_desc->C = 1;
278
279 /* Check if it is the last descriptor.
280 */
281 if (i == (NUM_TX_DESC - 1)) {
282 /* Let the last descriptor point to the
283 * first one.
284 */
285 tx_desc->nextTxDescPtr = KSEG1ADDR((u32)tx_ring);
286 } else {
287 /* Set the address of the next descriptor.
288 */
289 tx_desc->nextTxDescPtr = (u32)KSEG1ADDR(&tx_ring[i+1]);
290 }
291 }
292
293 /* Initialize RxDMA.
294 */
295 DMA_READ_REG(INCA_IP_DMA_DMA_RXISR, v);
296 #if 0
297 printf("RX status = 0x%08X\n", v);
298 #endif
299
300 /* Writing to the FRDA of CHANNEL.
301 */
302 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXFRDA0, (u32)rx_ring);
303
304 /* Writing to the COMMAND REG.
305 */
306 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_INIT);
307
308 /* Initialize TxDMA.
309 */
310 DMA_READ_REG(INCA_IP_DMA_DMA_TXISR, v);
311 #if 0
312 printf("TX status = 0x%08X\n", v);
313 #endif
314
315 /* Writing to the FRDA of CHANNEL.
316 */
317 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXFRDA0, (u32)tx_ring);
318
319 tx_new = rx_new = 0;
320
321 tx_hold = NUM_TX_DESC - 1;
322 rx_hold = NUM_RX_DESC - 1;
323
324 #if 0
325 rx_ring[rx_hold].params.field.HOLD = 1;
326 #endif
327 /* enable spanning tree forwarding, enable the CPU port */
328 /* ST_PT:
329 * CPS (CPU port status) 0x3 (forwarding)
330 * LPS (LAN port status) 0x3 (forwarding)
331 * PPS (PC port status) 0x3 (forwarding)
332 */
333 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f);
334
335 #if 0
336 printf("Leaving inca_switch_init()\n");
337 #endif
338
339 return 0;
340 }
341
342
343 static int inca_switch_send(struct eth_device *dev, volatile void *packet, int length)
344 {
345 int i;
346 int res = -1;
347 u32 command;
348 u32 regValue;
349 inca_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_ring[tx_new]);
350
351 #if 0
352 printf("Entered inca_switch_send()\n");
353 #endif
354
355 if (length <= 0) {
356 printf ("%s: bad packet size: %d\n", dev->name, length);
357 goto Done;
358 }
359
360 for(i = 0; tx_desc->C == 0; i++) {
361 if (i >= TOUT_LOOP) {
362 printf("%s: tx error buffer not ready\n", dev->name);
363 goto Done;
364 }
365 }
366
367 if (tx_old_hold >= 0) {
368 KSEG1ADDR(&tx_ring[tx_old_hold])->params.field.HOLD = 1;
369 }
370 tx_old_hold = tx_hold;
371
372 tx_desc->params.word =
373 (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD);
374
375 tx_desc->C = 0;
376 tx_desc->TxDataPtr = (u32)packet;
377 tx_desc->params.field.NBA = length;
378
379 KSEG1ADDR(&tx_ring[tx_hold])->params.field.HOLD = 0;
380
381 tx_hold = tx_new;
382 tx_new = (tx_new + 1) % NUM_TX_DESC;
383
384
385 if (! initialized) {
386 command = INCA_IP_DMA_DMA_TXCCR0_INIT;
387 initialized = 1;
388 } else {
389 command = INCA_IP_DMA_DMA_TXCCR0_HR;
390 }
391
392 DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
393 regValue |= command;
394 #if 0
395 printf("regValue = 0x%x\n", regValue);
396 #endif
397 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, regValue);
398
399 #if 1
400 for(i = 0; KSEG1ADDR(&tx_ring[tx_hold])->C == 0; i++) {
401 if (i >= TOUT_LOOP) {
402 printf("%s: tx buffer not ready\n", dev->name);
403 goto Done;
404 }
405 }
406 #endif
407 res = length;
408 Done:
409 #if 0
410 printf("Leaving inca_switch_send()\n");
411 #endif
412 return res;
413 }
414
415
416 static int inca_switch_recv(struct eth_device *dev)
417 {
418 int length = 0;
419 inca_rx_descriptor_t * rx_desc;
420
421 #if 0
422 printf("Entered inca_switch_recv()\n");
423 #endif
424
425 for (;;) {
426 rx_desc = KSEG1ADDR(&rx_ring[rx_new]);
427
428 if (rx_desc->status.field.C == 0) {
429 break;
430 }
431
432 #if 0
433 rx_ring[rx_new].params.field.HOLD = 1;
434 #endif
435
436 if (! rx_desc->status.field.Eop) {
437 printf("Partly received packet!!!\n");
438 break;
439 }
440
441 length = rx_desc->status.field.NBT;
442 rx_desc->status.word &=
443 ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C);
444 #if 0
445 {
446 int i;
447 for (i=0;i<length - 4;i++) {
448 if (i % 16 == 0) printf("\n%04x: ", i);
449 printf("%02X ", NetRxPackets[rx_new][i]);
450 }
451 printf("\n");
452 }
453 #endif
454
455 if (length) {
456 #if 0
457 printf("Received %d bytes\n", length);
458 #endif
459 NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), length - 4);
460 } else {
461 #if 1
462 printf("Zero length!!!\n");
463 #endif
464 }
465
466
467 KSEG1ADDR(&rx_ring[rx_hold])->params.field.HOLD = 0;
468
469 rx_hold = rx_new;
470
471 rx_new = (rx_new + 1) % NUM_RX_DESC;
472 }
473
474 #if 0
475 printf("Leaving inca_switch_recv()\n");
476 #endif
477
478 return length;
479 }
480
481
482 static void inca_switch_halt(struct eth_device *dev)
483 {
484 #if 0
485 printf("Entered inca_switch_halt()\n");
486 #endif
487
488 #if 1
489 initialized = 0;
490 #endif
491 #if 1
492 /* Disable forwarding to the CPU port.
493 */
494 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
495
496 /* Close RxDMA channel.
497 */
498 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
499
500 /* Close TxDMA channel.
501 */
502 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_TXCCR0_OFF);
503
504
505 #endif
506 #if 0
507 printf("Leaving inca_switch_halt()\n");
508 #endif
509 }
510
511
512 static void inca_init_switch_chip(void)
513 {
514 u32 regValue;
515
516 /* To workaround a problem with collision counter
517 * (see Errata sheet).
518 */
519 SW_WRITE_REG(INCA_IP_Switch_PC_TX_CTL, 0x00000001);
520 SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001);
521
522 #if 1
523 /* init MDIO configuration:
524 * MDS (Poll speed): 0x01 (4ms)
525 * PHY_LAN_ADDR: 0x06
526 * PHY_PC_ADDR: 0x05
527 * UEP (Use External PHY): 0x00 (Internal PHY is used)
528 * PS (Port Select): 0x00 (PT/UMM for LAN)
529 * PT (PHY Test): 0x00 (no test mode)
530 * UMM (Use MDIO Mode): 0x00 (state machine is disabled)
531 */
532 SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50);
533
534 /* init PHY:
535 * SL (Auto Neg. Speed for LAN)
536 * SP (Auto Neg. Speed for PC)
537 * LL (Link Status for LAN)
538 * LP (Link Status for PC)
539 * DL (Duplex Status for LAN)
540 * DP (Duplex Status for PC)
541 * PL (Auto Neg. Pause Status for LAN)
542 * PP (Auto Neg. Pause Status for PC)
543 */
544 SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff);
545
546 /* MDIO_ACC:
547 * RA (Request/Ack) 0x01 (Request)
548 * RW (Read/Write) 0x01 (Write)
549 * PHY_ADDR 0x05 (PC)
550 * REG_ADDR 0x00 (PHY_BCR: basic control register)
551 * PHY_DATA 0x8000
552 * Reset - software reset
553 * LB (loop back) - normal
554 * SS (speed select) - 10 Mbit/s
555 * ANE (auto neg. enable) - enable
556 * PD (power down) - normal
557 * ISO (isolate) - normal
558 * RAN (restart auto neg.) - normal
559 * DM (duplex mode) - half duplex
560 * CT (collision test) - enable
561 */
562 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a09000);
563
564 /* MDIO_ACC:
565 * RA (Request/Ack) 0x01 (Request)
566 * RW (Read/Write) 0x01 (Write)
567 * PHY_ADDR 0x06 (LAN)
568 * REG_ADDR 0x00 (PHY_BCR: basic control register)
569 * PHY_DATA 0x8000
570 * Reset - software reset
571 * LB (loop back) - normal
572 * SS (speed select) - 10 Mbit/s
573 * ANE (auto neg. enable) - enable
574 * PD (power down) - normal
575 * ISO (isolate) - normal
576 * RAN (restart auto neg.) - normal
577 * DM (duplex mode) - half duplex
578 * CT (collision test) - enable
579 */
580 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c09000);
581
582 #endif
583
584 /* Make sure the CPU port is disabled for now. We
585 * don't want packets to get stacked for us until
586 * we enable DMA and are prepared to receive them.
587 */
588 SW_WRITE_REG(INCA_IP_Switch_ST_PT,0xf);
589
590 SW_READ_REG(INCA_IP_Switch_ARL_CTL, regValue);
591
592 /* CRC GEN is enabled.
593 */
594 regValue |= 0x00000200;
595 SW_WRITE_REG(INCA_IP_Switch_ARL_CTL, regValue);
596
597 /* ADD TAG is disabled.
598 */
599 SW_READ_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
600 regValue &= ~0x00000002;
601 SW_WRITE_REG(INCA_IP_Switch_PMAC_HD_CTL, regValue);
602 }
603
604
605 static void inca_dma_init(void)
606 {
607 /* Switch off all DMA channels.
608 */
609 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
610 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR1, INCA_IP_DMA_DMA_RXCCR1_OFF);
611
612 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR0, INCA_IP_DMA_DMA_RXCCR0_OFF);
613 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR1, INCA_IP_DMA_DMA_TXCCR1_OFF);
614 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXCCR2, INCA_IP_DMA_DMA_TXCCR2_OFF);
615
616 /* Setup TX channel polling time.
617 */
618 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXPOLL, INCA_DMA_TX_POLLING_TIME);
619
620 /* Setup RX channel polling time.
621 */
622 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXPOLL, INCA_DMA_RX_POLLING_TIME);
623
624 /* ERRATA: write reset value into the DMA RX IMR register.
625 */
626 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXIMR, 0xFFFFFFFF);
627
628 /* Just in case: disable all transmit interrupts also.
629 */
630 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXIMR, 0xFFFFFFFF);
631
632 DMA_WRITE_REG(INCA_IP_DMA_DMA_TXISR, 0xFFFFFFFF);
633 DMA_WRITE_REG(INCA_IP_DMA_DMA_RXISR, 0xFFFFFFFF);
634 }
635
636 #if defined(CONFIG_INCA_IP_SWITCH_AMDIX)
637 static int inca_amdix(void)
638 {
639 u32 phyReg1 = 0;
640 u32 phyReg4 = 0;
641 u32 phyReg5 = 0;
642 u32 phyReg6 = 0;
643 u32 phyReg31 = 0;
644 u32 regEphy = 0;
645 int mdi_flag;
646 int retries;
647
648 /* Setup GPIO pins.
649 */
650 *INCA_IP_AUTO_MDIX_LAN_PORTS_DIR |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
651 *INCA_IP_AUTO_MDIX_LAN_PORTS_ALTSEL |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
652
653 #if 0
654 /* Wait for signal.
655 */
656 retries = WAIT_SIGNAL_RETRIES;
657 while (--retries) {
658 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
659 (0x1 << 31) | /* RA */
660 (0x0 << 30) | /* Read */
661 (0x6 << 21) | /* LAN */
662 (17 << 16)); /* PHY_MCSR */
663 do {
664 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
665 } while (phyReg1 & (1 << 31));
666
667 if (phyReg1 & (1 << 1)) {
668 /* Signal detected */
669 break;
670 }
671 }
672
673 if (!retries)
674 goto Fail;
675 #endif
676
677 /* Set MDI mode.
678 */
679 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
680 mdi_flag = 1;
681
682 /* Wait for link.
683 */
684 retries = WAIT_LINK_RETRIES;
685 while (--retries) {
686 udelay(LINK_RETRY_DELAY * 1000);
687 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
688 (0x1 << 31) | /* RA */
689 (0x0 << 30) | /* Read */
690 (0x6 << 21) | /* LAN */
691 (1 << 16)); /* PHY_BSR */
692 do {
693 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
694 } while (phyReg1 & (1 << 31));
695
696 if (phyReg1 & (1 << 2)) {
697 /* Link is up */
698 break;
699 } else if (mdi_flag) {
700 /* Set MDIX mode */
701 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT |= (1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
702 mdi_flag = 0;
703 } else {
704 /* Set MDI mode */
705 *INCA_IP_AUTO_MDIX_LAN_PORTS_OUT &= ~(1 << INCA_IP_AUTO_MDIX_LAN_GPIO_PIN_RXTX);
706 mdi_flag = 1;
707 }
708 }
709
710 if (!retries) {
711 goto Fail;
712 } else {
713 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
714 (0x1 << 31) | /* RA */
715 (0x0 << 30) | /* Read */
716 (0x6 << 21) | /* LAN */
717 (1 << 16)); /* PHY_BSR */
718 do {
719 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg1);
720 } while (phyReg1 & (1 << 31));
721
722 /* Auto-negotiation / Parallel detection complete
723 */
724 if (phyReg1 & (1 << 5)) {
725 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
726 (0x1 << 31) | /* RA */
727 (0x0 << 30) | /* Read */
728 (0x6 << 21) | /* LAN */
729 (31 << 16)); /* PHY_SCSR */
730 do {
731 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg31);
732 } while (phyReg31 & (1 << 31));
733
734 switch ((phyReg31 >> 2) & 0x7) {
735 case INCA_SWITCH_PHY_SPEED_10H:
736 /* 10Base-T Half-duplex */
737 regEphy = 0;
738 break;
739 case INCA_SWITCH_PHY_SPEED_10F:
740 /* 10Base-T Full-duplex */
741 regEphy = INCA_IP_Switch_EPHY_DL;
742 break;
743 case INCA_SWITCH_PHY_SPEED_100H:
744 /* 100Base-TX Half-duplex */
745 regEphy = INCA_IP_Switch_EPHY_SL;
746 break;
747 case INCA_SWITCH_PHY_SPEED_100F:
748 /* 100Base-TX Full-duplex */
749 regEphy = INCA_IP_Switch_EPHY_SL | INCA_IP_Switch_EPHY_DL;
750 break;
751 }
752
753 /* In case of Auto-negotiation,
754 * update the negotiated PAUSE support status
755 */
756 if (phyReg1 & (1 << 3)) {
757 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
758 (0x1 << 31) | /* RA */
759 (0x0 << 30) | /* Read */
760 (0x6 << 21) | /* LAN */
761 (6 << 16)); /* PHY_ANER */
762 do {
763 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg6);
764 } while (phyReg6 & (1 << 31));
765
766 /* We are Autoneg-able.
767 * Is Link partner also able to autoneg?
768 */
769 if (phyReg6 & (1 << 0)) {
770 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
771 (0x1 << 31) | /* RA */
772 (0x0 << 30) | /* Read */
773 (0x6 << 21) | /* LAN */
774 (4 << 16)); /* PHY_ANAR */
775 do {
776 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg4);
777 } while (phyReg4 & (1 << 31));
778
779 /* We advertise PAUSE capab.
780 * Does link partner also advertise it?
781 */
782 if (phyReg4 & (1 << 10)) {
783 SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC,
784 (0x1 << 31) | /* RA */
785 (0x0 << 30) | /* Read */
786 (0x6 << 21) | /* LAN */
787 (5 << 16)); /* PHY_ANLPAR */
788 do {
789 SW_READ_REG(INCA_IP_Switch_MDIO_ACC, phyReg5);
790 } while (phyReg5 & (1 << 31));
791
792 /* Link partner is PAUSE capab.
793 */
794 if (phyReg5 & (1 << 10)) {
795 regEphy |= INCA_IP_Switch_EPHY_PL;
796 }
797 }
798 }
799
800 }
801
802 /* Link is up */
803 regEphy |= INCA_IP_Switch_EPHY_LL;
804
805 SW_WRITE_REG(INCA_IP_Switch_EPHY, regEphy);
806 }
807 }
808
809 return 0;
810
811 Fail:
812 printf("No Link on LAN port\n");
813 return -1;
814 }
815 #endif /* CONFIG_INCA_IP_SWITCH_AMDIX */
816
817 #endif
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