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Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit...
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / cxgb3 / cxio_hal.c
1 /*
2 * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #include <asm/delay.h>
33
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/sched.h>
37 #include <linux/spinlock.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <net/net_namespace.h>
42
43 #include "cxio_resource.h"
44 #include "cxio_hal.h"
45 #include "cxgb3_offload.h"
46 #include "sge_defs.h"
47
48 static LIST_HEAD(rdev_list);
49 static cxio_hal_ev_callback_func_t cxio_ev_cb = NULL;
50
51 static struct cxio_rdev *cxio_hal_find_rdev_by_name(char *dev_name)
52 {
53 struct cxio_rdev *rdev;
54
55 list_for_each_entry(rdev, &rdev_list, entry)
56 if (!strcmp(rdev->dev_name, dev_name))
57 return rdev;
58 return NULL;
59 }
60
61 static struct cxio_rdev *cxio_hal_find_rdev_by_t3cdev(struct t3cdev *tdev)
62 {
63 struct cxio_rdev *rdev;
64
65 list_for_each_entry(rdev, &rdev_list, entry)
66 if (rdev->t3cdev_p == tdev)
67 return rdev;
68 return NULL;
69 }
70
71 int cxio_hal_cq_op(struct cxio_rdev *rdev_p, struct t3_cq *cq,
72 enum t3_cq_opcode op, u32 credit)
73 {
74 int ret;
75 struct t3_cqe *cqe;
76 u32 rptr;
77
78 struct rdma_cq_op setup;
79 setup.id = cq->cqid;
80 setup.credits = (op == CQ_CREDIT_UPDATE) ? credit : 0;
81 setup.op = op;
82 ret = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_OP, &setup);
83
84 if ((ret < 0) || (op == CQ_CREDIT_UPDATE))
85 return ret;
86
87 /*
88 * If the rearm returned an index other than our current index,
89 * then there might be CQE's in flight (being DMA'd). We must wait
90 * here for them to complete or the consumer can miss a notification.
91 */
92 if (Q_PTR2IDX((cq->rptr), cq->size_log2) != ret) {
93 int i=0;
94
95 rptr = cq->rptr;
96
97 /*
98 * Keep the generation correct by bumping rptr until it
99 * matches the index returned by the rearm - 1.
100 */
101 while (Q_PTR2IDX((rptr+1), cq->size_log2) != ret)
102 rptr++;
103
104 /*
105 * Now rptr is the index for the (last) cqe that was
106 * in-flight at the time the HW rearmed the CQ. We
107 * spin until that CQE is valid.
108 */
109 cqe = cq->queue + Q_PTR2IDX(rptr, cq->size_log2);
110 while (!CQ_VLD_ENTRY(rptr, cq->size_log2, cqe)) {
111 udelay(1);
112 if (i++ > 1000000) {
113 pr_err("%s: stalled rnic\n", rdev_p->dev_name);
114 return -EIO;
115 }
116 }
117
118 return 1;
119 }
120
121 return 0;
122 }
123
124 static int cxio_hal_clear_cq_ctx(struct cxio_rdev *rdev_p, u32 cqid)
125 {
126 struct rdma_cq_setup setup;
127 setup.id = cqid;
128 setup.base_addr = 0; /* NULL address */
129 setup.size = 0; /* disaable the CQ */
130 setup.credits = 0;
131 setup.credit_thres = 0;
132 setup.ovfl_mode = 0;
133 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
134 }
135
136 static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid)
137 {
138 u64 sge_cmd;
139 struct t3_modify_qp_wr *wqe;
140 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
141 if (!skb) {
142 pr_debug("%s alloc_skb failed\n", __func__);
143 return -ENOMEM;
144 }
145 wqe = skb_put_zero(skb, sizeof(*wqe));
146 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD,
147 T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7,
148 T3_SOPEOP);
149 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
150 sge_cmd = qpid << 8 | 3;
151 wqe->sge_cmd = cpu_to_be64(sge_cmd);
152 skb->priority = CPL_PRIORITY_CONTROL;
153 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
154 }
155
156 int cxio_create_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq, int kernel)
157 {
158 struct rdma_cq_setup setup;
159 int size = (1UL << (cq->size_log2)) * sizeof(struct t3_cqe);
160
161 size += 1; /* one extra page for storing cq-in-err state */
162 cq->cqid = cxio_hal_get_cqid(rdev_p->rscp);
163 if (!cq->cqid)
164 return -ENOMEM;
165 if (kernel) {
166 cq->sw_queue = kzalloc(size, GFP_KERNEL);
167 if (!cq->sw_queue)
168 return -ENOMEM;
169 }
170 cq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev), size,
171 &(cq->dma_addr), GFP_KERNEL);
172 if (!cq->queue) {
173 kfree(cq->sw_queue);
174 return -ENOMEM;
175 }
176 dma_unmap_addr_set(cq, mapping, cq->dma_addr);
177 memset(cq->queue, 0, size);
178 setup.id = cq->cqid;
179 setup.base_addr = (u64) (cq->dma_addr);
180 setup.size = 1UL << cq->size_log2;
181 setup.credits = 65535;
182 setup.credit_thres = 1;
183 if (rdev_p->t3cdev_p->type != T3A)
184 setup.ovfl_mode = 0;
185 else
186 setup.ovfl_mode = 1;
187 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
188 }
189
190 #ifdef notyet
191 int cxio_resize_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
192 {
193 struct rdma_cq_setup setup;
194 setup.id = cq->cqid;
195 setup.base_addr = (u64) (cq->dma_addr);
196 setup.size = 1UL << cq->size_log2;
197 setup.credits = setup.size;
198 setup.credit_thres = setup.size; /* TBD: overflow recovery */
199 setup.ovfl_mode = 1;
200 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
201 }
202 #endif
203
204 static u32 get_qpid(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
205 {
206 struct cxio_qpid_list *entry;
207 u32 qpid;
208 int i;
209
210 mutex_lock(&uctx->lock);
211 if (!list_empty(&uctx->qpids)) {
212 entry = list_entry(uctx->qpids.next, struct cxio_qpid_list,
213 entry);
214 list_del(&entry->entry);
215 qpid = entry->qpid;
216 kfree(entry);
217 } else {
218 qpid = cxio_hal_get_qpid(rdev_p->rscp);
219 if (!qpid)
220 goto out;
221 for (i = qpid+1; i & rdev_p->qpmask; i++) {
222 entry = kmalloc(sizeof *entry, GFP_KERNEL);
223 if (!entry)
224 break;
225 entry->qpid = i;
226 list_add_tail(&entry->entry, &uctx->qpids);
227 }
228 }
229 out:
230 mutex_unlock(&uctx->lock);
231 pr_debug("%s qpid 0x%x\n", __func__, qpid);
232 return qpid;
233 }
234
235 static void put_qpid(struct cxio_rdev *rdev_p, u32 qpid,
236 struct cxio_ucontext *uctx)
237 {
238 struct cxio_qpid_list *entry;
239
240 entry = kmalloc(sizeof *entry, GFP_KERNEL);
241 if (!entry)
242 return;
243 pr_debug("%s qpid 0x%x\n", __func__, qpid);
244 entry->qpid = qpid;
245 mutex_lock(&uctx->lock);
246 list_add_tail(&entry->entry, &uctx->qpids);
247 mutex_unlock(&uctx->lock);
248 }
249
250 void cxio_release_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
251 {
252 struct list_head *pos, *nxt;
253 struct cxio_qpid_list *entry;
254
255 mutex_lock(&uctx->lock);
256 list_for_each_safe(pos, nxt, &uctx->qpids) {
257 entry = list_entry(pos, struct cxio_qpid_list, entry);
258 list_del_init(&entry->entry);
259 if (!(entry->qpid & rdev_p->qpmask))
260 cxio_hal_put_qpid(rdev_p->rscp, entry->qpid);
261 kfree(entry);
262 }
263 mutex_unlock(&uctx->lock);
264 }
265
266 void cxio_init_ucontext(struct cxio_rdev *rdev_p, struct cxio_ucontext *uctx)
267 {
268 INIT_LIST_HEAD(&uctx->qpids);
269 mutex_init(&uctx->lock);
270 }
271
272 int cxio_create_qp(struct cxio_rdev *rdev_p, u32 kernel_domain,
273 struct t3_wq *wq, struct cxio_ucontext *uctx)
274 {
275 int depth = 1UL << wq->size_log2;
276 int rqsize = 1UL << wq->rq_size_log2;
277
278 wq->qpid = get_qpid(rdev_p, uctx);
279 if (!wq->qpid)
280 return -ENOMEM;
281
282 wq->rq = kcalloc(depth, sizeof(struct t3_swrq), GFP_KERNEL);
283 if (!wq->rq)
284 goto err1;
285
286 wq->rq_addr = cxio_hal_rqtpool_alloc(rdev_p, rqsize);
287 if (!wq->rq_addr)
288 goto err2;
289
290 wq->sq = kcalloc(depth, sizeof(struct t3_swsq), GFP_KERNEL);
291 if (!wq->sq)
292 goto err3;
293
294 wq->queue = dma_alloc_coherent(&(rdev_p->rnic_info.pdev->dev),
295 depth * sizeof(union t3_wr),
296 &(wq->dma_addr), GFP_KERNEL);
297 if (!wq->queue)
298 goto err4;
299
300 dma_unmap_addr_set(wq, mapping, wq->dma_addr);
301 wq->doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
302 if (!kernel_domain)
303 wq->udb = (u64)rdev_p->rnic_info.udbell_physbase +
304 (wq->qpid << rdev_p->qpshift);
305 wq->rdev = rdev_p;
306 pr_debug("%s qpid 0x%x doorbell 0x%p udb 0x%llx\n",
307 __func__, wq->qpid, wq->doorbell, (unsigned long long)wq->udb);
308 return 0;
309 err4:
310 kfree(wq->sq);
311 err3:
312 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, rqsize);
313 err2:
314 kfree(wq->rq);
315 err1:
316 put_qpid(rdev_p, wq->qpid, uctx);
317 return -ENOMEM;
318 }
319
320 int cxio_destroy_cq(struct cxio_rdev *rdev_p, struct t3_cq *cq)
321 {
322 int err;
323 err = cxio_hal_clear_cq_ctx(rdev_p, cq->cqid);
324 kfree(cq->sw_queue);
325 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
326 (1UL << (cq->size_log2))
327 * sizeof(struct t3_cqe) + 1, cq->queue,
328 dma_unmap_addr(cq, mapping));
329 cxio_hal_put_cqid(rdev_p->rscp, cq->cqid);
330 return err;
331 }
332
333 int cxio_destroy_qp(struct cxio_rdev *rdev_p, struct t3_wq *wq,
334 struct cxio_ucontext *uctx)
335 {
336 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
337 (1UL << (wq->size_log2))
338 * sizeof(union t3_wr), wq->queue,
339 dma_unmap_addr(wq, mapping));
340 kfree(wq->sq);
341 cxio_hal_rqtpool_free(rdev_p, wq->rq_addr, (1UL << wq->rq_size_log2));
342 kfree(wq->rq);
343 put_qpid(rdev_p, wq->qpid, uctx);
344 return 0;
345 }
346
347 static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq)
348 {
349 struct t3_cqe cqe;
350
351 pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
352 wq, cq, cq->sw_rptr, cq->sw_wptr);
353 memset(&cqe, 0, sizeof(cqe));
354 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
355 V_CQE_OPCODE(T3_SEND) |
356 V_CQE_TYPE(0) |
357 V_CQE_SWCQE(1) |
358 V_CQE_QPID(wq->qpid) |
359 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
360 cq->size_log2)));
361 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
362 cq->sw_wptr++;
363 }
364
365 int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count)
366 {
367 u32 ptr;
368 int flushed = 0;
369
370 pr_debug("%s wq %p cq %p\n", __func__, wq, cq);
371
372 /* flush RQ */
373 pr_debug("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__,
374 wq->rq_rptr, wq->rq_wptr, count);
375 ptr = wq->rq_rptr + count;
376 while (ptr++ != wq->rq_wptr) {
377 insert_recv_cqe(wq, cq);
378 flushed++;
379 }
380 return flushed;
381 }
382
383 static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq,
384 struct t3_swsq *sqp)
385 {
386 struct t3_cqe cqe;
387
388 pr_debug("%s wq %p cq %p sw_rptr 0x%x sw_wptr 0x%x\n", __func__,
389 wq, cq, cq->sw_rptr, cq->sw_wptr);
390 memset(&cqe, 0, sizeof(cqe));
391 cqe.header = cpu_to_be32(V_CQE_STATUS(TPT_ERR_SWFLUSH) |
392 V_CQE_OPCODE(sqp->opcode) |
393 V_CQE_TYPE(1) |
394 V_CQE_SWCQE(1) |
395 V_CQE_QPID(wq->qpid) |
396 V_CQE_GENBIT(Q_GENBIT(cq->sw_wptr,
397 cq->size_log2)));
398 cqe.u.scqe.wrid_hi = sqp->sq_wptr;
399
400 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2)) = cqe;
401 cq->sw_wptr++;
402 }
403
404 int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count)
405 {
406 __u32 ptr = wq->sq_rptr + count;
407 int flushed = 0;
408 struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
409
410 while (ptr != wq->sq_wptr) {
411 sqp->signaled = 0;
412 insert_sq_cqe(wq, cq, sqp);
413 ptr++;
414 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
415 flushed++;
416 }
417 return flushed;
418 }
419
420 /*
421 * Move all CQEs from the HWCQ into the SWCQ.
422 */
423 void cxio_flush_hw_cq(struct t3_cq *cq)
424 {
425 struct t3_cqe *cqe, *swcqe;
426
427 pr_debug("%s cq %p cqid 0x%x\n", __func__, cq, cq->cqid);
428 cqe = cxio_next_hw_cqe(cq);
429 while (cqe) {
430 pr_debug("%s flushing hwcq rptr 0x%x to swcq wptr 0x%x\n",
431 __func__, cq->rptr, cq->sw_wptr);
432 swcqe = cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2);
433 *swcqe = *cqe;
434 swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
435 cq->sw_wptr++;
436 cq->rptr++;
437 cqe = cxio_next_hw_cqe(cq);
438 }
439 }
440
441 static int cqe_completes_wr(struct t3_cqe *cqe, struct t3_wq *wq)
442 {
443 if (CQE_OPCODE(*cqe) == T3_TERMINATE)
444 return 0;
445
446 if ((CQE_OPCODE(*cqe) == T3_RDMA_WRITE) && RQ_TYPE(*cqe))
447 return 0;
448
449 if ((CQE_OPCODE(*cqe) == T3_READ_RESP) && SQ_TYPE(*cqe))
450 return 0;
451
452 if (CQE_SEND_OPCODE(*cqe) && RQ_TYPE(*cqe) &&
453 Q_EMPTY(wq->rq_rptr, wq->rq_wptr))
454 return 0;
455
456 return 1;
457 }
458
459 void cxio_count_scqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
460 {
461 struct t3_cqe *cqe;
462 u32 ptr;
463
464 *count = 0;
465 ptr = cq->sw_rptr;
466 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
467 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
468 if ((SQ_TYPE(*cqe) ||
469 ((CQE_OPCODE(*cqe) == T3_READ_RESP) && wq->oldest_read)) &&
470 (CQE_QPID(*cqe) == wq->qpid))
471 (*count)++;
472 ptr++;
473 }
474 pr_debug("%s cq %p count %d\n", __func__, cq, *count);
475 }
476
477 void cxio_count_rcqes(struct t3_cq *cq, struct t3_wq *wq, int *count)
478 {
479 struct t3_cqe *cqe;
480 u32 ptr;
481
482 *count = 0;
483 pr_debug("%s count zero %d\n", __func__, *count);
484 ptr = cq->sw_rptr;
485 while (!Q_EMPTY(ptr, cq->sw_wptr)) {
486 cqe = cq->sw_queue + (Q_PTR2IDX(ptr, cq->size_log2));
487 if (RQ_TYPE(*cqe) && (CQE_OPCODE(*cqe) != T3_READ_RESP) &&
488 (CQE_QPID(*cqe) == wq->qpid) && cqe_completes_wr(cqe, wq))
489 (*count)++;
490 ptr++;
491 }
492 pr_debug("%s cq %p count %d\n", __func__, cq, *count);
493 }
494
495 static int cxio_hal_init_ctrl_cq(struct cxio_rdev *rdev_p)
496 {
497 struct rdma_cq_setup setup;
498 setup.id = 0;
499 setup.base_addr = 0; /* NULL address */
500 setup.size = 1; /* enable the CQ */
501 setup.credits = 0;
502
503 /* force SGE to redirect to RspQ and interrupt */
504 setup.credit_thres = 0;
505 setup.ovfl_mode = 1;
506 return (rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_CQ_SETUP, &setup));
507 }
508
509 static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p)
510 {
511 int err;
512 u64 sge_cmd, ctx0, ctx1;
513 u64 base_addr;
514 struct t3_modify_qp_wr *wqe;
515 struct sk_buff *skb;
516
517 skb = alloc_skb(sizeof(*wqe), GFP_KERNEL);
518 if (!skb) {
519 pr_debug("%s alloc_skb failed\n", __func__);
520 return -ENOMEM;
521 }
522 err = cxio_hal_init_ctrl_cq(rdev_p);
523 if (err) {
524 pr_debug("%s err %d initializing ctrl_cq\n", __func__, err);
525 goto err;
526 }
527 rdev_p->ctrl_qp.workq = dma_alloc_coherent(
528 &(rdev_p->rnic_info.pdev->dev),
529 (1 << T3_CTRL_QP_SIZE_LOG2) *
530 sizeof(union t3_wr),
531 &(rdev_p->ctrl_qp.dma_addr),
532 GFP_KERNEL);
533 if (!rdev_p->ctrl_qp.workq) {
534 pr_debug("%s dma_alloc_coherent failed\n", __func__);
535 err = -ENOMEM;
536 goto err;
537 }
538 dma_unmap_addr_set(&rdev_p->ctrl_qp, mapping,
539 rdev_p->ctrl_qp.dma_addr);
540 rdev_p->ctrl_qp.doorbell = (void __iomem *)rdev_p->rnic_info.kdb_addr;
541 memset(rdev_p->ctrl_qp.workq, 0,
542 (1 << T3_CTRL_QP_SIZE_LOG2) * sizeof(union t3_wr));
543
544 mutex_init(&rdev_p->ctrl_qp.lock);
545 init_waitqueue_head(&rdev_p->ctrl_qp.waitq);
546
547 /* update HW Ctrl QP context */
548 base_addr = rdev_p->ctrl_qp.dma_addr;
549 base_addr >>= 12;
550 ctx0 = (V_EC_SIZE((1 << T3_CTRL_QP_SIZE_LOG2)) |
551 V_EC_BASE_LO((u32) base_addr & 0xffff));
552 ctx0 <<= 32;
553 ctx0 |= V_EC_CREDITS(FW_WR_NUM);
554 base_addr >>= 16;
555 ctx1 = (u32) base_addr;
556 base_addr >>= 32;
557 ctx1 |= ((u64) (V_EC_BASE_HI((u32) base_addr & 0xf) | V_EC_RESPQ(0) |
558 V_EC_TYPE(0) | V_EC_GEN(1) |
559 V_EC_UP_TOKEN(T3_CTL_QP_TID) | F_EC_VALID)) << 32;
560 wqe = skb_put_zero(skb, sizeof(*wqe));
561 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0,
562 T3_CTL_QP_TID, 7, T3_SOPEOP);
563 wqe->flags = cpu_to_be32(MODQP_WRITE_EC);
564 sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3;
565 wqe->sge_cmd = cpu_to_be64(sge_cmd);
566 wqe->ctx1 = cpu_to_be64(ctx1);
567 wqe->ctx0 = cpu_to_be64(ctx0);
568 pr_debug("CtrlQP dma_addr 0x%llx workq %p size %d\n",
569 (unsigned long long)rdev_p->ctrl_qp.dma_addr,
570 rdev_p->ctrl_qp.workq, 1 << T3_CTRL_QP_SIZE_LOG2);
571 skb->priority = CPL_PRIORITY_CONTROL;
572 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
573 err:
574 kfree_skb(skb);
575 return err;
576 }
577
578 static int cxio_hal_destroy_ctrl_qp(struct cxio_rdev *rdev_p)
579 {
580 dma_free_coherent(&(rdev_p->rnic_info.pdev->dev),
581 (1UL << T3_CTRL_QP_SIZE_LOG2)
582 * sizeof(union t3_wr), rdev_p->ctrl_qp.workq,
583 dma_unmap_addr(&rdev_p->ctrl_qp, mapping));
584 return cxio_hal_clear_qp_ctx(rdev_p, T3_CTRL_QP_ID);
585 }
586
587 /* write len bytes of data into addr (32B aligned address)
588 * If data is NULL, clear len byte of memory to zero.
589 * caller acquires the ctrl_qp lock before the call
590 */
591 static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr,
592 u32 len, void *data)
593 {
594 u32 i, nr_wqe, copy_len;
595 u8 *copy_data;
596 u8 wr_len, utx_len; /* length in 8 byte flit */
597 enum t3_wr_flags flag;
598 __be64 *wqe;
599 u64 utx_cmd;
600 addr &= 0x7FFFFFF;
601 nr_wqe = len % 96 ? len / 96 + 1 : len / 96; /* 96B max per WQE */
602 pr_debug("%s wptr 0x%x rptr 0x%x len %d, nr_wqe %d data %p addr 0x%0x\n",
603 __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len,
604 nr_wqe, data, addr);
605 utx_len = 3; /* in 32B unit */
606 for (i = 0; i < nr_wqe; i++) {
607 if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr,
608 T3_CTRL_QP_SIZE_LOG2)) {
609 pr_debug("%s ctrl_qp full wtpr 0x%0x rptr 0x%0x, wait for more space i %d\n",
610 __func__,
611 rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i);
612 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
613 !Q_FULL(rdev_p->ctrl_qp.rptr,
614 rdev_p->ctrl_qp.wptr,
615 T3_CTRL_QP_SIZE_LOG2))) {
616 pr_debug("%s ctrl_qp workq interrupted\n",
617 __func__);
618 return -ERESTARTSYS;
619 }
620 pr_debug("%s ctrl_qp wakeup, continue posting work request i %d\n",
621 __func__, i);
622 }
623 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
624 (1 << T3_CTRL_QP_SIZE_LOG2)));
625 flag = 0;
626 if (i == (nr_wqe - 1)) {
627 /* last WQE */
628 flag = T3_COMPLETION_FLAG;
629 if (len % 32)
630 utx_len = len / 32 + 1;
631 else
632 utx_len = len / 32;
633 }
634
635 /*
636 * Force a CQE to return the credit to the workq in case
637 * we posted more than half the max QP size of WRs
638 */
639 if ((i != 0) &&
640 (i % (((1 << T3_CTRL_QP_SIZE_LOG2)) >> 1) == 0)) {
641 flag = T3_COMPLETION_FLAG;
642 pr_debug("%s force completion at i %d\n", __func__, i);
643 }
644
645 /* build the utx mem command */
646 wqe += (sizeof(struct t3_bypass_wr) >> 3);
647 utx_cmd = (T3_UTX_MEM_WRITE << 28) | (addr + i * 3);
648 utx_cmd <<= 32;
649 utx_cmd |= (utx_len << 28) | ((utx_len << 2) + 1);
650 *wqe = cpu_to_be64(utx_cmd);
651 wqe++;
652 copy_data = (u8 *) data + i * 96;
653 copy_len = len > 96 ? 96 : len;
654
655 /* clear memory content if data is NULL */
656 if (data)
657 memcpy(wqe, copy_data, copy_len);
658 else
659 memset(wqe, 0, copy_len);
660 if (copy_len % 32)
661 memset(((u8 *) wqe) + copy_len, 0,
662 32 - (copy_len % 32));
663 wr_len = ((sizeof(struct t3_bypass_wr)) >> 3) + 1 +
664 (utx_len << 2);
665 wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr %
666 (1 << T3_CTRL_QP_SIZE_LOG2)));
667
668 /* wptr in the WRID[31:0] */
669 ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr;
670
671 /*
672 * This must be the last write with a memory barrier
673 * for the genbit
674 */
675 build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag,
676 Q_GENBIT(rdev_p->ctrl_qp.wptr,
677 T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID,
678 wr_len, T3_SOPEOP);
679 if (flag == T3_COMPLETION_FLAG)
680 ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID);
681 len -= 96;
682 rdev_p->ctrl_qp.wptr++;
683 }
684 return 0;
685 }
686
687 /* IN: stag key, pdid, perm, zbva, to, len, page_size, pbl_size and pbl_addr
688 * OUT: stag index
689 * TBD: shared memory region support
690 */
691 static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry,
692 u32 *stag, u8 stag_state, u32 pdid,
693 enum tpt_mem_type type, enum tpt_mem_perm perm,
694 u32 zbva, u64 to, u32 len, u8 page_size,
695 u32 pbl_size, u32 pbl_addr)
696 {
697 int err;
698 struct tpt_entry tpt;
699 u32 stag_idx;
700 u32 wptr;
701
702 if (cxio_fatal_error(rdev_p))
703 return -EIO;
704
705 stag_state = stag_state > 0;
706 stag_idx = (*stag) >> 8;
707
708 if ((!reset_tpt_entry) && !(*stag != T3_STAG_UNSET)) {
709 stag_idx = cxio_hal_get_stag(rdev_p->rscp);
710 if (!stag_idx)
711 return -ENOMEM;
712 *stag = (stag_idx << 8) | ((*stag) & 0xFF);
713 }
714 pr_debug("%s stag_state 0x%0x type 0x%0x pdid 0x%0x, stag_idx 0x%x\n",
715 __func__, stag_state, type, pdid, stag_idx);
716
717 mutex_lock(&rdev_p->ctrl_qp.lock);
718
719 /* write TPT entry */
720 if (reset_tpt_entry)
721 memset(&tpt, 0, sizeof(tpt));
722 else {
723 tpt.valid_stag_pdid = cpu_to_be32(F_TPT_VALID |
724 V_TPT_STAG_KEY((*stag) & M_TPT_STAG_KEY) |
725 V_TPT_STAG_STATE(stag_state) |
726 V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid));
727 BUG_ON(page_size >= 28);
728 tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) |
729 ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) |
730 V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) |
731 V_TPT_PAGE_SIZE(page_size));
732 tpt.rsvd_pbl_addr = cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3));
733 tpt.len = cpu_to_be32(len);
734 tpt.va_hi = cpu_to_be32((u32) (to >> 32));
735 tpt.va_low_or_fbo = cpu_to_be32((u32) (to & 0xFFFFFFFFULL));
736 tpt.rsvd_bind_cnt_or_pstag = 0;
737 tpt.rsvd_pbl_size = cpu_to_be32(V_TPT_PBL_SIZE(pbl_size >> 2));
738 }
739 err = cxio_hal_ctrl_qp_write_mem(rdev_p,
740 stag_idx +
741 (rdev_p->rnic_info.tpt_base >> 5),
742 sizeof(tpt), &tpt);
743
744 /* release the stag index to free pool */
745 if (reset_tpt_entry)
746 cxio_hal_put_stag(rdev_p->rscp, stag_idx);
747
748 wptr = rdev_p->ctrl_qp.wptr;
749 mutex_unlock(&rdev_p->ctrl_qp.lock);
750 if (!err)
751 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
752 SEQ32_GE(rdev_p->ctrl_qp.rptr,
753 wptr)))
754 return -ERESTARTSYS;
755 return err;
756 }
757
758 int cxio_write_pbl(struct cxio_rdev *rdev_p, __be64 *pbl,
759 u32 pbl_addr, u32 pbl_size)
760 {
761 u32 wptr;
762 int err;
763
764 pr_debug("%s *pdb_addr 0x%x, pbl_base 0x%x, pbl_size %d\n",
765 __func__, pbl_addr, rdev_p->rnic_info.pbl_base,
766 pbl_size);
767
768 mutex_lock(&rdev_p->ctrl_qp.lock);
769 err = cxio_hal_ctrl_qp_write_mem(rdev_p, pbl_addr >> 5, pbl_size << 3,
770 pbl);
771 wptr = rdev_p->ctrl_qp.wptr;
772 mutex_unlock(&rdev_p->ctrl_qp.lock);
773 if (err)
774 return err;
775
776 if (wait_event_interruptible(rdev_p->ctrl_qp.waitq,
777 SEQ32_GE(rdev_p->ctrl_qp.rptr,
778 wptr)))
779 return -ERESTARTSYS;
780
781 return 0;
782 }
783
784 int cxio_register_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
785 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
786 u8 page_size, u32 pbl_size, u32 pbl_addr)
787 {
788 *stag = T3_STAG_UNSET;
789 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
790 zbva, to, len, page_size, pbl_size, pbl_addr);
791 }
792
793 int cxio_reregister_phys_mem(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid,
794 enum tpt_mem_perm perm, u32 zbva, u64 to, u32 len,
795 u8 page_size, u32 pbl_size, u32 pbl_addr)
796 {
797 return __cxio_tpt_op(rdev_p, 0, stag, 1, pdid, TPT_NON_SHARED_MR, perm,
798 zbva, to, len, page_size, pbl_size, pbl_addr);
799 }
800
801 int cxio_dereg_mem(struct cxio_rdev *rdev_p, u32 stag, u32 pbl_size,
802 u32 pbl_addr)
803 {
804 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
805 pbl_size, pbl_addr);
806 }
807
808 int cxio_allocate_window(struct cxio_rdev *rdev_p, u32 * stag, u32 pdid)
809 {
810 *stag = T3_STAG_UNSET;
811 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_MW, 0, 0, 0ULL, 0, 0,
812 0, 0);
813 }
814
815 int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag)
816 {
817 return __cxio_tpt_op(rdev_p, 1, &stag, 0, 0, 0, 0, 0, 0ULL, 0, 0,
818 0, 0);
819 }
820
821 int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr)
822 {
823 *stag = T3_STAG_UNSET;
824 return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR,
825 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr);
826 }
827
828 int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr)
829 {
830 struct t3_rdma_init_wr *wqe;
831 struct sk_buff *skb = alloc_skb(sizeof(*wqe), GFP_ATOMIC);
832 if (!skb)
833 return -ENOMEM;
834 pr_debug("%s rdev_p %p\n", __func__, rdev_p);
835 wqe = __skb_put(skb, sizeof(*wqe));
836 wqe->wrh.op_seop_flags = cpu_to_be32(V_FW_RIWR_OP(T3_WR_INIT));
837 wqe->wrh.gen_tid_len = cpu_to_be32(V_FW_RIWR_TID(attr->tid) |
838 V_FW_RIWR_LEN(sizeof(*wqe) >> 3));
839 wqe->wrid.id1 = 0;
840 wqe->qpid = cpu_to_be32(attr->qpid);
841 wqe->pdid = cpu_to_be32(attr->pdid);
842 wqe->scqid = cpu_to_be32(attr->scqid);
843 wqe->rcqid = cpu_to_be32(attr->rcqid);
844 wqe->rq_addr = cpu_to_be32(attr->rq_addr - rdev_p->rnic_info.rqt_base);
845 wqe->rq_size = cpu_to_be32(attr->rq_size);
846 wqe->mpaattrs = attr->mpaattrs;
847 wqe->qpcaps = attr->qpcaps;
848 wqe->ulpdu_size = cpu_to_be16(attr->tcp_emss);
849 wqe->rqe_count = cpu_to_be16(attr->rqe_count);
850 wqe->flags_rtr_type = cpu_to_be16(attr->flags |
851 V_RTR_TYPE(attr->rtr_type) |
852 V_CHAN(attr->chan));
853 wqe->ord = cpu_to_be32(attr->ord);
854 wqe->ird = cpu_to_be32(attr->ird);
855 wqe->qp_dma_addr = cpu_to_be64(attr->qp_dma_addr);
856 wqe->qp_dma_size = cpu_to_be32(attr->qp_dma_size);
857 wqe->irs = cpu_to_be32(attr->irs);
858 skb->priority = 0; /* 0=>ToeQ; 1=>CtrlQ */
859 return iwch_cxgb3_ofld_send(rdev_p->t3cdev_p, skb);
860 }
861
862 void cxio_register_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
863 {
864 cxio_ev_cb = ev_cb;
865 }
866
867 void cxio_unregister_ev_cb(cxio_hal_ev_callback_func_t ev_cb)
868 {
869 cxio_ev_cb = NULL;
870 }
871
872 static int cxio_hal_ev_handler(struct t3cdev *t3cdev_p, struct sk_buff *skb)
873 {
874 static int cnt;
875 struct cxio_rdev *rdev_p = NULL;
876 struct respQ_msg_t *rsp_msg = (struct respQ_msg_t *) skb->data;
877 pr_debug("%d: %s cq_id 0x%x cq_ptr 0x%x genbit %0x overflow %0x an %0x se %0x notify %0x cqbranch %0x creditth %0x\n",
878 cnt, __func__, RSPQ_CQID(rsp_msg), RSPQ_CQPTR(rsp_msg),
879 RSPQ_GENBIT(rsp_msg), RSPQ_OVERFLOW(rsp_msg), RSPQ_AN(rsp_msg),
880 RSPQ_SE(rsp_msg), RSPQ_NOTIFY(rsp_msg), RSPQ_CQBRANCH(rsp_msg),
881 RSPQ_CREDIT_THRESH(rsp_msg));
882 pr_debug("CQE: QPID 0x%0x genbit %0x type 0x%0x status 0x%0x opcode %d len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
883 CQE_QPID(rsp_msg->cqe), CQE_GENBIT(rsp_msg->cqe),
884 CQE_TYPE(rsp_msg->cqe), CQE_STATUS(rsp_msg->cqe),
885 CQE_OPCODE(rsp_msg->cqe), CQE_LEN(rsp_msg->cqe),
886 CQE_WRID_HI(rsp_msg->cqe), CQE_WRID_LOW(rsp_msg->cqe));
887 rdev_p = (struct cxio_rdev *)t3cdev_p->ulp;
888 if (!rdev_p) {
889 pr_debug("%s called by t3cdev %p with null ulp\n", __func__,
890 t3cdev_p);
891 return 0;
892 }
893 if (CQE_QPID(rsp_msg->cqe) == T3_CTRL_QP_ID) {
894 rdev_p->ctrl_qp.rptr = CQE_WRID_LOW(rsp_msg->cqe) + 1;
895 wake_up_interruptible(&rdev_p->ctrl_qp.waitq);
896 dev_kfree_skb_irq(skb);
897 } else if (CQE_QPID(rsp_msg->cqe) == 0xfff8)
898 dev_kfree_skb_irq(skb);
899 else if (cxio_ev_cb)
900 (*cxio_ev_cb) (rdev_p, skb);
901 else
902 dev_kfree_skb_irq(skb);
903 cnt++;
904 return 0;
905 }
906
907 /* Caller takes care of locking if needed */
908 int cxio_rdev_open(struct cxio_rdev *rdev_p)
909 {
910 struct net_device *netdev_p = NULL;
911 int err = 0;
912 if (strlen(rdev_p->dev_name)) {
913 if (cxio_hal_find_rdev_by_name(rdev_p->dev_name)) {
914 return -EBUSY;
915 }
916 netdev_p = dev_get_by_name(&init_net, rdev_p->dev_name);
917 if (!netdev_p) {
918 return -EINVAL;
919 }
920 dev_put(netdev_p);
921 } else if (rdev_p->t3cdev_p) {
922 if (cxio_hal_find_rdev_by_t3cdev(rdev_p->t3cdev_p)) {
923 return -EBUSY;
924 }
925 netdev_p = rdev_p->t3cdev_p->lldev;
926 strncpy(rdev_p->dev_name, rdev_p->t3cdev_p->name,
927 T3_MAX_DEV_NAME_LEN);
928 } else {
929 pr_debug("%s t3cdev_p or dev_name must be set\n", __func__);
930 return -EINVAL;
931 }
932
933 list_add_tail(&rdev_p->entry, &rdev_list);
934
935 pr_debug("%s opening rnic dev %s\n", __func__, rdev_p->dev_name);
936 memset(&rdev_p->ctrl_qp, 0, sizeof(rdev_p->ctrl_qp));
937 if (!rdev_p->t3cdev_p)
938 rdev_p->t3cdev_p = dev2t3cdev(netdev_p);
939 rdev_p->t3cdev_p->ulp = (void *) rdev_p;
940
941 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_EMBEDDED_INFO,
942 &(rdev_p->fw_info));
943 if (err) {
944 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
945 __func__, rdev_p->t3cdev_p, err);
946 goto err1;
947 }
948 if (G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers) != CXIO_FW_MAJ) {
949 pr_err("fatal firmware version mismatch: need version %u but adapter has version %u\n",
950 CXIO_FW_MAJ,
951 G_FW_VERSION_MAJOR(rdev_p->fw_info.fw_vers));
952 err = -EINVAL;
953 goto err1;
954 }
955
956 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, RDMA_GET_PARAMS,
957 &(rdev_p->rnic_info));
958 if (err) {
959 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
960 __func__, rdev_p->t3cdev_p, err);
961 goto err1;
962 }
963 err = rdev_p->t3cdev_p->ctl(rdev_p->t3cdev_p, GET_PORTS,
964 &(rdev_p->port_info));
965 if (err) {
966 pr_err("%s t3cdev_p(%p)->ctl returned error %d\n",
967 __func__, rdev_p->t3cdev_p, err);
968 goto err1;
969 }
970
971 /*
972 * qpshift is the number of bits to shift the qpid left in order
973 * to get the correct address of the doorbell for that qp.
974 */
975 cxio_init_ucontext(rdev_p, &rdev_p->uctx);
976 rdev_p->qpshift = PAGE_SHIFT -
977 ilog2(65536 >>
978 ilog2(rdev_p->rnic_info.udbell_len >>
979 PAGE_SHIFT));
980 rdev_p->qpnr = rdev_p->rnic_info.udbell_len >> PAGE_SHIFT;
981 rdev_p->qpmask = (65536 >> ilog2(rdev_p->qpnr)) - 1;
982 pr_debug("%s rnic %s info: tpt_base 0x%0x tpt_top 0x%0x num stags %d pbl_base 0x%0x pbl_top 0x%0x rqt_base 0x%0x, rqt_top 0x%0x\n",
983 __func__, rdev_p->dev_name, rdev_p->rnic_info.tpt_base,
984 rdev_p->rnic_info.tpt_top, cxio_num_stags(rdev_p),
985 rdev_p->rnic_info.pbl_base,
986 rdev_p->rnic_info.pbl_top, rdev_p->rnic_info.rqt_base,
987 rdev_p->rnic_info.rqt_top);
988 pr_debug("udbell_len 0x%0x udbell_physbase 0x%lx kdb_addr %p qpshift %lu qpnr %d qpmask 0x%x\n",
989 rdev_p->rnic_info.udbell_len,
990 rdev_p->rnic_info.udbell_physbase, rdev_p->rnic_info.kdb_addr,
991 rdev_p->qpshift, rdev_p->qpnr, rdev_p->qpmask);
992
993 err = cxio_hal_init_ctrl_qp(rdev_p);
994 if (err) {
995 pr_err("%s error %d initializing ctrl_qp\n", __func__, err);
996 goto err1;
997 }
998 err = cxio_hal_init_resource(rdev_p, cxio_num_stags(rdev_p), 0,
999 0, T3_MAX_NUM_QP, T3_MAX_NUM_CQ,
1000 T3_MAX_NUM_PD);
1001 if (err) {
1002 pr_err("%s error %d initializing hal resources\n",
1003 __func__, err);
1004 goto err2;
1005 }
1006 err = cxio_hal_pblpool_create(rdev_p);
1007 if (err) {
1008 pr_err("%s error %d initializing pbl mem pool\n",
1009 __func__, err);
1010 goto err3;
1011 }
1012 err = cxio_hal_rqtpool_create(rdev_p);
1013 if (err) {
1014 pr_err("%s error %d initializing rqt mem pool\n",
1015 __func__, err);
1016 goto err4;
1017 }
1018 return 0;
1019 err4:
1020 cxio_hal_pblpool_destroy(rdev_p);
1021 err3:
1022 cxio_hal_destroy_resource(rdev_p->rscp);
1023 err2:
1024 cxio_hal_destroy_ctrl_qp(rdev_p);
1025 err1:
1026 rdev_p->t3cdev_p->ulp = NULL;
1027 list_del(&rdev_p->entry);
1028 return err;
1029 }
1030
1031 void cxio_rdev_close(struct cxio_rdev *rdev_p)
1032 {
1033 if (rdev_p) {
1034 cxio_hal_pblpool_destroy(rdev_p);
1035 cxio_hal_rqtpool_destroy(rdev_p);
1036 list_del(&rdev_p->entry);
1037 cxio_hal_destroy_ctrl_qp(rdev_p);
1038 cxio_hal_destroy_resource(rdev_p->rscp);
1039 rdev_p->t3cdev_p->ulp = NULL;
1040 }
1041 }
1042
1043 int __init cxio_hal_init(void)
1044 {
1045 if (cxio_hal_init_rhdl_resource(T3_MAX_NUM_RI))
1046 return -ENOMEM;
1047 t3_register_cpl_handler(CPL_ASYNC_NOTIF, cxio_hal_ev_handler);
1048 return 0;
1049 }
1050
1051 void __exit cxio_hal_exit(void)
1052 {
1053 struct cxio_rdev *rdev, *tmp;
1054
1055 t3_register_cpl_handler(CPL_ASYNC_NOTIF, NULL);
1056 list_for_each_entry_safe(rdev, tmp, &rdev_list, entry)
1057 cxio_rdev_close(rdev);
1058 cxio_hal_destroy_rhdl_resource();
1059 }
1060
1061 static void flush_completed_wrs(struct t3_wq *wq, struct t3_cq *cq)
1062 {
1063 struct t3_swsq *sqp;
1064 __u32 ptr = wq->sq_rptr;
1065 int count = Q_COUNT(wq->sq_rptr, wq->sq_wptr);
1066
1067 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1068 while (count--)
1069 if (!sqp->signaled) {
1070 ptr++;
1071 sqp = wq->sq + Q_PTR2IDX(ptr, wq->sq_size_log2);
1072 } else if (sqp->complete) {
1073
1074 /*
1075 * Insert this completed cqe into the swcq.
1076 */
1077 pr_debug("%s moving cqe into swcq sq idx %ld cq idx %ld\n",
1078 __func__, Q_PTR2IDX(ptr, wq->sq_size_log2),
1079 Q_PTR2IDX(cq->sw_wptr, cq->size_log2));
1080 sqp->cqe.header |= htonl(V_CQE_SWCQE(1));
1081 *(cq->sw_queue + Q_PTR2IDX(cq->sw_wptr, cq->size_log2))
1082 = sqp->cqe;
1083 cq->sw_wptr++;
1084 sqp->signaled = 0;
1085 break;
1086 } else
1087 break;
1088 }
1089
1090 static void create_read_req_cqe(struct t3_wq *wq, struct t3_cqe *hw_cqe,
1091 struct t3_cqe *read_cqe)
1092 {
1093 read_cqe->u.scqe.wrid_hi = wq->oldest_read->sq_wptr;
1094 read_cqe->len = wq->oldest_read->read_len;
1095 read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(*hw_cqe)) |
1096 V_CQE_SWCQE(SW_CQE(*hw_cqe)) |
1097 V_CQE_OPCODE(T3_READ_REQ) |
1098 V_CQE_TYPE(1));
1099 }
1100
1101 /*
1102 * Return a ptr to the next read wr in the SWSQ or NULL.
1103 */
1104 static void advance_oldest_read(struct t3_wq *wq)
1105 {
1106
1107 u32 rptr = wq->oldest_read - wq->sq + 1;
1108 u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2);
1109
1110 while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) {
1111 wq->oldest_read = wq->sq + Q_PTR2IDX(rptr, wq->sq_size_log2);
1112
1113 if (wq->oldest_read->opcode == T3_READ_REQ)
1114 return;
1115 rptr++;
1116 }
1117 wq->oldest_read = NULL;
1118 }
1119
1120 /*
1121 * cxio_poll_cq
1122 *
1123 * Caller must:
1124 * check the validity of the first CQE,
1125 * supply the wq assicated with the qpid.
1126 *
1127 * credit: cq credit to return to sge.
1128 * cqe_flushed: 1 iff the CQE is flushed.
1129 * cqe: copy of the polled CQE.
1130 *
1131 * return value:
1132 * 0 CQE returned,
1133 * -1 CQE skipped, try again.
1134 */
1135 int cxio_poll_cq(struct t3_wq *wq, struct t3_cq *cq, struct t3_cqe *cqe,
1136 u8 *cqe_flushed, u64 *cookie, u32 *credit)
1137 {
1138 int ret = 0;
1139 struct t3_cqe *hw_cqe, read_cqe;
1140
1141 *cqe_flushed = 0;
1142 *credit = 0;
1143 hw_cqe = cxio_next_cqe(cq);
1144
1145 pr_debug("%s CQE OOO %d qpid 0x%0x genbit %d type %d status 0x%0x opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
1146 __func__, CQE_OOO(*hw_cqe), CQE_QPID(*hw_cqe),
1147 CQE_GENBIT(*hw_cqe), CQE_TYPE(*hw_cqe), CQE_STATUS(*hw_cqe),
1148 CQE_OPCODE(*hw_cqe), CQE_LEN(*hw_cqe), CQE_WRID_HI(*hw_cqe),
1149 CQE_WRID_LOW(*hw_cqe));
1150
1151 /*
1152 * skip cqe's not affiliated with a QP.
1153 */
1154 if (wq == NULL) {
1155 ret = -1;
1156 goto skip_cqe;
1157 }
1158
1159 /*
1160 * Gotta tweak READ completions:
1161 * 1) the cqe doesn't contain the sq_wptr from the wr.
1162 * 2) opcode not reflected from the wr.
1163 * 3) read_len not reflected from the wr.
1164 * 4) cq_type is RQ_TYPE not SQ_TYPE.
1165 */
1166 if (RQ_TYPE(*hw_cqe) && (CQE_OPCODE(*hw_cqe) == T3_READ_RESP)) {
1167
1168 /*
1169 * If this is an unsolicited read response, then the read
1170 * was generated by the kernel driver as part of peer-2-peer
1171 * connection setup. So ignore the completion.
1172 */
1173 if (!wq->oldest_read) {
1174 if (CQE_STATUS(*hw_cqe))
1175 wq->error = 1;
1176 ret = -1;
1177 goto skip_cqe;
1178 }
1179
1180 /*
1181 * Don't write to the HWCQ, so create a new read req CQE
1182 * in local memory.
1183 */
1184 create_read_req_cqe(wq, hw_cqe, &read_cqe);
1185 hw_cqe = &read_cqe;
1186 advance_oldest_read(wq);
1187 }
1188
1189 /*
1190 * T3A: Discard TERMINATE CQEs.
1191 */
1192 if (CQE_OPCODE(*hw_cqe) == T3_TERMINATE) {
1193 ret = -1;
1194 wq->error = 1;
1195 goto skip_cqe;
1196 }
1197
1198 if (CQE_STATUS(*hw_cqe) || wq->error) {
1199 *cqe_flushed = wq->error;
1200 wq->error = 1;
1201
1202 /*
1203 * T3A inserts errors into the CQE. We cannot return
1204 * these as work completions.
1205 */
1206 /* incoming write failures */
1207 if ((CQE_OPCODE(*hw_cqe) == T3_RDMA_WRITE)
1208 && RQ_TYPE(*hw_cqe)) {
1209 ret = -1;
1210 goto skip_cqe;
1211 }
1212 /* incoming read request failures */
1213 if ((CQE_OPCODE(*hw_cqe) == T3_READ_RESP) && SQ_TYPE(*hw_cqe)) {
1214 ret = -1;
1215 goto skip_cqe;
1216 }
1217
1218 /* incoming SEND with no receive posted failures */
1219 if (CQE_SEND_OPCODE(*hw_cqe) && RQ_TYPE(*hw_cqe) &&
1220 Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1221 ret = -1;
1222 goto skip_cqe;
1223 }
1224 BUG_ON((*cqe_flushed == 0) && !SW_CQE(*hw_cqe));
1225 goto proc_cqe;
1226 }
1227
1228 /*
1229 * RECV completion.
1230 */
1231 if (RQ_TYPE(*hw_cqe)) {
1232
1233 /*
1234 * HW only validates 4 bits of MSN. So we must validate that
1235 * the MSN in the SEND is the next expected MSN. If its not,
1236 * then we complete this with TPT_ERR_MSN and mark the wq in
1237 * error.
1238 */
1239
1240 if (Q_EMPTY(wq->rq_rptr, wq->rq_wptr)) {
1241 wq->error = 1;
1242 ret = -1;
1243 goto skip_cqe;
1244 }
1245
1246 if (unlikely((CQE_WRID_MSN(*hw_cqe) != (wq->rq_rptr + 1)))) {
1247 wq->error = 1;
1248 hw_cqe->header |= htonl(V_CQE_STATUS(TPT_ERR_MSN));
1249 goto proc_cqe;
1250 }
1251 goto proc_cqe;
1252 }
1253
1254 /*
1255 * If we get here its a send completion.
1256 *
1257 * Handle out of order completion. These get stuffed
1258 * in the SW SQ. Then the SW SQ is walked to move any
1259 * now in-order completions into the SW CQ. This handles
1260 * 2 cases:
1261 * 1) reaping unsignaled WRs when the first subsequent
1262 * signaled WR is completed.
1263 * 2) out of order read completions.
1264 */
1265 if (!SW_CQE(*hw_cqe) && (CQE_WRID_SQ_WPTR(*hw_cqe) != wq->sq_rptr)) {
1266 struct t3_swsq *sqp;
1267
1268 pr_debug("%s out of order completion going in swsq at idx %ld\n",
1269 __func__,
1270 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe),
1271 wq->sq_size_log2));
1272 sqp = wq->sq +
1273 Q_PTR2IDX(CQE_WRID_SQ_WPTR(*hw_cqe), wq->sq_size_log2);
1274 sqp->cqe = *hw_cqe;
1275 sqp->complete = 1;
1276 ret = -1;
1277 goto flush_wq;
1278 }
1279
1280 proc_cqe:
1281 *cqe = *hw_cqe;
1282
1283 /*
1284 * Reap the associated WR(s) that are freed up with this
1285 * completion.
1286 */
1287 if (SQ_TYPE(*hw_cqe)) {
1288 wq->sq_rptr = CQE_WRID_SQ_WPTR(*hw_cqe);
1289 pr_debug("%s completing sq idx %ld\n", __func__,
1290 Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2));
1291 *cookie = wq->sq[Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2)].wr_id;
1292 wq->sq_rptr++;
1293 } else {
1294 pr_debug("%s completing rq idx %ld\n", __func__,
1295 Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2));
1296 *cookie = wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].wr_id;
1297 if (wq->rq[Q_PTR2IDX(wq->rq_rptr, wq->rq_size_log2)].pbl_addr)
1298 cxio_hal_pblpool_free(wq->rdev,
1299 wq->rq[Q_PTR2IDX(wq->rq_rptr,
1300 wq->rq_size_log2)].pbl_addr, T3_STAG0_PBL_SIZE);
1301 BUG_ON(Q_EMPTY(wq->rq_rptr, wq->rq_wptr));
1302 wq->rq_rptr++;
1303 }
1304
1305 flush_wq:
1306 /*
1307 * Flush any completed cqes that are now in-order.
1308 */
1309 flush_completed_wrs(wq, cq);
1310
1311 skip_cqe:
1312 if (SW_CQE(*hw_cqe)) {
1313 pr_debug("%s cq %p cqid 0x%x skip sw cqe sw_rptr 0x%x\n",
1314 __func__, cq, cq->cqid, cq->sw_rptr);
1315 ++cq->sw_rptr;
1316 } else {
1317 pr_debug("%s cq %p cqid 0x%x skip hw cqe rptr 0x%x\n",
1318 __func__, cq, cq->cqid, cq->rptr);
1319 ++cq->rptr;
1320
1321 /*
1322 * T3A: compute credits.
1323 */
1324 if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1)))
1325 || ((cq->rptr - cq->wptr) >= 128)) {
1326 *credit = cq->rptr - cq->wptr;
1327 cq->wptr = cq->rptr;
1328 }
1329 }
1330 return ret;
1331 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git