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IB/mlx5: Add tunneling offloads support
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_ib.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 };
57
58 static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73 };
74
75 struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77 };
78
79 enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
82 };
83
84 struct mlx5_modify_raw_qp_param {
85 u16 operation;
86
87 u32 set_mask; /* raw_qp_set_mask_map */
88 u32 rate_limit;
89 u8 rq_q_ctr_id;
90 };
91
92 static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
96 static int is_qp0(enum ib_qp_type qp_type)
97 {
98 return qp_type == IB_QPT_SMI;
99 }
100
101 static int is_sqp(enum ib_qp_type qp_type)
102 {
103 return is_qp0(qp_type) || is_qp1(qp_type);
104 }
105
106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107 {
108 return mlx5_buf_offset(&qp->buf, offset);
109 }
110
111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112 {
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114 }
115
116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117 {
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119 }
120
121 /**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
141 {
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
147 struct ib_umem *umem = base->ubuffer.umem;
148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191 }
192
193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194 {
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238 }
239
240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242 {
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
262 } else {
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
271 wqe_size,
272 MLX5_CAP_GEN(dev->mdev,
273 max_wqe_sz_rq));
274 return -EINVAL;
275 }
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
279 }
280 }
281
282 return 0;
283 }
284
285 static int sq_overhead(struct ib_qp_init_attr *attr)
286 {
287 int size = 0;
288
289 switch (attr->qp_type) {
290 case IB_QPT_XRC_INI:
291 size += sizeof(struct mlx5_wqe_xrc_seg);
292 /* fall through */
293 case IB_QPT_RC:
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
299 break;
300
301 case IB_QPT_XRC_TGT:
302 return 0;
303
304 case IB_QPT_UC:
305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
309 break;
310
311 case IB_QPT_UD:
312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
315 /* fall through */
316 case IB_QPT_SMI:
317 case MLX5_IB_QPT_HW_GSI:
318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
319 sizeof(struct mlx5_wqe_datagram_seg);
320 break;
321
322 case MLX5_IB_QPT_REG_UMR:
323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return size;
333 }
334
335 static int calc_send_wqe(struct ib_qp_init_attr *attr)
336 {
337 int inl_size = 0;
338 int size;
339
340 size = sq_overhead(attr);
341 if (size < 0)
342 return size;
343
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
347 }
348
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
353 else
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
355 }
356
357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
358 {
359 int max_sge;
360
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
372 else
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
375
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
378 }
379
380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
382 {
383 int wqe_size;
384 int wq_size;
385
386 if (!attr->cap.max_send_wr)
387 return 0;
388
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
391 if (wqe_size < 0)
392 return wqe_size;
393
394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
397 return -EINVAL;
398 }
399
400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
402 attr->cap.max_inline_data = qp->max_inline_data;
403
404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
406
407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
414 return -ENOMEM;
415 }
416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
419 return -ENOMEM;
420
421 attr->cap.max_send_sge = qp->sq.max_gs;
422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
424
425 return wq_size;
426 }
427
428 static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
430 struct mlx5_ib_create_qp *ucmd,
431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
433 {
434 int desc_sz = 1 << qp->sq.wqe_shift;
435
436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
439 return -EINVAL;
440 }
441
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
445 return -EINVAL;
446 }
447
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
449
450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
452 qp->sq.wqe_cnt,
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
454 return -EINVAL;
455 }
456
457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
461 } else {
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
464 }
465
466 return 0;
467 }
468
469 static int qp_has_rq(struct ib_qp_init_attr *attr)
470 {
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
475 return 0;
476
477 return 1;
478 }
479
480 static int first_med_bfreg(void)
481 {
482 return 1;
483 }
484
485 enum {
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
489 * "odd/even" order
490 */
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
492 };
493
494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
495 {
496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
497 }
498
499 static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
501 {
502 int n;
503
504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
506
507 return n >= 0 ? n : 0;
508 }
509
510 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
512 {
513 int med;
514
515 med = num_med_bfreg(dev, bfregi);
516 return ++med;
517 }
518
519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
521 {
522 int i;
523
524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
526 bfregi->count[i]++;
527 return i;
528 }
529 }
530
531 return -ENOMEM;
532 }
533
534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
536 {
537 int minidx = first_med_bfreg();
538 int i;
539
540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
541 if (bfregi->count[i] < bfregi->count[minidx])
542 minidx = i;
543 if (!bfregi->count[minidx])
544 break;
545 }
546
547 bfregi->count[minidx]++;
548 return minidx;
549 }
550
551 static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
553 enum mlx5_ib_latency_class lat)
554 {
555 int bfregn = -EINVAL;
556
557 mutex_lock(&bfregi->lock);
558 switch (lat) {
559 case MLX5_IB_LATENCY_CLASS_LOW:
560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
561 bfregn = 0;
562 bfregi->count[bfregn]++;
563 break;
564
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
566 if (bfregi->ver < 2)
567 bfregn = -ENOMEM;
568 else
569 bfregn = alloc_med_class_bfreg(dev, bfregi);
570 break;
571
572 case MLX5_IB_LATENCY_CLASS_HIGH:
573 if (bfregi->ver < 2)
574 bfregn = -ENOMEM;
575 else
576 bfregn = alloc_high_class_bfreg(dev, bfregi);
577 break;
578 }
579 mutex_unlock(&bfregi->lock);
580
581 return bfregn;
582 }
583
584 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
585 {
586 mutex_lock(&bfregi->lock);
587 bfregi->count[bfregn]--;
588 mutex_unlock(&bfregi->lock);
589 }
590
591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
592 {
593 switch (state) {
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
601 default: return -1;
602 }
603 }
604
605 static int to_mlx5_st(enum ib_qp_type type)
606 {
607 switch (type) {
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
612 case IB_QPT_XRC_INI:
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
617 case IB_QPT_RAW_PACKET:
618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
619 case IB_QPT_MAX:
620 default: return -EINVAL;
621 }
622 }
623
624 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
627 struct mlx5_ib_cq *recv_cq);
628
629 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
630 struct mlx5_bfreg_info *bfregi, int bfregn)
631 {
632 int bfregs_per_sys_page;
633 int index_of_sys_page;
634 int offset;
635
636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
637 MLX5_NON_FP_BFREGS_PER_UAR;
638 index_of_sys_page = bfregn / bfregs_per_sys_page;
639
640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
641
642 return bfregi->sys_pages[index_of_sys_page] + offset;
643 }
644
645 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
646 struct ib_pd *pd,
647 unsigned long addr, size_t size,
648 struct ib_umem **umem,
649 int *npages, int *page_shift, int *ncont,
650 u32 *offset)
651 {
652 int err;
653
654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
655 if (IS_ERR(*umem)) {
656 mlx5_ib_dbg(dev, "umem_get failed\n");
657 return PTR_ERR(*umem);
658 }
659
660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
661
662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
663 if (err) {
664 mlx5_ib_warn(dev, "bad offset\n");
665 goto err_umem;
666 }
667
668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
669 addr, size, *npages, *page_shift, *ncont, *offset);
670
671 return 0;
672
673 err_umem:
674 ib_umem_release(*umem);
675 *umem = NULL;
676
677 return err;
678 }
679
680 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
681 struct mlx5_ib_rwq *rwq)
682 {
683 struct mlx5_ib_ucontext *context;
684
685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
686 atomic_dec(&dev->delay_drop.rqs_cnt);
687
688 context = to_mucontext(pd->uobject->context);
689 mlx5_ib_db_unmap_user(context, &rwq->db);
690 if (rwq->umem)
691 ib_umem_release(rwq->umem);
692 }
693
694 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
695 struct mlx5_ib_rwq *rwq,
696 struct mlx5_ib_create_wq *ucmd)
697 {
698 struct mlx5_ib_ucontext *context;
699 int page_shift = 0;
700 int npages;
701 u32 offset = 0;
702 int ncont = 0;
703 int err;
704
705 if (!ucmd->buf_addr)
706 return -EINVAL;
707
708 context = to_mucontext(pd->uobject->context);
709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
710 rwq->buf_size, 0, 0);
711 if (IS_ERR(rwq->umem)) {
712 mlx5_ib_dbg(dev, "umem_get failed\n");
713 err = PTR_ERR(rwq->umem);
714 return err;
715 }
716
717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
718 &ncont, NULL);
719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
720 &rwq->rq_page_offset);
721 if (err) {
722 mlx5_ib_warn(dev, "bad offset\n");
723 goto err_umem;
724 }
725
726 rwq->rq_num_pas = ncont;
727 rwq->page_shift = page_shift;
728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
730
731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
732 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
733 npages, page_shift, ncont, offset);
734
735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
736 if (err) {
737 mlx5_ib_dbg(dev, "map failed\n");
738 goto err_umem;
739 }
740
741 rwq->create_type = MLX5_WQ_USER;
742 return 0;
743
744 err_umem:
745 ib_umem_release(rwq->umem);
746 return err;
747 }
748
749 static int adjust_bfregn(struct mlx5_ib_dev *dev,
750 struct mlx5_bfreg_info *bfregi, int bfregn)
751 {
752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
754 }
755
756 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
757 struct mlx5_ib_qp *qp, struct ib_udata *udata,
758 struct ib_qp_init_attr *attr,
759 u32 **in,
760 struct mlx5_ib_create_qp_resp *resp, int *inlen,
761 struct mlx5_ib_qp_base *base)
762 {
763 struct mlx5_ib_ucontext *context;
764 struct mlx5_ib_create_qp ucmd;
765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
766 int page_shift = 0;
767 int uar_index;
768 int npages;
769 u32 offset = 0;
770 int bfregn;
771 int ncont = 0;
772 __be64 *pas;
773 void *qpc;
774 int err;
775
776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
777 if (err) {
778 mlx5_ib_dbg(dev, "copy failed\n");
779 return err;
780 }
781
782 context = to_mucontext(pd->uobject->context);
783 /*
784 * TBD: should come from the verbs when we have the API
785 */
786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
788 bfregn = MLX5_CROSS_CHANNEL_BFREG;
789 else {
790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
791 if (bfregn < 0) {
792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
793 mlx5_ib_dbg(dev, "reverting to medium latency\n");
794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
795 if (bfregn < 0) {
796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
797 mlx5_ib_dbg(dev, "reverting to high latency\n");
798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
799 if (bfregn < 0) {
800 mlx5_ib_warn(dev, "bfreg allocation failed\n");
801 return bfregn;
802 }
803 }
804 }
805 }
806
807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
809
810 qp->rq.offset = 0;
811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
813
814 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
815 if (err)
816 goto err_bfreg;
817
818 if (ucmd.buf_addr && ubuffer->buf_size) {
819 ubuffer->buf_addr = ucmd.buf_addr;
820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
821 ubuffer->buf_size,
822 &ubuffer->umem, &npages, &page_shift,
823 &ncont, &offset);
824 if (err)
825 goto err_bfreg;
826 } else {
827 ubuffer->umem = NULL;
828 }
829
830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
832 *in = kvzalloc(*inlen, GFP_KERNEL);
833 if (!*in) {
834 err = -ENOMEM;
835 goto err_umem;
836 }
837
838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
839 if (ubuffer->umem)
840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
841
842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
843
844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
845 MLX5_SET(qpc, qpc, page_offset, offset);
846
847 MLX5_SET(qpc, qpc, uar_page, uar_index);
848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
849 qp->bfregn = bfregn;
850
851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
852 if (err) {
853 mlx5_ib_dbg(dev, "map failed\n");
854 goto err_free;
855 }
856
857 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
858 if (err) {
859 mlx5_ib_dbg(dev, "copy failed\n");
860 goto err_unmap;
861 }
862 qp->create_type = MLX5_QP_USER;
863
864 return 0;
865
866 err_unmap:
867 mlx5_ib_db_unmap_user(context, &qp->db);
868
869 err_free:
870 kvfree(*in);
871
872 err_umem:
873 if (ubuffer->umem)
874 ib_umem_release(ubuffer->umem);
875
876 err_bfreg:
877 free_bfreg(dev, &context->bfregi, bfregn);
878 return err;
879 }
880
881 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
883 {
884 struct mlx5_ib_ucontext *context;
885
886 context = to_mucontext(pd->uobject->context);
887 mlx5_ib_db_unmap_user(context, &qp->db);
888 if (base->ubuffer.umem)
889 ib_umem_release(base->ubuffer.umem);
890 free_bfreg(dev, &context->bfregi, qp->bfregn);
891 }
892
893 static int create_kernel_qp(struct mlx5_ib_dev *dev,
894 struct ib_qp_init_attr *init_attr,
895 struct mlx5_ib_qp *qp,
896 u32 **in, int *inlen,
897 struct mlx5_ib_qp_base *base)
898 {
899 int uar_index;
900 void *qpc;
901 int err;
902
903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
905 IB_QP_CREATE_IPOIB_UD_LSO |
906 IB_QP_CREATE_NETIF_QP |
907 mlx5_ib_create_qp_sqpn_qp1()))
908 return -EINVAL;
909
910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
911 qp->bf.bfreg = &dev->fp_bfreg;
912 else
913 qp->bf.bfreg = &dev->bfreg;
914
915 /* We need to divide by two since each register is comprised of
916 * two buffers of identical size, namely odd and even
917 */
918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
919 uar_index = qp->bf.bfreg->index;
920
921 err = calc_sq_size(dev, init_attr, qp);
922 if (err < 0) {
923 mlx5_ib_dbg(dev, "err %d\n", err);
924 return err;
925 }
926
927 qp->rq.offset = 0;
928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
930
931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
932 if (err) {
933 mlx5_ib_dbg(dev, "err %d\n", err);
934 return err;
935 }
936
937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
940 *in = kvzalloc(*inlen, GFP_KERNEL);
941 if (!*in) {
942 err = -ENOMEM;
943 goto err_buf;
944 }
945
946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
947 MLX5_SET(qpc, qpc, uar_page, uar_index);
948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
949
950 /* Set "fast registration enabled" for all kernel QPs */
951 MLX5_SET(qpc, qpc, fre, 1);
952 MLX5_SET(qpc, qpc, rlky, 1);
953
954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
955 MLX5_SET(qpc, qpc, deth_sqpn, 1);
956 qp->flags |= MLX5_IB_QP_SQPN_QP1;
957 }
958
959 mlx5_fill_page_array(&qp->buf,
960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
961
962 err = mlx5_db_alloc(dev->mdev, &qp->db);
963 if (err) {
964 mlx5_ib_dbg(dev, "err %d\n", err);
965 goto err_free;
966 }
967
968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
969 sizeof(*qp->sq.wrid), GFP_KERNEL);
970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
971 sizeof(*qp->sq.wr_data), GFP_KERNEL);
972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
973 sizeof(*qp->rq.wrid), GFP_KERNEL);
974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
975 sizeof(*qp->sq.w_list), GFP_KERNEL);
976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
977 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
978
979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
980 !qp->sq.w_list || !qp->sq.wqe_head) {
981 err = -ENOMEM;
982 goto err_wrid;
983 }
984 qp->create_type = MLX5_QP_KERNEL;
985
986 return 0;
987
988 err_wrid:
989 kvfree(qp->sq.wqe_head);
990 kvfree(qp->sq.w_list);
991 kvfree(qp->sq.wrid);
992 kvfree(qp->sq.wr_data);
993 kvfree(qp->rq.wrid);
994 mlx5_db_free(dev->mdev, &qp->db);
995
996 err_free:
997 kvfree(*in);
998
999 err_buf:
1000 mlx5_buf_free(dev->mdev, &qp->buf);
1001 return err;
1002 }
1003
1004 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1005 {
1006 kvfree(qp->sq.wqe_head);
1007 kvfree(qp->sq.w_list);
1008 kvfree(qp->sq.wrid);
1009 kvfree(qp->sq.wr_data);
1010 kvfree(qp->rq.wrid);
1011 mlx5_db_free(dev->mdev, &qp->db);
1012 mlx5_buf_free(dev->mdev, &qp->buf);
1013 }
1014
1015 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1016 {
1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1018 (attr->qp_type == IB_QPT_XRC_INI))
1019 return MLX5_SRQ_RQ;
1020 else if (!qp->has_rq)
1021 return MLX5_ZERO_LEN_RQ;
1022 else
1023 return MLX5_NON_ZERO_RQ;
1024 }
1025
1026 static int is_connected(enum ib_qp_type qp_type)
1027 {
1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1029 return 1;
1030
1031 return 0;
1032 }
1033
1034 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1035 struct mlx5_ib_qp *qp,
1036 struct mlx5_ib_sq *sq, u32 tdn)
1037 {
1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1040
1041 MLX5_SET(tisc, tisc, transport_domain, tdn);
1042 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1044
1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1046 }
1047
1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1049 struct mlx5_ib_sq *sq)
1050 {
1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1052 }
1053
1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1055 struct mlx5_ib_sq *sq, void *qpin,
1056 struct ib_pd *pd)
1057 {
1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1059 __be64 *pas;
1060 void *in;
1061 void *sqc;
1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1063 void *wq;
1064 int inlen;
1065 int err;
1066 int page_shift = 0;
1067 int npages;
1068 int ncont = 0;
1069 u32 offset = 0;
1070
1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1072 &sq->ubuffer.umem, &npages, &page_shift,
1073 &ncont, &offset);
1074 if (err)
1075 return err;
1076
1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1078 in = kvzalloc(inlen, GFP_KERNEL);
1079 if (!in) {
1080 err = -ENOMEM;
1081 goto err_umem;
1082 }
1083
1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1086 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1087 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1091 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1092 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1093 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1094 MLX5_CAP_ETH(dev->mdev, swp))
1095 MLX5_SET(sqc, sqc, allow_swp, 1);
1096
1097 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1098 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1099 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1100 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1101 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1102 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1103 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1104 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1105 MLX5_SET(wq, wq, page_offset, offset);
1106
1107 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1108 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1109
1110 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1111
1112 kvfree(in);
1113
1114 if (err)
1115 goto err_umem;
1116
1117 return 0;
1118
1119 err_umem:
1120 ib_umem_release(sq->ubuffer.umem);
1121 sq->ubuffer.umem = NULL;
1122
1123 return err;
1124 }
1125
1126 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1127 struct mlx5_ib_sq *sq)
1128 {
1129 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1130 ib_umem_release(sq->ubuffer.umem);
1131 }
1132
1133 static int get_rq_pas_size(void *qpc)
1134 {
1135 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1136 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1137 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1138 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1139 u32 po_quanta = 1 << (log_page_size - 6);
1140 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1141 u32 page_size = 1 << log_page_size;
1142 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1143 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1144
1145 return rq_num_pas * sizeof(u64);
1146 }
1147
1148 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1149 struct mlx5_ib_rq *rq, void *qpin)
1150 {
1151 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1152 __be64 *pas;
1153 __be64 *qp_pas;
1154 void *in;
1155 void *rqc;
1156 void *wq;
1157 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1158 int inlen;
1159 int err;
1160 u32 rq_pas_size = get_rq_pas_size(qpc);
1161
1162 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1163 in = kvzalloc(inlen, GFP_KERNEL);
1164 if (!in)
1165 return -ENOMEM;
1166
1167 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1168 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1169 MLX5_SET(rqc, rqc, vsd, 1);
1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1175
1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1177 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1178
1179 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1181 MLX5_SET(wq, wq, end_padding_mode,
1182 MLX5_GET(qpc, qpc, end_padding_mode));
1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1189
1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1192 memcpy(pas, qp_pas, rq_pas_size);
1193
1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1195
1196 kvfree(in);
1197
1198 return err;
1199 }
1200
1201 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1202 struct mlx5_ib_rq *rq)
1203 {
1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1205 }
1206
1207 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1208 {
1209 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1210 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1211 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1212 }
1213
1214 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1215 struct mlx5_ib_rq *rq, u32 tdn,
1216 bool tunnel_offload_en)
1217 {
1218 u32 *in;
1219 void *tirc;
1220 int inlen;
1221 int err;
1222
1223 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1224 in = kvzalloc(inlen, GFP_KERNEL);
1225 if (!in)
1226 return -ENOMEM;
1227
1228 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1229 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1230 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1231 MLX5_SET(tirc, tirc, transport_domain, tdn);
1232 if (tunnel_offload_en)
1233 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1234
1235 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1236
1237 kvfree(in);
1238
1239 return err;
1240 }
1241
1242 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1243 struct mlx5_ib_rq *rq)
1244 {
1245 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1246 }
1247
1248 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1249 u32 *in,
1250 struct ib_pd *pd)
1251 {
1252 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1253 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1254 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1255 struct ib_uobject *uobj = pd->uobject;
1256 struct ib_ucontext *ucontext = uobj->context;
1257 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1258 int err;
1259 u32 tdn = mucontext->tdn;
1260
1261 if (qp->sq.wqe_cnt) {
1262 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1263 if (err)
1264 return err;
1265
1266 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1267 if (err)
1268 goto err_destroy_tis;
1269
1270 sq->base.container_mibqp = qp;
1271 sq->base.mqp.event = mlx5_ib_qp_event;
1272 }
1273
1274 if (qp->rq.wqe_cnt) {
1275 rq->base.container_mibqp = qp;
1276
1277 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1278 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1279 err = create_raw_packet_qp_rq(dev, rq, in);
1280 if (err)
1281 goto err_destroy_sq;
1282
1283
1284 err = create_raw_packet_qp_tir(dev, rq, tdn,
1285 qp->tunnel_offload_en);
1286 if (err)
1287 goto err_destroy_rq;
1288 }
1289
1290 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1291 rq->base.mqp.qpn;
1292
1293 return 0;
1294
1295 err_destroy_rq:
1296 destroy_raw_packet_qp_rq(dev, rq);
1297 err_destroy_sq:
1298 if (!qp->sq.wqe_cnt)
1299 return err;
1300 destroy_raw_packet_qp_sq(dev, sq);
1301 err_destroy_tis:
1302 destroy_raw_packet_qp_tis(dev, sq);
1303
1304 return err;
1305 }
1306
1307 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1308 struct mlx5_ib_qp *qp)
1309 {
1310 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1311 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1312 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1313
1314 if (qp->rq.wqe_cnt) {
1315 destroy_raw_packet_qp_tir(dev, rq);
1316 destroy_raw_packet_qp_rq(dev, rq);
1317 }
1318
1319 if (qp->sq.wqe_cnt) {
1320 destroy_raw_packet_qp_sq(dev, sq);
1321 destroy_raw_packet_qp_tis(dev, sq);
1322 }
1323 }
1324
1325 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1326 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1327 {
1328 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1329 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1330
1331 sq->sq = &qp->sq;
1332 rq->rq = &qp->rq;
1333 sq->doorbell = &qp->db;
1334 rq->doorbell = &qp->db;
1335 }
1336
1337 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1338 {
1339 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1340 }
1341
1342 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1343 struct ib_pd *pd,
1344 struct ib_qp_init_attr *init_attr,
1345 struct ib_udata *udata)
1346 {
1347 struct ib_uobject *uobj = pd->uobject;
1348 struct ib_ucontext *ucontext = uobj->context;
1349 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1350 struct mlx5_ib_create_qp_resp resp = {};
1351 int inlen;
1352 int err;
1353 u32 *in;
1354 void *tirc;
1355 void *hfso;
1356 u32 selected_fields = 0;
1357 size_t min_resp_len;
1358 u32 tdn = mucontext->tdn;
1359 struct mlx5_ib_create_qp_rss ucmd = {};
1360 size_t required_cmd_sz;
1361
1362 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1363 return -EOPNOTSUPP;
1364
1365 if (init_attr->create_flags || init_attr->send_cq)
1366 return -EINVAL;
1367
1368 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1369 if (udata->outlen < min_resp_len)
1370 return -EINVAL;
1371
1372 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1373 if (udata->inlen < required_cmd_sz) {
1374 mlx5_ib_dbg(dev, "invalid inlen\n");
1375 return -EINVAL;
1376 }
1377
1378 if (udata->inlen > sizeof(ucmd) &&
1379 !ib_is_udata_cleared(udata, sizeof(ucmd),
1380 udata->inlen - sizeof(ucmd))) {
1381 mlx5_ib_dbg(dev, "inlen is not supported\n");
1382 return -EOPNOTSUPP;
1383 }
1384
1385 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1386 mlx5_ib_dbg(dev, "copy failed\n");
1387 return -EFAULT;
1388 }
1389
1390 if (ucmd.comp_mask) {
1391 mlx5_ib_dbg(dev, "invalid comp mask\n");
1392 return -EOPNOTSUPP;
1393 }
1394
1395 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1396 mlx5_ib_dbg(dev, "invalid flags\n");
1397 return -EOPNOTSUPP;
1398 }
1399
1400 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1401 !tunnel_offload_supported(dev->mdev)) {
1402 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1403 return -EOPNOTSUPP;
1404 }
1405
1406 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1407 if (err) {
1408 mlx5_ib_dbg(dev, "copy failed\n");
1409 return -EINVAL;
1410 }
1411
1412 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1413 in = kvzalloc(inlen, GFP_KERNEL);
1414 if (!in)
1415 return -ENOMEM;
1416
1417 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1418 MLX5_SET(tirc, tirc, disp_type,
1419 MLX5_TIRC_DISP_TYPE_INDIRECT);
1420 MLX5_SET(tirc, tirc, indirect_table,
1421 init_attr->rwq_ind_tbl->ind_tbl_num);
1422 MLX5_SET(tirc, tirc, transport_domain, tdn);
1423
1424 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1425
1426 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1427 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1428
1429 switch (ucmd.rx_hash_function) {
1430 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1431 {
1432 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1433 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1434
1435 if (len != ucmd.rx_key_len) {
1436 err = -EINVAL;
1437 goto err;
1438 }
1439
1440 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1441 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1442 memcpy(rss_key, ucmd.rx_hash_key, len);
1443 break;
1444 }
1445 default:
1446 err = -EOPNOTSUPP;
1447 goto err;
1448 }
1449
1450 if (!ucmd.rx_hash_fields_mask) {
1451 /* special case when this TIR serves as steering entry without hashing */
1452 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1453 goto create_tir;
1454 err = -EINVAL;
1455 goto err;
1456 }
1457
1458 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1459 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1460 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1461 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1462 err = -EINVAL;
1463 goto err;
1464 }
1465
1466 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1467 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1468 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1469 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1470 MLX5_L3_PROT_TYPE_IPV4);
1471 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1472 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1473 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1474 MLX5_L3_PROT_TYPE_IPV6);
1475
1476 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1477 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1478 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1479 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1480 err = -EINVAL;
1481 goto err;
1482 }
1483
1484 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1485 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1486 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1487 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1488 MLX5_L4_PROT_TYPE_TCP);
1489 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1490 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1491 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1492 MLX5_L4_PROT_TYPE_UDP);
1493
1494 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1495 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1496 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1497
1498 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1499 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1500 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1501
1502 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1504 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1505
1506 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1507 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1508 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1509
1510 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1511
1512 create_tir:
1513 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1514
1515 if (err)
1516 goto err;
1517
1518 kvfree(in);
1519 /* qpn is reserved for that QP */
1520 qp->trans_qp.base.mqp.qpn = 0;
1521 qp->flags |= MLX5_IB_QP_RSS;
1522 return 0;
1523
1524 err:
1525 kvfree(in);
1526 return err;
1527 }
1528
1529 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1530 struct ib_qp_init_attr *init_attr,
1531 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1532 {
1533 struct mlx5_ib_resources *devr = &dev->devr;
1534 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1535 struct mlx5_core_dev *mdev = dev->mdev;
1536 struct mlx5_ib_create_qp_resp resp;
1537 struct mlx5_ib_cq *send_cq;
1538 struct mlx5_ib_cq *recv_cq;
1539 unsigned long flags;
1540 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1541 struct mlx5_ib_create_qp ucmd;
1542 struct mlx5_ib_qp_base *base;
1543 void *qpc;
1544 u32 *in;
1545 int err;
1546
1547 mutex_init(&qp->mutex);
1548 spin_lock_init(&qp->sq.lock);
1549 spin_lock_init(&qp->rq.lock);
1550
1551 if (init_attr->rwq_ind_tbl) {
1552 if (!udata)
1553 return -ENOSYS;
1554
1555 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1556 return err;
1557 }
1558
1559 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1560 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1561 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1562 return -EINVAL;
1563 } else {
1564 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1565 }
1566 }
1567
1568 if (init_attr->create_flags &
1569 (IB_QP_CREATE_CROSS_CHANNEL |
1570 IB_QP_CREATE_MANAGED_SEND |
1571 IB_QP_CREATE_MANAGED_RECV)) {
1572 if (!MLX5_CAP_GEN(mdev, cd)) {
1573 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1574 return -EINVAL;
1575 }
1576 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1577 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1578 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1579 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1580 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1581 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1582 }
1583
1584 if (init_attr->qp_type == IB_QPT_UD &&
1585 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1586 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1587 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1588 return -EOPNOTSUPP;
1589 }
1590
1591 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1592 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1593 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1594 return -EOPNOTSUPP;
1595 }
1596 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1597 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1598 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1599 return -EOPNOTSUPP;
1600 }
1601 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1602 }
1603
1604 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1605 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1606
1607 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1608 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1609 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1610 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1611 return -EOPNOTSUPP;
1612 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1613 }
1614
1615 if (pd && pd->uobject) {
1616 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1617 mlx5_ib_dbg(dev, "copy failed\n");
1618 return -EFAULT;
1619 }
1620
1621 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1622 &ucmd, udata->inlen, &uidx);
1623 if (err)
1624 return err;
1625
1626 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1627 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1628 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1629 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1630 !tunnel_offload_supported(mdev)) {
1631 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1632 return -EOPNOTSUPP;
1633 }
1634 qp->tunnel_offload_en = true;
1635 }
1636
1637 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1638 if (init_attr->qp_type != IB_QPT_UD ||
1639 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1640 MLX5_CAP_PORT_TYPE_IB) ||
1641 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1642 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1643 return -EOPNOTSUPP;
1644 }
1645
1646 qp->flags |= MLX5_IB_QP_UNDERLAY;
1647 qp->underlay_qpn = init_attr->source_qpn;
1648 }
1649 } else {
1650 qp->wq_sig = !!wq_signature;
1651 }
1652
1653 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1654 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1655 &qp->raw_packet_qp.rq.base :
1656 &qp->trans_qp.base;
1657
1658 qp->has_rq = qp_has_rq(init_attr);
1659 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1660 qp, (pd && pd->uobject) ? &ucmd : NULL);
1661 if (err) {
1662 mlx5_ib_dbg(dev, "err %d\n", err);
1663 return err;
1664 }
1665
1666 if (pd) {
1667 if (pd->uobject) {
1668 __u32 max_wqes =
1669 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1670 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1671 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1672 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1673 mlx5_ib_dbg(dev, "invalid rq params\n");
1674 return -EINVAL;
1675 }
1676 if (ucmd.sq_wqe_count > max_wqes) {
1677 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1678 ucmd.sq_wqe_count, max_wqes);
1679 return -EINVAL;
1680 }
1681 if (init_attr->create_flags &
1682 mlx5_ib_create_qp_sqpn_qp1()) {
1683 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1684 return -EINVAL;
1685 }
1686 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1687 &resp, &inlen, base);
1688 if (err)
1689 mlx5_ib_dbg(dev, "err %d\n", err);
1690 } else {
1691 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1692 base);
1693 if (err)
1694 mlx5_ib_dbg(dev, "err %d\n", err);
1695 }
1696
1697 if (err)
1698 return err;
1699 } else {
1700 in = kvzalloc(inlen, GFP_KERNEL);
1701 if (!in)
1702 return -ENOMEM;
1703
1704 qp->create_type = MLX5_QP_EMPTY;
1705 }
1706
1707 if (is_sqp(init_attr->qp_type))
1708 qp->port = init_attr->port_num;
1709
1710 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1711
1712 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1713 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1714
1715 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1716 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1717 else
1718 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1719
1720
1721 if (qp->wq_sig)
1722 MLX5_SET(qpc, qpc, wq_signature, 1);
1723
1724 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1725 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1726
1727 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1728 MLX5_SET(qpc, qpc, cd_master, 1);
1729 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1730 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1731 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1732 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1733
1734 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1735 int rcqe_sz;
1736 int scqe_sz;
1737
1738 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1739 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1740
1741 if (rcqe_sz == 128)
1742 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1743 else
1744 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1745
1746 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1747 if (scqe_sz == 128)
1748 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1749 else
1750 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1751 }
1752 }
1753
1754 if (qp->rq.wqe_cnt) {
1755 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1756 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1757 }
1758
1759 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1760
1761 if (qp->sq.wqe_cnt) {
1762 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1763 } else {
1764 MLX5_SET(qpc, qpc, no_sq, 1);
1765 if (init_attr->srq &&
1766 init_attr->srq->srq_type == IB_SRQT_TM)
1767 MLX5_SET(qpc, qpc, offload_type,
1768 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1769 }
1770
1771 /* Set default resources */
1772 switch (init_attr->qp_type) {
1773 case IB_QPT_XRC_TGT:
1774 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1775 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1776 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1777 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1778 break;
1779 case IB_QPT_XRC_INI:
1780 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1781 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1782 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1783 break;
1784 default:
1785 if (init_attr->srq) {
1786 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1787 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1788 } else {
1789 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1790 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1791 }
1792 }
1793
1794 if (init_attr->send_cq)
1795 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1796
1797 if (init_attr->recv_cq)
1798 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1799
1800 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1801
1802 /* 0xffffff means we ask to work with cqe version 0 */
1803 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1804 MLX5_SET(qpc, qpc, user_index, uidx);
1805
1806 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1807 if (init_attr->qp_type == IB_QPT_UD &&
1808 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1809 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1810 qp->flags |= MLX5_IB_QP_LSO;
1811 }
1812
1813 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1814 qp->flags & MLX5_IB_QP_UNDERLAY) {
1815 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1816 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1817 err = create_raw_packet_qp(dev, qp, in, pd);
1818 } else {
1819 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1820 }
1821
1822 if (err) {
1823 mlx5_ib_dbg(dev, "create qp failed\n");
1824 goto err_create;
1825 }
1826
1827 kvfree(in);
1828
1829 base->container_mibqp = qp;
1830 base->mqp.event = mlx5_ib_qp_event;
1831
1832 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1833 &send_cq, &recv_cq);
1834 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1835 mlx5_ib_lock_cqs(send_cq, recv_cq);
1836 /* Maintain device to QPs access, needed for further handling via reset
1837 * flow
1838 */
1839 list_add_tail(&qp->qps_list, &dev->qp_list);
1840 /* Maintain CQ to QPs access, needed for further handling via reset flow
1841 */
1842 if (send_cq)
1843 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1844 if (recv_cq)
1845 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1846 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1847 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1848
1849 return 0;
1850
1851 err_create:
1852 if (qp->create_type == MLX5_QP_USER)
1853 destroy_qp_user(dev, pd, qp, base);
1854 else if (qp->create_type == MLX5_QP_KERNEL)
1855 destroy_qp_kernel(dev, qp);
1856
1857 kvfree(in);
1858 return err;
1859 }
1860
1861 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1862 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1863 {
1864 if (send_cq) {
1865 if (recv_cq) {
1866 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1867 spin_lock(&send_cq->lock);
1868 spin_lock_nested(&recv_cq->lock,
1869 SINGLE_DEPTH_NESTING);
1870 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1871 spin_lock(&send_cq->lock);
1872 __acquire(&recv_cq->lock);
1873 } else {
1874 spin_lock(&recv_cq->lock);
1875 spin_lock_nested(&send_cq->lock,
1876 SINGLE_DEPTH_NESTING);
1877 }
1878 } else {
1879 spin_lock(&send_cq->lock);
1880 __acquire(&recv_cq->lock);
1881 }
1882 } else if (recv_cq) {
1883 spin_lock(&recv_cq->lock);
1884 __acquire(&send_cq->lock);
1885 } else {
1886 __acquire(&send_cq->lock);
1887 __acquire(&recv_cq->lock);
1888 }
1889 }
1890
1891 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1892 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1893 {
1894 if (send_cq) {
1895 if (recv_cq) {
1896 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1897 spin_unlock(&recv_cq->lock);
1898 spin_unlock(&send_cq->lock);
1899 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1900 __release(&recv_cq->lock);
1901 spin_unlock(&send_cq->lock);
1902 } else {
1903 spin_unlock(&send_cq->lock);
1904 spin_unlock(&recv_cq->lock);
1905 }
1906 } else {
1907 __release(&recv_cq->lock);
1908 spin_unlock(&send_cq->lock);
1909 }
1910 } else if (recv_cq) {
1911 __release(&send_cq->lock);
1912 spin_unlock(&recv_cq->lock);
1913 } else {
1914 __release(&recv_cq->lock);
1915 __release(&send_cq->lock);
1916 }
1917 }
1918
1919 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1920 {
1921 return to_mpd(qp->ibqp.pd);
1922 }
1923
1924 static void get_cqs(enum ib_qp_type qp_type,
1925 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1926 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1927 {
1928 switch (qp_type) {
1929 case IB_QPT_XRC_TGT:
1930 *send_cq = NULL;
1931 *recv_cq = NULL;
1932 break;
1933 case MLX5_IB_QPT_REG_UMR:
1934 case IB_QPT_XRC_INI:
1935 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1936 *recv_cq = NULL;
1937 break;
1938
1939 case IB_QPT_SMI:
1940 case MLX5_IB_QPT_HW_GSI:
1941 case IB_QPT_RC:
1942 case IB_QPT_UC:
1943 case IB_QPT_UD:
1944 case IB_QPT_RAW_IPV6:
1945 case IB_QPT_RAW_ETHERTYPE:
1946 case IB_QPT_RAW_PACKET:
1947 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1948 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1949 break;
1950
1951 case IB_QPT_MAX:
1952 default:
1953 *send_cq = NULL;
1954 *recv_cq = NULL;
1955 break;
1956 }
1957 }
1958
1959 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1960 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1961 u8 lag_tx_affinity);
1962
1963 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1964 {
1965 struct mlx5_ib_cq *send_cq, *recv_cq;
1966 struct mlx5_ib_qp_base *base;
1967 unsigned long flags;
1968 int err;
1969
1970 if (qp->ibqp.rwq_ind_tbl) {
1971 destroy_rss_raw_qp_tir(dev, qp);
1972 return;
1973 }
1974
1975 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
1976 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1977 &qp->raw_packet_qp.rq.base :
1978 &qp->trans_qp.base;
1979
1980 if (qp->state != IB_QPS_RESET) {
1981 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
1982 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
1983 err = mlx5_core_qp_modify(dev->mdev,
1984 MLX5_CMD_OP_2RST_QP, 0,
1985 NULL, &base->mqp);
1986 } else {
1987 struct mlx5_modify_raw_qp_param raw_qp_param = {
1988 .operation = MLX5_CMD_OP_2RST_QP
1989 };
1990
1991 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1992 }
1993 if (err)
1994 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1995 base->mqp.qpn);
1996 }
1997
1998 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1999 &send_cq, &recv_cq);
2000
2001 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2002 mlx5_ib_lock_cqs(send_cq, recv_cq);
2003 /* del from lists under both locks above to protect reset flow paths */
2004 list_del(&qp->qps_list);
2005 if (send_cq)
2006 list_del(&qp->cq_send_list);
2007
2008 if (recv_cq)
2009 list_del(&qp->cq_recv_list);
2010
2011 if (qp->create_type == MLX5_QP_KERNEL) {
2012 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2013 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2014 if (send_cq != recv_cq)
2015 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2016 NULL);
2017 }
2018 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2019 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2020
2021 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2022 qp->flags & MLX5_IB_QP_UNDERLAY) {
2023 destroy_raw_packet_qp(dev, qp);
2024 } else {
2025 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2026 if (err)
2027 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2028 base->mqp.qpn);
2029 }
2030
2031 if (qp->create_type == MLX5_QP_KERNEL)
2032 destroy_qp_kernel(dev, qp);
2033 else if (qp->create_type == MLX5_QP_USER)
2034 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2035 }
2036
2037 static const char *ib_qp_type_str(enum ib_qp_type type)
2038 {
2039 switch (type) {
2040 case IB_QPT_SMI:
2041 return "IB_QPT_SMI";
2042 case IB_QPT_GSI:
2043 return "IB_QPT_GSI";
2044 case IB_QPT_RC:
2045 return "IB_QPT_RC";
2046 case IB_QPT_UC:
2047 return "IB_QPT_UC";
2048 case IB_QPT_UD:
2049 return "IB_QPT_UD";
2050 case IB_QPT_RAW_IPV6:
2051 return "IB_QPT_RAW_IPV6";
2052 case IB_QPT_RAW_ETHERTYPE:
2053 return "IB_QPT_RAW_ETHERTYPE";
2054 case IB_QPT_XRC_INI:
2055 return "IB_QPT_XRC_INI";
2056 case IB_QPT_XRC_TGT:
2057 return "IB_QPT_XRC_TGT";
2058 case IB_QPT_RAW_PACKET:
2059 return "IB_QPT_RAW_PACKET";
2060 case MLX5_IB_QPT_REG_UMR:
2061 return "MLX5_IB_QPT_REG_UMR";
2062 case IB_QPT_MAX:
2063 default:
2064 return "Invalid QP type";
2065 }
2066 }
2067
2068 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2069 struct ib_qp_init_attr *init_attr,
2070 struct ib_udata *udata)
2071 {
2072 struct mlx5_ib_dev *dev;
2073 struct mlx5_ib_qp *qp;
2074 u16 xrcdn = 0;
2075 int err;
2076
2077 if (pd) {
2078 dev = to_mdev(pd->device);
2079
2080 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2081 if (!pd->uobject) {
2082 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2083 return ERR_PTR(-EINVAL);
2084 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2085 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2086 return ERR_PTR(-EINVAL);
2087 }
2088 }
2089 } else {
2090 /* being cautious here */
2091 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2092 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2093 pr_warn("%s: no PD for transport %s\n", __func__,
2094 ib_qp_type_str(init_attr->qp_type));
2095 return ERR_PTR(-EINVAL);
2096 }
2097 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2098 }
2099
2100 switch (init_attr->qp_type) {
2101 case IB_QPT_XRC_TGT:
2102 case IB_QPT_XRC_INI:
2103 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2104 mlx5_ib_dbg(dev, "XRC not supported\n");
2105 return ERR_PTR(-ENOSYS);
2106 }
2107 init_attr->recv_cq = NULL;
2108 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2109 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2110 init_attr->send_cq = NULL;
2111 }
2112
2113 /* fall through */
2114 case IB_QPT_RAW_PACKET:
2115 case IB_QPT_RC:
2116 case IB_QPT_UC:
2117 case IB_QPT_UD:
2118 case IB_QPT_SMI:
2119 case MLX5_IB_QPT_HW_GSI:
2120 case MLX5_IB_QPT_REG_UMR:
2121 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2122 if (!qp)
2123 return ERR_PTR(-ENOMEM);
2124
2125 err = create_qp_common(dev, pd, init_attr, udata, qp);
2126 if (err) {
2127 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2128 kfree(qp);
2129 return ERR_PTR(err);
2130 }
2131
2132 if (is_qp0(init_attr->qp_type))
2133 qp->ibqp.qp_num = 0;
2134 else if (is_qp1(init_attr->qp_type))
2135 qp->ibqp.qp_num = 1;
2136 else
2137 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2138
2139 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2140 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2141 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2142 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2143
2144 qp->trans_qp.xrcdn = xrcdn;
2145
2146 break;
2147
2148 case IB_QPT_GSI:
2149 return mlx5_ib_gsi_create_qp(pd, init_attr);
2150
2151 case IB_QPT_RAW_IPV6:
2152 case IB_QPT_RAW_ETHERTYPE:
2153 case IB_QPT_MAX:
2154 default:
2155 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2156 init_attr->qp_type);
2157 /* Don't support raw QPs */
2158 return ERR_PTR(-EINVAL);
2159 }
2160
2161 return &qp->ibqp;
2162 }
2163
2164 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2165 {
2166 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2167 struct mlx5_ib_qp *mqp = to_mqp(qp);
2168
2169 if (unlikely(qp->qp_type == IB_QPT_GSI))
2170 return mlx5_ib_gsi_destroy_qp(qp);
2171
2172 destroy_qp_common(dev, mqp);
2173
2174 kfree(mqp);
2175
2176 return 0;
2177 }
2178
2179 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2180 int attr_mask)
2181 {
2182 u32 hw_access_flags = 0;
2183 u8 dest_rd_atomic;
2184 u32 access_flags;
2185
2186 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2187 dest_rd_atomic = attr->max_dest_rd_atomic;
2188 else
2189 dest_rd_atomic = qp->trans_qp.resp_depth;
2190
2191 if (attr_mask & IB_QP_ACCESS_FLAGS)
2192 access_flags = attr->qp_access_flags;
2193 else
2194 access_flags = qp->trans_qp.atomic_rd_en;
2195
2196 if (!dest_rd_atomic)
2197 access_flags &= IB_ACCESS_REMOTE_WRITE;
2198
2199 if (access_flags & IB_ACCESS_REMOTE_READ)
2200 hw_access_flags |= MLX5_QP_BIT_RRE;
2201 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2202 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2203 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2204 hw_access_flags |= MLX5_QP_BIT_RWE;
2205
2206 return cpu_to_be32(hw_access_flags);
2207 }
2208
2209 enum {
2210 MLX5_PATH_FLAG_FL = 1 << 0,
2211 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2212 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2213 };
2214
2215 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2216 {
2217 if (rate == IB_RATE_PORT_CURRENT) {
2218 return 0;
2219 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2220 return -EINVAL;
2221 } else {
2222 while (rate != IB_RATE_2_5_GBPS &&
2223 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2224 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2225 --rate;
2226 }
2227
2228 return rate + MLX5_STAT_RATE_OFFSET;
2229 }
2230
2231 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2232 struct mlx5_ib_sq *sq, u8 sl)
2233 {
2234 void *in;
2235 void *tisc;
2236 int inlen;
2237 int err;
2238
2239 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2240 in = kvzalloc(inlen, GFP_KERNEL);
2241 if (!in)
2242 return -ENOMEM;
2243
2244 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2245
2246 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2247 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2248
2249 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2250
2251 kvfree(in);
2252
2253 return err;
2254 }
2255
2256 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2257 struct mlx5_ib_sq *sq, u8 tx_affinity)
2258 {
2259 void *in;
2260 void *tisc;
2261 int inlen;
2262 int err;
2263
2264 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2265 in = kvzalloc(inlen, GFP_KERNEL);
2266 if (!in)
2267 return -ENOMEM;
2268
2269 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2270
2271 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2272 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2273
2274 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2275
2276 kvfree(in);
2277
2278 return err;
2279 }
2280
2281 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2282 const struct rdma_ah_attr *ah,
2283 struct mlx5_qp_path *path, u8 port, int attr_mask,
2284 u32 path_flags, const struct ib_qp_attr *attr,
2285 bool alt)
2286 {
2287 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2288 int err;
2289 enum ib_gid_type gid_type;
2290 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2291 u8 sl = rdma_ah_get_sl(ah);
2292
2293 if (attr_mask & IB_QP_PKEY_INDEX)
2294 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2295 attr->pkey_index);
2296
2297 if (ah_flags & IB_AH_GRH) {
2298 if (grh->sgid_index >=
2299 dev->mdev->port_caps[port - 1].gid_table_len) {
2300 pr_err("sgid_index (%u) too large. max is %d\n",
2301 grh->sgid_index,
2302 dev->mdev->port_caps[port - 1].gid_table_len);
2303 return -EINVAL;
2304 }
2305 }
2306
2307 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2308 if (!(ah_flags & IB_AH_GRH))
2309 return -EINVAL;
2310 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2311 &gid_type);
2312 if (err)
2313 return err;
2314 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2315 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2316 grh->sgid_index);
2317 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2318 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2319 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2320 } else {
2321 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2322 path->fl_free_ar |=
2323 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2324 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2325 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2326 if (ah_flags & IB_AH_GRH)
2327 path->grh_mlid |= 1 << 7;
2328 path->dci_cfi_prio_sl = sl & 0xf;
2329 }
2330
2331 if (ah_flags & IB_AH_GRH) {
2332 path->mgid_index = grh->sgid_index;
2333 path->hop_limit = grh->hop_limit;
2334 path->tclass_flowlabel =
2335 cpu_to_be32((grh->traffic_class << 20) |
2336 (grh->flow_label));
2337 memcpy(path->rgid, grh->dgid.raw, 16);
2338 }
2339
2340 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2341 if (err < 0)
2342 return err;
2343 path->static_rate = err;
2344 path->port = port;
2345
2346 if (attr_mask & IB_QP_TIMEOUT)
2347 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2348
2349 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2350 return modify_raw_packet_eth_prio(dev->mdev,
2351 &qp->raw_packet_qp.sq,
2352 sl & 0xf);
2353
2354 return 0;
2355 }
2356
2357 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2358 [MLX5_QP_STATE_INIT] = {
2359 [MLX5_QP_STATE_INIT] = {
2360 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2361 MLX5_QP_OPTPAR_RAE |
2362 MLX5_QP_OPTPAR_RWE |
2363 MLX5_QP_OPTPAR_PKEY_INDEX |
2364 MLX5_QP_OPTPAR_PRI_PORT,
2365 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2366 MLX5_QP_OPTPAR_PKEY_INDEX |
2367 MLX5_QP_OPTPAR_PRI_PORT,
2368 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2369 MLX5_QP_OPTPAR_Q_KEY |
2370 MLX5_QP_OPTPAR_PRI_PORT,
2371 },
2372 [MLX5_QP_STATE_RTR] = {
2373 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2374 MLX5_QP_OPTPAR_RRE |
2375 MLX5_QP_OPTPAR_RAE |
2376 MLX5_QP_OPTPAR_RWE |
2377 MLX5_QP_OPTPAR_PKEY_INDEX,
2378 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2379 MLX5_QP_OPTPAR_RWE |
2380 MLX5_QP_OPTPAR_PKEY_INDEX,
2381 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2382 MLX5_QP_OPTPAR_Q_KEY,
2383 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2384 MLX5_QP_OPTPAR_Q_KEY,
2385 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2386 MLX5_QP_OPTPAR_RRE |
2387 MLX5_QP_OPTPAR_RAE |
2388 MLX5_QP_OPTPAR_RWE |
2389 MLX5_QP_OPTPAR_PKEY_INDEX,
2390 },
2391 },
2392 [MLX5_QP_STATE_RTR] = {
2393 [MLX5_QP_STATE_RTS] = {
2394 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2395 MLX5_QP_OPTPAR_RRE |
2396 MLX5_QP_OPTPAR_RAE |
2397 MLX5_QP_OPTPAR_RWE |
2398 MLX5_QP_OPTPAR_PM_STATE |
2399 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2400 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2401 MLX5_QP_OPTPAR_RWE |
2402 MLX5_QP_OPTPAR_PM_STATE,
2403 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2404 },
2405 },
2406 [MLX5_QP_STATE_RTS] = {
2407 [MLX5_QP_STATE_RTS] = {
2408 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2409 MLX5_QP_OPTPAR_RAE |
2410 MLX5_QP_OPTPAR_RWE |
2411 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2412 MLX5_QP_OPTPAR_PM_STATE |
2413 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2414 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2415 MLX5_QP_OPTPAR_PM_STATE |
2416 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2417 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2418 MLX5_QP_OPTPAR_SRQN |
2419 MLX5_QP_OPTPAR_CQN_RCV,
2420 },
2421 },
2422 [MLX5_QP_STATE_SQER] = {
2423 [MLX5_QP_STATE_RTS] = {
2424 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2425 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2426 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2427 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2428 MLX5_QP_OPTPAR_RWE |
2429 MLX5_QP_OPTPAR_RAE |
2430 MLX5_QP_OPTPAR_RRE,
2431 },
2432 },
2433 };
2434
2435 static int ib_nr_to_mlx5_nr(int ib_mask)
2436 {
2437 switch (ib_mask) {
2438 case IB_QP_STATE:
2439 return 0;
2440 case IB_QP_CUR_STATE:
2441 return 0;
2442 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2443 return 0;
2444 case IB_QP_ACCESS_FLAGS:
2445 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2446 MLX5_QP_OPTPAR_RAE;
2447 case IB_QP_PKEY_INDEX:
2448 return MLX5_QP_OPTPAR_PKEY_INDEX;
2449 case IB_QP_PORT:
2450 return MLX5_QP_OPTPAR_PRI_PORT;
2451 case IB_QP_QKEY:
2452 return MLX5_QP_OPTPAR_Q_KEY;
2453 case IB_QP_AV:
2454 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2455 MLX5_QP_OPTPAR_PRI_PORT;
2456 case IB_QP_PATH_MTU:
2457 return 0;
2458 case IB_QP_TIMEOUT:
2459 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2460 case IB_QP_RETRY_CNT:
2461 return MLX5_QP_OPTPAR_RETRY_COUNT;
2462 case IB_QP_RNR_RETRY:
2463 return MLX5_QP_OPTPAR_RNR_RETRY;
2464 case IB_QP_RQ_PSN:
2465 return 0;
2466 case IB_QP_MAX_QP_RD_ATOMIC:
2467 return MLX5_QP_OPTPAR_SRA_MAX;
2468 case IB_QP_ALT_PATH:
2469 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2470 case IB_QP_MIN_RNR_TIMER:
2471 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2472 case IB_QP_SQ_PSN:
2473 return 0;
2474 case IB_QP_MAX_DEST_RD_ATOMIC:
2475 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2476 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2477 case IB_QP_PATH_MIG_STATE:
2478 return MLX5_QP_OPTPAR_PM_STATE;
2479 case IB_QP_CAP:
2480 return 0;
2481 case IB_QP_DEST_QPN:
2482 return 0;
2483 }
2484 return 0;
2485 }
2486
2487 static int ib_mask_to_mlx5_opt(int ib_mask)
2488 {
2489 int result = 0;
2490 int i;
2491
2492 for (i = 0; i < 8 * sizeof(int); i++) {
2493 if ((1 << i) & ib_mask)
2494 result |= ib_nr_to_mlx5_nr(1 << i);
2495 }
2496
2497 return result;
2498 }
2499
2500 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2501 struct mlx5_ib_rq *rq, int new_state,
2502 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2503 {
2504 void *in;
2505 void *rqc;
2506 int inlen;
2507 int err;
2508
2509 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2510 in = kvzalloc(inlen, GFP_KERNEL);
2511 if (!in)
2512 return -ENOMEM;
2513
2514 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2515
2516 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2517 MLX5_SET(rqc, rqc, state, new_state);
2518
2519 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2520 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2521 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2522 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2523 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2524 } else
2525 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2526 dev->ib_dev.name);
2527 }
2528
2529 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2530 if (err)
2531 goto out;
2532
2533 rq->state = new_state;
2534
2535 out:
2536 kvfree(in);
2537 return err;
2538 }
2539
2540 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2541 struct mlx5_ib_sq *sq,
2542 int new_state,
2543 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2544 {
2545 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2546 u32 old_rate = ibqp->rate_limit;
2547 u32 new_rate = old_rate;
2548 u16 rl_index = 0;
2549 void *in;
2550 void *sqc;
2551 int inlen;
2552 int err;
2553
2554 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2555 in = kvzalloc(inlen, GFP_KERNEL);
2556 if (!in)
2557 return -ENOMEM;
2558
2559 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2560
2561 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2562 MLX5_SET(sqc, sqc, state, new_state);
2563
2564 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2565 if (new_state != MLX5_SQC_STATE_RDY)
2566 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2567 __func__);
2568 else
2569 new_rate = raw_qp_param->rate_limit;
2570 }
2571
2572 if (old_rate != new_rate) {
2573 if (new_rate) {
2574 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2575 if (err) {
2576 pr_err("Failed configuring rate %u: %d\n",
2577 new_rate, err);
2578 goto out;
2579 }
2580 }
2581
2582 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2583 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2584 }
2585
2586 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2587 if (err) {
2588 /* Remove new rate from table if failed */
2589 if (new_rate &&
2590 old_rate != new_rate)
2591 mlx5_rl_remove_rate(dev, new_rate);
2592 goto out;
2593 }
2594
2595 /* Only remove the old rate after new rate was set */
2596 if ((old_rate &&
2597 (old_rate != new_rate)) ||
2598 (new_state != MLX5_SQC_STATE_RDY))
2599 mlx5_rl_remove_rate(dev, old_rate);
2600
2601 ibqp->rate_limit = new_rate;
2602 sq->state = new_state;
2603
2604 out:
2605 kvfree(in);
2606 return err;
2607 }
2608
2609 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2610 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2611 u8 tx_affinity)
2612 {
2613 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2614 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2615 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2616 int modify_rq = !!qp->rq.wqe_cnt;
2617 int modify_sq = !!qp->sq.wqe_cnt;
2618 int rq_state;
2619 int sq_state;
2620 int err;
2621
2622 switch (raw_qp_param->operation) {
2623 case MLX5_CMD_OP_RST2INIT_QP:
2624 rq_state = MLX5_RQC_STATE_RDY;
2625 sq_state = MLX5_SQC_STATE_RDY;
2626 break;
2627 case MLX5_CMD_OP_2ERR_QP:
2628 rq_state = MLX5_RQC_STATE_ERR;
2629 sq_state = MLX5_SQC_STATE_ERR;
2630 break;
2631 case MLX5_CMD_OP_2RST_QP:
2632 rq_state = MLX5_RQC_STATE_RST;
2633 sq_state = MLX5_SQC_STATE_RST;
2634 break;
2635 case MLX5_CMD_OP_RTR2RTS_QP:
2636 case MLX5_CMD_OP_RTS2RTS_QP:
2637 if (raw_qp_param->set_mask ==
2638 MLX5_RAW_QP_RATE_LIMIT) {
2639 modify_rq = 0;
2640 sq_state = sq->state;
2641 } else {
2642 return raw_qp_param->set_mask ? -EINVAL : 0;
2643 }
2644 break;
2645 case MLX5_CMD_OP_INIT2INIT_QP:
2646 case MLX5_CMD_OP_INIT2RTR_QP:
2647 if (raw_qp_param->set_mask)
2648 return -EINVAL;
2649 else
2650 return 0;
2651 default:
2652 WARN_ON(1);
2653 return -EINVAL;
2654 }
2655
2656 if (modify_rq) {
2657 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2658 if (err)
2659 return err;
2660 }
2661
2662 if (modify_sq) {
2663 if (tx_affinity) {
2664 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2665 tx_affinity);
2666 if (err)
2667 return err;
2668 }
2669
2670 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2671 }
2672
2673 return 0;
2674 }
2675
2676 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2677 const struct ib_qp_attr *attr, int attr_mask,
2678 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2679 {
2680 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2681 [MLX5_QP_STATE_RST] = {
2682 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2683 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2684 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2685 },
2686 [MLX5_QP_STATE_INIT] = {
2687 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2688 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2689 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2690 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2691 },
2692 [MLX5_QP_STATE_RTR] = {
2693 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2694 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2695 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2696 },
2697 [MLX5_QP_STATE_RTS] = {
2698 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2699 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2700 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2701 },
2702 [MLX5_QP_STATE_SQD] = {
2703 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2704 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2705 },
2706 [MLX5_QP_STATE_SQER] = {
2707 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2708 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2709 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2710 },
2711 [MLX5_QP_STATE_ERR] = {
2712 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2713 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2714 }
2715 };
2716
2717 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2718 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2719 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2720 struct mlx5_ib_cq *send_cq, *recv_cq;
2721 struct mlx5_qp_context *context;
2722 struct mlx5_ib_pd *pd;
2723 struct mlx5_ib_port *mibport = NULL;
2724 enum mlx5_qp_state mlx5_cur, mlx5_new;
2725 enum mlx5_qp_optpar optpar;
2726 int mlx5_st;
2727 int err;
2728 u16 op;
2729 u8 tx_affinity = 0;
2730
2731 context = kzalloc(sizeof(*context), GFP_KERNEL);
2732 if (!context)
2733 return -ENOMEM;
2734
2735 err = to_mlx5_st(ibqp->qp_type);
2736 if (err < 0) {
2737 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2738 goto out;
2739 }
2740
2741 context->flags = cpu_to_be32(err << 16);
2742
2743 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2744 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2745 } else {
2746 switch (attr->path_mig_state) {
2747 case IB_MIG_MIGRATED:
2748 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2749 break;
2750 case IB_MIG_REARM:
2751 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2752 break;
2753 case IB_MIG_ARMED:
2754 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2755 break;
2756 }
2757 }
2758
2759 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2760 if ((ibqp->qp_type == IB_QPT_RC) ||
2761 (ibqp->qp_type == IB_QPT_UD &&
2762 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2763 (ibqp->qp_type == IB_QPT_UC) ||
2764 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2765 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2766 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2767 if (mlx5_lag_is_active(dev->mdev)) {
2768 tx_affinity = (unsigned int)atomic_add_return(1,
2769 &dev->roce.next_port) %
2770 MLX5_MAX_PORTS + 1;
2771 context->flags |= cpu_to_be32(tx_affinity << 24);
2772 }
2773 }
2774 }
2775
2776 if (is_sqp(ibqp->qp_type)) {
2777 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2778 } else if ((ibqp->qp_type == IB_QPT_UD &&
2779 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
2780 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2781 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2782 } else if (attr_mask & IB_QP_PATH_MTU) {
2783 if (attr->path_mtu < IB_MTU_256 ||
2784 attr->path_mtu > IB_MTU_4096) {
2785 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2786 err = -EINVAL;
2787 goto out;
2788 }
2789 context->mtu_msgmax = (attr->path_mtu << 5) |
2790 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2791 }
2792
2793 if (attr_mask & IB_QP_DEST_QPN)
2794 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2795
2796 if (attr_mask & IB_QP_PKEY_INDEX)
2797 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2798
2799 /* todo implement counter_index functionality */
2800
2801 if (is_sqp(ibqp->qp_type))
2802 context->pri_path.port = qp->port;
2803
2804 if (attr_mask & IB_QP_PORT)
2805 context->pri_path.port = attr->port_num;
2806
2807 if (attr_mask & IB_QP_AV) {
2808 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2809 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2810 attr_mask, 0, attr, false);
2811 if (err)
2812 goto out;
2813 }
2814
2815 if (attr_mask & IB_QP_TIMEOUT)
2816 context->pri_path.ackto_lt |= attr->timeout << 3;
2817
2818 if (attr_mask & IB_QP_ALT_PATH) {
2819 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2820 &context->alt_path,
2821 attr->alt_port_num,
2822 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2823 0, attr, true);
2824 if (err)
2825 goto out;
2826 }
2827
2828 pd = get_pd(qp);
2829 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2830 &send_cq, &recv_cq);
2831
2832 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2833 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2834 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2835 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2836
2837 if (attr_mask & IB_QP_RNR_RETRY)
2838 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2839
2840 if (attr_mask & IB_QP_RETRY_CNT)
2841 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2842
2843 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2844 if (attr->max_rd_atomic)
2845 context->params1 |=
2846 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2847 }
2848
2849 if (attr_mask & IB_QP_SQ_PSN)
2850 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2851
2852 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2853 if (attr->max_dest_rd_atomic)
2854 context->params2 |=
2855 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2856 }
2857
2858 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2859 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2860
2861 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2862 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2863
2864 if (attr_mask & IB_QP_RQ_PSN)
2865 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2866
2867 if (attr_mask & IB_QP_QKEY)
2868 context->qkey = cpu_to_be32(attr->qkey);
2869
2870 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2871 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2872
2873 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2874 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2875 qp->port) - 1;
2876
2877 /* Underlay port should be used - index 0 function per port */
2878 if (qp->flags & MLX5_IB_QP_UNDERLAY)
2879 port_num = 0;
2880
2881 mibport = &dev->port[port_num];
2882 context->qp_counter_set_usr_page |=
2883 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2884 }
2885
2886 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2887 context->sq_crq_size |= cpu_to_be16(1 << 4);
2888
2889 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2890 context->deth_sqpn = cpu_to_be32(1);
2891
2892 mlx5_cur = to_mlx5_state(cur_state);
2893 mlx5_new = to_mlx5_state(new_state);
2894 mlx5_st = to_mlx5_st(ibqp->qp_type);
2895 if (mlx5_st < 0)
2896 goto out;
2897
2898 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2899 !optab[mlx5_cur][mlx5_new])
2900 goto out;
2901
2902 op = optab[mlx5_cur][mlx5_new];
2903 optpar = ib_mask_to_mlx5_opt(attr_mask);
2904 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2905
2906 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2907 qp->flags & MLX5_IB_QP_UNDERLAY) {
2908 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2909
2910 raw_qp_param.operation = op;
2911 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2912 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2913 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2914 }
2915
2916 if (attr_mask & IB_QP_RATE_LIMIT) {
2917 raw_qp_param.rate_limit = attr->rate_limit;
2918 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2919 }
2920
2921 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2922 } else {
2923 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2924 &base->mqp);
2925 }
2926
2927 if (err)
2928 goto out;
2929
2930 qp->state = new_state;
2931
2932 if (attr_mask & IB_QP_ACCESS_FLAGS)
2933 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2934 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2935 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2936 if (attr_mask & IB_QP_PORT)
2937 qp->port = attr->port_num;
2938 if (attr_mask & IB_QP_ALT_PATH)
2939 qp->trans_qp.alt_port = attr->alt_port_num;
2940
2941 /*
2942 * If we moved a kernel QP to RESET, clean up all old CQ
2943 * entries and reinitialize the QP.
2944 */
2945 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2946 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2947 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2948 if (send_cq != recv_cq)
2949 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2950
2951 qp->rq.head = 0;
2952 qp->rq.tail = 0;
2953 qp->sq.head = 0;
2954 qp->sq.tail = 0;
2955 qp->sq.cur_post = 0;
2956 qp->sq.last_poll = 0;
2957 qp->db.db[MLX5_RCV_DBR] = 0;
2958 qp->db.db[MLX5_SND_DBR] = 0;
2959 }
2960
2961 out:
2962 kfree(context);
2963 return err;
2964 }
2965
2966 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2967 int attr_mask, struct ib_udata *udata)
2968 {
2969 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2970 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2971 enum ib_qp_type qp_type;
2972 enum ib_qp_state cur_state, new_state;
2973 int err = -EINVAL;
2974 int port;
2975 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2976
2977 if (ibqp->rwq_ind_tbl)
2978 return -ENOSYS;
2979
2980 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2981 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2982
2983 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2984 IB_QPT_GSI : ibqp->qp_type;
2985
2986 mutex_lock(&qp->mutex);
2987
2988 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2989 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2990
2991 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2992 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2993 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2994 }
2995
2996 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
2997 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
2998 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
2999 attr_mask);
3000 goto out;
3001 }
3002 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3003 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3004 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3005 cur_state, new_state, ibqp->qp_type, attr_mask);
3006 goto out;
3007 }
3008
3009 if ((attr_mask & IB_QP_PORT) &&
3010 (attr->port_num == 0 ||
3011 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
3012 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3013 attr->port_num, dev->num_ports);
3014 goto out;
3015 }
3016
3017 if (attr_mask & IB_QP_PKEY_INDEX) {
3018 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3019 if (attr->pkey_index >=
3020 dev->mdev->port_caps[port - 1].pkey_table_len) {
3021 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3022 attr->pkey_index);
3023 goto out;
3024 }
3025 }
3026
3027 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3028 attr->max_rd_atomic >
3029 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3030 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3031 attr->max_rd_atomic);
3032 goto out;
3033 }
3034
3035 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3036 attr->max_dest_rd_atomic >
3037 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3038 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3039 attr->max_dest_rd_atomic);
3040 goto out;
3041 }
3042
3043 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3044 err = 0;
3045 goto out;
3046 }
3047
3048 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3049
3050 out:
3051 mutex_unlock(&qp->mutex);
3052 return err;
3053 }
3054
3055 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3056 {
3057 struct mlx5_ib_cq *cq;
3058 unsigned cur;
3059
3060 cur = wq->head - wq->tail;
3061 if (likely(cur + nreq < wq->max_post))
3062 return 0;
3063
3064 cq = to_mcq(ib_cq);
3065 spin_lock(&cq->lock);
3066 cur = wq->head - wq->tail;
3067 spin_unlock(&cq->lock);
3068
3069 return cur + nreq >= wq->max_post;
3070 }
3071
3072 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3073 u64 remote_addr, u32 rkey)
3074 {
3075 rseg->raddr = cpu_to_be64(remote_addr);
3076 rseg->rkey = cpu_to_be32(rkey);
3077 rseg->reserved = 0;
3078 }
3079
3080 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3081 struct ib_send_wr *wr, void *qend,
3082 struct mlx5_ib_qp *qp, int *size)
3083 {
3084 void *seg = eseg;
3085
3086 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3087
3088 if (wr->send_flags & IB_SEND_IP_CSUM)
3089 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3090 MLX5_ETH_WQE_L4_CSUM;
3091
3092 seg += sizeof(struct mlx5_wqe_eth_seg);
3093 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3094
3095 if (wr->opcode == IB_WR_LSO) {
3096 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3097 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3098 u64 left, leftlen, copysz;
3099 void *pdata = ud_wr->header;
3100
3101 left = ud_wr->hlen;
3102 eseg->mss = cpu_to_be16(ud_wr->mss);
3103 eseg->inline_hdr.sz = cpu_to_be16(left);
3104
3105 /*
3106 * check if there is space till the end of queue, if yes,
3107 * copy all in one shot, otherwise copy till the end of queue,
3108 * rollback and than the copy the left
3109 */
3110 leftlen = qend - (void *)eseg->inline_hdr.start;
3111 copysz = min_t(u64, leftlen, left);
3112
3113 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3114
3115 if (likely(copysz > size_of_inl_hdr_start)) {
3116 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3117 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3118 }
3119
3120 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3121 seg = mlx5_get_send_wqe(qp, 0);
3122 left -= copysz;
3123 pdata += copysz;
3124 memcpy(seg, pdata, left);
3125 seg += ALIGN(left, 16);
3126 *size += ALIGN(left, 16) / 16;
3127 }
3128 }
3129
3130 return seg;
3131 }
3132
3133 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3134 struct ib_send_wr *wr)
3135 {
3136 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3137 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3138 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3139 }
3140
3141 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3142 {
3143 dseg->byte_count = cpu_to_be32(sg->length);
3144 dseg->lkey = cpu_to_be32(sg->lkey);
3145 dseg->addr = cpu_to_be64(sg->addr);
3146 }
3147
3148 static u64 get_xlt_octo(u64 bytes)
3149 {
3150 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3151 MLX5_IB_UMR_OCTOWORD;
3152 }
3153
3154 static __be64 frwr_mkey_mask(void)
3155 {
3156 u64 result;
3157
3158 result = MLX5_MKEY_MASK_LEN |
3159 MLX5_MKEY_MASK_PAGE_SIZE |
3160 MLX5_MKEY_MASK_START_ADDR |
3161 MLX5_MKEY_MASK_EN_RINVAL |
3162 MLX5_MKEY_MASK_KEY |
3163 MLX5_MKEY_MASK_LR |
3164 MLX5_MKEY_MASK_LW |
3165 MLX5_MKEY_MASK_RR |
3166 MLX5_MKEY_MASK_RW |
3167 MLX5_MKEY_MASK_A |
3168 MLX5_MKEY_MASK_SMALL_FENCE |
3169 MLX5_MKEY_MASK_FREE;
3170
3171 return cpu_to_be64(result);
3172 }
3173
3174 static __be64 sig_mkey_mask(void)
3175 {
3176 u64 result;
3177
3178 result = MLX5_MKEY_MASK_LEN |
3179 MLX5_MKEY_MASK_PAGE_SIZE |
3180 MLX5_MKEY_MASK_START_ADDR |
3181 MLX5_MKEY_MASK_EN_SIGERR |
3182 MLX5_MKEY_MASK_EN_RINVAL |
3183 MLX5_MKEY_MASK_KEY |
3184 MLX5_MKEY_MASK_LR |
3185 MLX5_MKEY_MASK_LW |
3186 MLX5_MKEY_MASK_RR |
3187 MLX5_MKEY_MASK_RW |
3188 MLX5_MKEY_MASK_SMALL_FENCE |
3189 MLX5_MKEY_MASK_FREE |
3190 MLX5_MKEY_MASK_BSF_EN;
3191
3192 return cpu_to_be64(result);
3193 }
3194
3195 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3196 struct mlx5_ib_mr *mr)
3197 {
3198 int size = mr->ndescs * mr->desc_size;
3199
3200 memset(umr, 0, sizeof(*umr));
3201
3202 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3203 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3204 umr->mkey_mask = frwr_mkey_mask();
3205 }
3206
3207 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3208 {
3209 memset(umr, 0, sizeof(*umr));
3210 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3211 umr->flags = MLX5_UMR_INLINE;
3212 }
3213
3214 static __be64 get_umr_enable_mr_mask(void)
3215 {
3216 u64 result;
3217
3218 result = MLX5_MKEY_MASK_KEY |
3219 MLX5_MKEY_MASK_FREE;
3220
3221 return cpu_to_be64(result);
3222 }
3223
3224 static __be64 get_umr_disable_mr_mask(void)
3225 {
3226 u64 result;
3227
3228 result = MLX5_MKEY_MASK_FREE;
3229
3230 return cpu_to_be64(result);
3231 }
3232
3233 static __be64 get_umr_update_translation_mask(void)
3234 {
3235 u64 result;
3236
3237 result = MLX5_MKEY_MASK_LEN |
3238 MLX5_MKEY_MASK_PAGE_SIZE |
3239 MLX5_MKEY_MASK_START_ADDR;
3240
3241 return cpu_to_be64(result);
3242 }
3243
3244 static __be64 get_umr_update_access_mask(int atomic)
3245 {
3246 u64 result;
3247
3248 result = MLX5_MKEY_MASK_LR |
3249 MLX5_MKEY_MASK_LW |
3250 MLX5_MKEY_MASK_RR |
3251 MLX5_MKEY_MASK_RW;
3252
3253 if (atomic)
3254 result |= MLX5_MKEY_MASK_A;
3255
3256 return cpu_to_be64(result);
3257 }
3258
3259 static __be64 get_umr_update_pd_mask(void)
3260 {
3261 u64 result;
3262
3263 result = MLX5_MKEY_MASK_PD;
3264
3265 return cpu_to_be64(result);
3266 }
3267
3268 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3269 struct ib_send_wr *wr, int atomic)
3270 {
3271 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3272
3273 memset(umr, 0, sizeof(*umr));
3274
3275 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3276 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3277 else
3278 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3279
3280 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3281 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3282 u64 offset = get_xlt_octo(umrwr->offset);
3283
3284 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3285 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3286 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3287 }
3288 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3289 umr->mkey_mask |= get_umr_update_translation_mask();
3290 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3291 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3292 umr->mkey_mask |= get_umr_update_pd_mask();
3293 }
3294 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3295 umr->mkey_mask |= get_umr_enable_mr_mask();
3296 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3297 umr->mkey_mask |= get_umr_disable_mr_mask();
3298
3299 if (!wr->num_sge)
3300 umr->flags |= MLX5_UMR_INLINE;
3301 }
3302
3303 static u8 get_umr_flags(int acc)
3304 {
3305 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3306 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3307 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3308 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3309 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3310 }
3311
3312 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3313 struct mlx5_ib_mr *mr,
3314 u32 key, int access)
3315 {
3316 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3317
3318 memset(seg, 0, sizeof(*seg));
3319
3320 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3321 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3322 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3323 /* KLMs take twice the size of MTTs */
3324 ndescs *= 2;
3325
3326 seg->flags = get_umr_flags(access) | mr->access_mode;
3327 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3328 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3329 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3330 seg->len = cpu_to_be64(mr->ibmr.length);
3331 seg->xlt_oct_size = cpu_to_be32(ndescs);
3332 }
3333
3334 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3335 {
3336 memset(seg, 0, sizeof(*seg));
3337 seg->status = MLX5_MKEY_STATUS_FREE;
3338 }
3339
3340 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3341 {
3342 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3343
3344 memset(seg, 0, sizeof(*seg));
3345 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3346 seg->status = MLX5_MKEY_STATUS_FREE;
3347
3348 seg->flags = convert_access(umrwr->access_flags);
3349 if (umrwr->pd)
3350 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3351 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3352 !umrwr->length)
3353 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3354
3355 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3356 seg->len = cpu_to_be64(umrwr->length);
3357 seg->log2_page_size = umrwr->page_shift;
3358 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3359 mlx5_mkey_variant(umrwr->mkey));
3360 }
3361
3362 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3363 struct mlx5_ib_mr *mr,
3364 struct mlx5_ib_pd *pd)
3365 {
3366 int bcount = mr->desc_size * mr->ndescs;
3367
3368 dseg->addr = cpu_to_be64(mr->desc_map);
3369 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3370 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3371 }
3372
3373 static __be32 send_ieth(struct ib_send_wr *wr)
3374 {
3375 switch (wr->opcode) {
3376 case IB_WR_SEND_WITH_IMM:
3377 case IB_WR_RDMA_WRITE_WITH_IMM:
3378 return wr->ex.imm_data;
3379
3380 case IB_WR_SEND_WITH_INV:
3381 return cpu_to_be32(wr->ex.invalidate_rkey);
3382
3383 default:
3384 return 0;
3385 }
3386 }
3387
3388 static u8 calc_sig(void *wqe, int size)
3389 {
3390 u8 *p = wqe;
3391 u8 res = 0;
3392 int i;
3393
3394 for (i = 0; i < size; i++)
3395 res ^= p[i];
3396
3397 return ~res;
3398 }
3399
3400 static u8 wq_sig(void *wqe)
3401 {
3402 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3403 }
3404
3405 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3406 void *wqe, int *sz)
3407 {
3408 struct mlx5_wqe_inline_seg *seg;
3409 void *qend = qp->sq.qend;
3410 void *addr;
3411 int inl = 0;
3412 int copy;
3413 int len;
3414 int i;
3415
3416 seg = wqe;
3417 wqe += sizeof(*seg);
3418 for (i = 0; i < wr->num_sge; i++) {
3419 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3420 len = wr->sg_list[i].length;
3421 inl += len;
3422
3423 if (unlikely(inl > qp->max_inline_data))
3424 return -ENOMEM;
3425
3426 if (unlikely(wqe + len > qend)) {
3427 copy = qend - wqe;
3428 memcpy(wqe, addr, copy);
3429 addr += copy;
3430 len -= copy;
3431 wqe = mlx5_get_send_wqe(qp, 0);
3432 }
3433 memcpy(wqe, addr, len);
3434 wqe += len;
3435 }
3436
3437 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3438
3439 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3440
3441 return 0;
3442 }
3443
3444 static u16 prot_field_size(enum ib_signature_type type)
3445 {
3446 switch (type) {
3447 case IB_SIG_TYPE_T10_DIF:
3448 return MLX5_DIF_SIZE;
3449 default:
3450 return 0;
3451 }
3452 }
3453
3454 static u8 bs_selector(int block_size)
3455 {
3456 switch (block_size) {
3457 case 512: return 0x1;
3458 case 520: return 0x2;
3459 case 4096: return 0x3;
3460 case 4160: return 0x4;
3461 case 1073741824: return 0x5;
3462 default: return 0;
3463 }
3464 }
3465
3466 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3467 struct mlx5_bsf_inl *inl)
3468 {
3469 /* Valid inline section and allow BSF refresh */
3470 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3471 MLX5_BSF_REFRESH_DIF);
3472 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3473 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3474 /* repeating block */
3475 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3476 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3477 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3478
3479 if (domain->sig.dif.ref_remap)
3480 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3481
3482 if (domain->sig.dif.app_escape) {
3483 if (domain->sig.dif.ref_escape)
3484 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3485 else
3486 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3487 }
3488
3489 inl->dif_app_bitmask_check =
3490 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3491 }
3492
3493 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3494 struct ib_sig_attrs *sig_attrs,
3495 struct mlx5_bsf *bsf, u32 data_size)
3496 {
3497 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3498 struct mlx5_bsf_basic *basic = &bsf->basic;
3499 struct ib_sig_domain *mem = &sig_attrs->mem;
3500 struct ib_sig_domain *wire = &sig_attrs->wire;
3501
3502 memset(bsf, 0, sizeof(*bsf));
3503
3504 /* Basic + Extended + Inline */
3505 basic->bsf_size_sbs = 1 << 7;
3506 /* Input domain check byte mask */
3507 basic->check_byte_mask = sig_attrs->check_mask;
3508 basic->raw_data_size = cpu_to_be32(data_size);
3509
3510 /* Memory domain */
3511 switch (sig_attrs->mem.sig_type) {
3512 case IB_SIG_TYPE_NONE:
3513 break;
3514 case IB_SIG_TYPE_T10_DIF:
3515 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3516 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3517 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3518 break;
3519 default:
3520 return -EINVAL;
3521 }
3522
3523 /* Wire domain */
3524 switch (sig_attrs->wire.sig_type) {
3525 case IB_SIG_TYPE_NONE:
3526 break;
3527 case IB_SIG_TYPE_T10_DIF:
3528 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3529 mem->sig_type == wire->sig_type) {
3530 /* Same block structure */
3531 basic->bsf_size_sbs |= 1 << 4;
3532 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3533 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3534 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3535 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3536 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3537 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3538 } else
3539 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3540
3541 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3542 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3543 break;
3544 default:
3545 return -EINVAL;
3546 }
3547
3548 return 0;
3549 }
3550
3551 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3552 struct mlx5_ib_qp *qp, void **seg, int *size)
3553 {
3554 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3555 struct ib_mr *sig_mr = wr->sig_mr;
3556 struct mlx5_bsf *bsf;
3557 u32 data_len = wr->wr.sg_list->length;
3558 u32 data_key = wr->wr.sg_list->lkey;
3559 u64 data_va = wr->wr.sg_list->addr;
3560 int ret;
3561 int wqe_size;
3562
3563 if (!wr->prot ||
3564 (data_key == wr->prot->lkey &&
3565 data_va == wr->prot->addr &&
3566 data_len == wr->prot->length)) {
3567 /**
3568 * Source domain doesn't contain signature information
3569 * or data and protection are interleaved in memory.
3570 * So need construct:
3571 * ------------------
3572 * | data_klm |
3573 * ------------------
3574 * | BSF |
3575 * ------------------
3576 **/
3577 struct mlx5_klm *data_klm = *seg;
3578
3579 data_klm->bcount = cpu_to_be32(data_len);
3580 data_klm->key = cpu_to_be32(data_key);
3581 data_klm->va = cpu_to_be64(data_va);
3582 wqe_size = ALIGN(sizeof(*data_klm), 64);
3583 } else {
3584 /**
3585 * Source domain contains signature information
3586 * So need construct a strided block format:
3587 * ---------------------------
3588 * | stride_block_ctrl |
3589 * ---------------------------
3590 * | data_klm |
3591 * ---------------------------
3592 * | prot_klm |
3593 * ---------------------------
3594 * | BSF |
3595 * ---------------------------
3596 **/
3597 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3598 struct mlx5_stride_block_entry *data_sentry;
3599 struct mlx5_stride_block_entry *prot_sentry;
3600 u32 prot_key = wr->prot->lkey;
3601 u64 prot_va = wr->prot->addr;
3602 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3603 int prot_size;
3604
3605 sblock_ctrl = *seg;
3606 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3607 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3608
3609 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3610 if (!prot_size) {
3611 pr_err("Bad block size given: %u\n", block_size);
3612 return -EINVAL;
3613 }
3614 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3615 prot_size);
3616 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3617 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3618 sblock_ctrl->num_entries = cpu_to_be16(2);
3619
3620 data_sentry->bcount = cpu_to_be16(block_size);
3621 data_sentry->key = cpu_to_be32(data_key);
3622 data_sentry->va = cpu_to_be64(data_va);
3623 data_sentry->stride = cpu_to_be16(block_size);
3624
3625 prot_sentry->bcount = cpu_to_be16(prot_size);
3626 prot_sentry->key = cpu_to_be32(prot_key);
3627 prot_sentry->va = cpu_to_be64(prot_va);
3628 prot_sentry->stride = cpu_to_be16(prot_size);
3629
3630 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3631 sizeof(*prot_sentry), 64);
3632 }
3633
3634 *seg += wqe_size;
3635 *size += wqe_size / 16;
3636 if (unlikely((*seg == qp->sq.qend)))
3637 *seg = mlx5_get_send_wqe(qp, 0);
3638
3639 bsf = *seg;
3640 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3641 if (ret)
3642 return -EINVAL;
3643
3644 *seg += sizeof(*bsf);
3645 *size += sizeof(*bsf) / 16;
3646 if (unlikely((*seg == qp->sq.qend)))
3647 *seg = mlx5_get_send_wqe(qp, 0);
3648
3649 return 0;
3650 }
3651
3652 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3653 struct ib_sig_handover_wr *wr, u32 size,
3654 u32 length, u32 pdn)
3655 {
3656 struct ib_mr *sig_mr = wr->sig_mr;
3657 u32 sig_key = sig_mr->rkey;
3658 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3659
3660 memset(seg, 0, sizeof(*seg));
3661
3662 seg->flags = get_umr_flags(wr->access_flags) |
3663 MLX5_MKC_ACCESS_MODE_KLMS;
3664 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3665 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3666 MLX5_MKEY_BSF_EN | pdn);
3667 seg->len = cpu_to_be64(length);
3668 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3669 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3670 }
3671
3672 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3673 u32 size)
3674 {
3675 memset(umr, 0, sizeof(*umr));
3676
3677 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3678 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3679 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3680 umr->mkey_mask = sig_mkey_mask();
3681 }
3682
3683
3684 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3685 void **seg, int *size)
3686 {
3687 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3688 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3689 u32 pdn = get_pd(qp)->pdn;
3690 u32 xlt_size;
3691 int region_len, ret;
3692
3693 if (unlikely(wr->wr.num_sge != 1) ||
3694 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3695 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3696 unlikely(!sig_mr->sig->sig_status_checked))
3697 return -EINVAL;
3698
3699 /* length of the protected region, data + protection */
3700 region_len = wr->wr.sg_list->length;
3701 if (wr->prot &&
3702 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3703 wr->prot->addr != wr->wr.sg_list->addr ||
3704 wr->prot->length != wr->wr.sg_list->length))
3705 region_len += wr->prot->length;
3706
3707 /**
3708 * KLM octoword size - if protection was provided
3709 * then we use strided block format (3 octowords),
3710 * else we use single KLM (1 octoword)
3711 **/
3712 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3713
3714 set_sig_umr_segment(*seg, xlt_size);
3715 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3716 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3717 if (unlikely((*seg == qp->sq.qend)))
3718 *seg = mlx5_get_send_wqe(qp, 0);
3719
3720 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3721 *seg += sizeof(struct mlx5_mkey_seg);
3722 *size += sizeof(struct mlx5_mkey_seg) / 16;
3723 if (unlikely((*seg == qp->sq.qend)))
3724 *seg = mlx5_get_send_wqe(qp, 0);
3725
3726 ret = set_sig_data_segment(wr, qp, seg, size);
3727 if (ret)
3728 return ret;
3729
3730 sig_mr->sig->sig_status_checked = false;
3731 return 0;
3732 }
3733
3734 static int set_psv_wr(struct ib_sig_domain *domain,
3735 u32 psv_idx, void **seg, int *size)
3736 {
3737 struct mlx5_seg_set_psv *psv_seg = *seg;
3738
3739 memset(psv_seg, 0, sizeof(*psv_seg));
3740 psv_seg->psv_num = cpu_to_be32(psv_idx);
3741 switch (domain->sig_type) {
3742 case IB_SIG_TYPE_NONE:
3743 break;
3744 case IB_SIG_TYPE_T10_DIF:
3745 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3746 domain->sig.dif.app_tag);
3747 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3748 break;
3749 default:
3750 pr_err("Bad signature type (%d) is given.\n",
3751 domain->sig_type);
3752 return -EINVAL;
3753 }
3754
3755 *seg += sizeof(*psv_seg);
3756 *size += sizeof(*psv_seg) / 16;
3757
3758 return 0;
3759 }
3760
3761 static int set_reg_wr(struct mlx5_ib_qp *qp,
3762 struct ib_reg_wr *wr,
3763 void **seg, int *size)
3764 {
3765 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3766 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3767
3768 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3769 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3770 "Invalid IB_SEND_INLINE send flag\n");
3771 return -EINVAL;
3772 }
3773
3774 set_reg_umr_seg(*seg, mr);
3775 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3776 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3777 if (unlikely((*seg == qp->sq.qend)))
3778 *seg = mlx5_get_send_wqe(qp, 0);
3779
3780 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3781 *seg += sizeof(struct mlx5_mkey_seg);
3782 *size += sizeof(struct mlx5_mkey_seg) / 16;
3783 if (unlikely((*seg == qp->sq.qend)))
3784 *seg = mlx5_get_send_wqe(qp, 0);
3785
3786 set_reg_data_seg(*seg, mr, pd);
3787 *seg += sizeof(struct mlx5_wqe_data_seg);
3788 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3789
3790 return 0;
3791 }
3792
3793 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3794 {
3795 set_linv_umr_seg(*seg);
3796 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3797 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3798 if (unlikely((*seg == qp->sq.qend)))
3799 *seg = mlx5_get_send_wqe(qp, 0);
3800 set_linv_mkey_seg(*seg);
3801 *seg += sizeof(struct mlx5_mkey_seg);
3802 *size += sizeof(struct mlx5_mkey_seg) / 16;
3803 if (unlikely((*seg == qp->sq.qend)))
3804 *seg = mlx5_get_send_wqe(qp, 0);
3805 }
3806
3807 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3808 {
3809 __be32 *p = NULL;
3810 int tidx = idx;
3811 int i, j;
3812
3813 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3814 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3815 if ((i & 0xf) == 0) {
3816 void *buf = mlx5_get_send_wqe(qp, tidx);
3817 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3818 p = buf;
3819 j = 0;
3820 }
3821 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3822 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3823 be32_to_cpu(p[j + 3]));
3824 }
3825 }
3826
3827 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3828 struct mlx5_wqe_ctrl_seg **ctrl,
3829 struct ib_send_wr *wr, unsigned *idx,
3830 int *size, int nreq)
3831 {
3832 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3833 return -ENOMEM;
3834
3835 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3836 *seg = mlx5_get_send_wqe(qp, *idx);
3837 *ctrl = *seg;
3838 *(uint32_t *)(*seg + 8) = 0;
3839 (*ctrl)->imm = send_ieth(wr);
3840 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3841 (wr->send_flags & IB_SEND_SIGNALED ?
3842 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3843 (wr->send_flags & IB_SEND_SOLICITED ?
3844 MLX5_WQE_CTRL_SOLICITED : 0);
3845
3846 *seg += sizeof(**ctrl);
3847 *size = sizeof(**ctrl) / 16;
3848
3849 return 0;
3850 }
3851
3852 static void finish_wqe(struct mlx5_ib_qp *qp,
3853 struct mlx5_wqe_ctrl_seg *ctrl,
3854 u8 size, unsigned idx, u64 wr_id,
3855 int nreq, u8 fence, u32 mlx5_opcode)
3856 {
3857 u8 opmod = 0;
3858
3859 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3860 mlx5_opcode | ((u32)opmod << 24));
3861 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3862 ctrl->fm_ce_se |= fence;
3863 if (unlikely(qp->wq_sig))
3864 ctrl->signature = wq_sig(ctrl);
3865
3866 qp->sq.wrid[idx] = wr_id;
3867 qp->sq.w_list[idx].opcode = mlx5_opcode;
3868 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3869 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3870 qp->sq.w_list[idx].next = qp->sq.cur_post;
3871 }
3872
3873
3874 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3875 struct ib_send_wr **bad_wr)
3876 {
3877 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3878 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3879 struct mlx5_core_dev *mdev = dev->mdev;
3880 struct mlx5_ib_qp *qp;
3881 struct mlx5_ib_mr *mr;
3882 struct mlx5_wqe_data_seg *dpseg;
3883 struct mlx5_wqe_xrc_seg *xrc;
3884 struct mlx5_bf *bf;
3885 int uninitialized_var(size);
3886 void *qend;
3887 unsigned long flags;
3888 unsigned idx;
3889 int err = 0;
3890 int num_sge;
3891 void *seg;
3892 int nreq;
3893 int i;
3894 u8 next_fence = 0;
3895 u8 fence;
3896
3897 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3898 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3899
3900 qp = to_mqp(ibqp);
3901 bf = &qp->bf;
3902 qend = qp->sq.qend;
3903
3904 spin_lock_irqsave(&qp->sq.lock, flags);
3905
3906 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3907 err = -EIO;
3908 *bad_wr = wr;
3909 nreq = 0;
3910 goto out;
3911 }
3912
3913 for (nreq = 0; wr; nreq++, wr = wr->next) {
3914 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3915 mlx5_ib_warn(dev, "\n");
3916 err = -EINVAL;
3917 *bad_wr = wr;
3918 goto out;
3919 }
3920
3921 num_sge = wr->num_sge;
3922 if (unlikely(num_sge > qp->sq.max_gs)) {
3923 mlx5_ib_warn(dev, "\n");
3924 err = -EINVAL;
3925 *bad_wr = wr;
3926 goto out;
3927 }
3928
3929 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3930 if (err) {
3931 mlx5_ib_warn(dev, "\n");
3932 err = -ENOMEM;
3933 *bad_wr = wr;
3934 goto out;
3935 }
3936
3937 if (wr->opcode == IB_WR_LOCAL_INV ||
3938 wr->opcode == IB_WR_REG_MR) {
3939 fence = dev->umr_fence;
3940 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3941 } else if (wr->send_flags & IB_SEND_FENCE) {
3942 if (qp->next_fence)
3943 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3944 else
3945 fence = MLX5_FENCE_MODE_FENCE;
3946 } else {
3947 fence = qp->next_fence;
3948 }
3949
3950 switch (ibqp->qp_type) {
3951 case IB_QPT_XRC_INI:
3952 xrc = seg;
3953 seg += sizeof(*xrc);
3954 size += sizeof(*xrc) / 16;
3955 /* fall through */
3956 case IB_QPT_RC:
3957 switch (wr->opcode) {
3958 case IB_WR_RDMA_READ:
3959 case IB_WR_RDMA_WRITE:
3960 case IB_WR_RDMA_WRITE_WITH_IMM:
3961 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3962 rdma_wr(wr)->rkey);
3963 seg += sizeof(struct mlx5_wqe_raddr_seg);
3964 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3965 break;
3966
3967 case IB_WR_ATOMIC_CMP_AND_SWP:
3968 case IB_WR_ATOMIC_FETCH_AND_ADD:
3969 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3970 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3971 err = -ENOSYS;
3972 *bad_wr = wr;
3973 goto out;
3974
3975 case IB_WR_LOCAL_INV:
3976 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3977 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3978 set_linv_wr(qp, &seg, &size);
3979 num_sge = 0;
3980 break;
3981
3982 case IB_WR_REG_MR:
3983 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3984 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3985 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3986 if (err) {
3987 *bad_wr = wr;
3988 goto out;
3989 }
3990 num_sge = 0;
3991 break;
3992
3993 case IB_WR_REG_SIG_MR:
3994 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3995 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3996
3997 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3998 err = set_sig_umr_wr(wr, qp, &seg, &size);
3999 if (err) {
4000 mlx5_ib_warn(dev, "\n");
4001 *bad_wr = wr;
4002 goto out;
4003 }
4004
4005 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4006 fence, MLX5_OPCODE_UMR);
4007 /*
4008 * SET_PSV WQEs are not signaled and solicited
4009 * on error
4010 */
4011 wr->send_flags &= ~IB_SEND_SIGNALED;
4012 wr->send_flags |= IB_SEND_SOLICITED;
4013 err = begin_wqe(qp, &seg, &ctrl, wr,
4014 &idx, &size, nreq);
4015 if (err) {
4016 mlx5_ib_warn(dev, "\n");
4017 err = -ENOMEM;
4018 *bad_wr = wr;
4019 goto out;
4020 }
4021
4022 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4023 mr->sig->psv_memory.psv_idx, &seg,
4024 &size);
4025 if (err) {
4026 mlx5_ib_warn(dev, "\n");
4027 *bad_wr = wr;
4028 goto out;
4029 }
4030
4031 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4032 fence, MLX5_OPCODE_SET_PSV);
4033 err = begin_wqe(qp, &seg, &ctrl, wr,
4034 &idx, &size, nreq);
4035 if (err) {
4036 mlx5_ib_warn(dev, "\n");
4037 err = -ENOMEM;
4038 *bad_wr = wr;
4039 goto out;
4040 }
4041
4042 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4043 mr->sig->psv_wire.psv_idx, &seg,
4044 &size);
4045 if (err) {
4046 mlx5_ib_warn(dev, "\n");
4047 *bad_wr = wr;
4048 goto out;
4049 }
4050
4051 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4052 fence, MLX5_OPCODE_SET_PSV);
4053 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4054 num_sge = 0;
4055 goto skip_psv;
4056
4057 default:
4058 break;
4059 }
4060 break;
4061
4062 case IB_QPT_UC:
4063 switch (wr->opcode) {
4064 case IB_WR_RDMA_WRITE:
4065 case IB_WR_RDMA_WRITE_WITH_IMM:
4066 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4067 rdma_wr(wr)->rkey);
4068 seg += sizeof(struct mlx5_wqe_raddr_seg);
4069 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4070 break;
4071
4072 default:
4073 break;
4074 }
4075 break;
4076
4077 case IB_QPT_SMI:
4078 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4079 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4080 err = -EPERM;
4081 *bad_wr = wr;
4082 goto out;
4083 }
4084 /* fall through */
4085 case MLX5_IB_QPT_HW_GSI:
4086 set_datagram_seg(seg, wr);
4087 seg += sizeof(struct mlx5_wqe_datagram_seg);
4088 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4089 if (unlikely((seg == qend)))
4090 seg = mlx5_get_send_wqe(qp, 0);
4091 break;
4092 case IB_QPT_UD:
4093 set_datagram_seg(seg, wr);
4094 seg += sizeof(struct mlx5_wqe_datagram_seg);
4095 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4096
4097 if (unlikely((seg == qend)))
4098 seg = mlx5_get_send_wqe(qp, 0);
4099
4100 /* handle qp that supports ud offload */
4101 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4102 struct mlx5_wqe_eth_pad *pad;
4103
4104 pad = seg;
4105 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4106 seg += sizeof(struct mlx5_wqe_eth_pad);
4107 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4108
4109 seg = set_eth_seg(seg, wr, qend, qp, &size);
4110
4111 if (unlikely((seg == qend)))
4112 seg = mlx5_get_send_wqe(qp, 0);
4113 }
4114 break;
4115 case MLX5_IB_QPT_REG_UMR:
4116 if (wr->opcode != MLX5_IB_WR_UMR) {
4117 err = -EINVAL;
4118 mlx5_ib_warn(dev, "bad opcode\n");
4119 goto out;
4120 }
4121 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4122 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4123 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4124 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4125 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4126 if (unlikely((seg == qend)))
4127 seg = mlx5_get_send_wqe(qp, 0);
4128 set_reg_mkey_segment(seg, wr);
4129 seg += sizeof(struct mlx5_mkey_seg);
4130 size += sizeof(struct mlx5_mkey_seg) / 16;
4131 if (unlikely((seg == qend)))
4132 seg = mlx5_get_send_wqe(qp, 0);
4133 break;
4134
4135 default:
4136 break;
4137 }
4138
4139 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4140 int uninitialized_var(sz);
4141
4142 err = set_data_inl_seg(qp, wr, seg, &sz);
4143 if (unlikely(err)) {
4144 mlx5_ib_warn(dev, "\n");
4145 *bad_wr = wr;
4146 goto out;
4147 }
4148 size += sz;
4149 } else {
4150 dpseg = seg;
4151 for (i = 0; i < num_sge; i++) {
4152 if (unlikely(dpseg == qend)) {
4153 seg = mlx5_get_send_wqe(qp, 0);
4154 dpseg = seg;
4155 }
4156 if (likely(wr->sg_list[i].length)) {
4157 set_data_ptr_seg(dpseg, wr->sg_list + i);
4158 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4159 dpseg++;
4160 }
4161 }
4162 }
4163
4164 qp->next_fence = next_fence;
4165 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4166 mlx5_ib_opcode[wr->opcode]);
4167 skip_psv:
4168 if (0)
4169 dump_wqe(qp, idx, size);
4170 }
4171
4172 out:
4173 if (likely(nreq)) {
4174 qp->sq.head += nreq;
4175
4176 /* Make sure that descriptors are written before
4177 * updating doorbell record and ringing the doorbell
4178 */
4179 wmb();
4180
4181 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4182
4183 /* Make sure doorbell record is visible to the HCA before
4184 * we hit doorbell */
4185 wmb();
4186
4187 /* currently we support only regular doorbells */
4188 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4189 /* Make sure doorbells don't leak out of SQ spinlock
4190 * and reach the HCA out of order.
4191 */
4192 mmiowb();
4193 bf->offset ^= bf->buf_size;
4194 }
4195
4196 spin_unlock_irqrestore(&qp->sq.lock, flags);
4197
4198 return err;
4199 }
4200
4201 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4202 {
4203 sig->signature = calc_sig(sig, size);
4204 }
4205
4206 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4207 struct ib_recv_wr **bad_wr)
4208 {
4209 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4210 struct mlx5_wqe_data_seg *scat;
4211 struct mlx5_rwqe_sig *sig;
4212 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4213 struct mlx5_core_dev *mdev = dev->mdev;
4214 unsigned long flags;
4215 int err = 0;
4216 int nreq;
4217 int ind;
4218 int i;
4219
4220 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4221 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4222
4223 spin_lock_irqsave(&qp->rq.lock, flags);
4224
4225 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4226 err = -EIO;
4227 *bad_wr = wr;
4228 nreq = 0;
4229 goto out;
4230 }
4231
4232 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4233
4234 for (nreq = 0; wr; nreq++, wr = wr->next) {
4235 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4236 err = -ENOMEM;
4237 *bad_wr = wr;
4238 goto out;
4239 }
4240
4241 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4242 err = -EINVAL;
4243 *bad_wr = wr;
4244 goto out;
4245 }
4246
4247 scat = get_recv_wqe(qp, ind);
4248 if (qp->wq_sig)
4249 scat++;
4250
4251 for (i = 0; i < wr->num_sge; i++)
4252 set_data_ptr_seg(scat + i, wr->sg_list + i);
4253
4254 if (i < qp->rq.max_gs) {
4255 scat[i].byte_count = 0;
4256 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4257 scat[i].addr = 0;
4258 }
4259
4260 if (qp->wq_sig) {
4261 sig = (struct mlx5_rwqe_sig *)scat;
4262 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4263 }
4264
4265 qp->rq.wrid[ind] = wr->wr_id;
4266
4267 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4268 }
4269
4270 out:
4271 if (likely(nreq)) {
4272 qp->rq.head += nreq;
4273
4274 /* Make sure that descriptors are written before
4275 * doorbell record.
4276 */
4277 wmb();
4278
4279 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4280 }
4281
4282 spin_unlock_irqrestore(&qp->rq.lock, flags);
4283
4284 return err;
4285 }
4286
4287 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4288 {
4289 switch (mlx5_state) {
4290 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4291 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4292 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4293 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4294 case MLX5_QP_STATE_SQ_DRAINING:
4295 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4296 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4297 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4298 default: return -1;
4299 }
4300 }
4301
4302 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4303 {
4304 switch (mlx5_mig_state) {
4305 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4306 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4307 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4308 default: return -1;
4309 }
4310 }
4311
4312 static int to_ib_qp_access_flags(int mlx5_flags)
4313 {
4314 int ib_flags = 0;
4315
4316 if (mlx5_flags & MLX5_QP_BIT_RRE)
4317 ib_flags |= IB_ACCESS_REMOTE_READ;
4318 if (mlx5_flags & MLX5_QP_BIT_RWE)
4319 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4320 if (mlx5_flags & MLX5_QP_BIT_RAE)
4321 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4322
4323 return ib_flags;
4324 }
4325
4326 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4327 struct rdma_ah_attr *ah_attr,
4328 struct mlx5_qp_path *path)
4329 {
4330 struct mlx5_core_dev *dev = ibdev->mdev;
4331
4332 memset(ah_attr, 0, sizeof(*ah_attr));
4333
4334 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4335 rdma_ah_set_port_num(ah_attr, path->port);
4336 if (rdma_ah_get_port_num(ah_attr) == 0 ||
4337 rdma_ah_get_port_num(ah_attr) > MLX5_CAP_GEN(dev, num_ports))
4338 return;
4339
4340 rdma_ah_set_port_num(ah_attr, path->port);
4341 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4342
4343 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4344 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4345 rdma_ah_set_static_rate(ah_attr,
4346 path->static_rate ? path->static_rate - 5 : 0);
4347 if (path->grh_mlid & (1 << 7)) {
4348 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4349
4350 rdma_ah_set_grh(ah_attr, NULL,
4351 tc_fl & 0xfffff,
4352 path->mgid_index,
4353 path->hop_limit,
4354 (tc_fl >> 20) & 0xff);
4355 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4356 }
4357 }
4358
4359 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4360 struct mlx5_ib_sq *sq,
4361 u8 *sq_state)
4362 {
4363 void *out;
4364 void *sqc;
4365 int inlen;
4366 int err;
4367
4368 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4369 out = kvzalloc(inlen, GFP_KERNEL);
4370 if (!out)
4371 return -ENOMEM;
4372
4373 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4374 if (err)
4375 goto out;
4376
4377 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4378 *sq_state = MLX5_GET(sqc, sqc, state);
4379 sq->state = *sq_state;
4380
4381 out:
4382 kvfree(out);
4383 return err;
4384 }
4385
4386 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4387 struct mlx5_ib_rq *rq,
4388 u8 *rq_state)
4389 {
4390 void *out;
4391 void *rqc;
4392 int inlen;
4393 int err;
4394
4395 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4396 out = kvzalloc(inlen, GFP_KERNEL);
4397 if (!out)
4398 return -ENOMEM;
4399
4400 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4401 if (err)
4402 goto out;
4403
4404 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4405 *rq_state = MLX5_GET(rqc, rqc, state);
4406 rq->state = *rq_state;
4407
4408 out:
4409 kvfree(out);
4410 return err;
4411 }
4412
4413 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4414 struct mlx5_ib_qp *qp, u8 *qp_state)
4415 {
4416 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4417 [MLX5_RQC_STATE_RST] = {
4418 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4419 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4420 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4421 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4422 },
4423 [MLX5_RQC_STATE_RDY] = {
4424 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4425 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4426 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4427 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4428 },
4429 [MLX5_RQC_STATE_ERR] = {
4430 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4431 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4432 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4433 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4434 },
4435 [MLX5_RQ_STATE_NA] = {
4436 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4437 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4438 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4439 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4440 },
4441 };
4442
4443 *qp_state = sqrq_trans[rq_state][sq_state];
4444
4445 if (*qp_state == MLX5_QP_STATE_BAD) {
4446 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4447 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4448 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4449 return -EINVAL;
4450 }
4451
4452 if (*qp_state == MLX5_QP_STATE)
4453 *qp_state = qp->state;
4454
4455 return 0;
4456 }
4457
4458 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4459 struct mlx5_ib_qp *qp,
4460 u8 *raw_packet_qp_state)
4461 {
4462 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4463 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4464 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4465 int err;
4466 u8 sq_state = MLX5_SQ_STATE_NA;
4467 u8 rq_state = MLX5_RQ_STATE_NA;
4468
4469 if (qp->sq.wqe_cnt) {
4470 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4471 if (err)
4472 return err;
4473 }
4474
4475 if (qp->rq.wqe_cnt) {
4476 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4477 if (err)
4478 return err;
4479 }
4480
4481 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4482 raw_packet_qp_state);
4483 }
4484
4485 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4486 struct ib_qp_attr *qp_attr)
4487 {
4488 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4489 struct mlx5_qp_context *context;
4490 int mlx5_state;
4491 u32 *outb;
4492 int err = 0;
4493
4494 outb = kzalloc(outlen, GFP_KERNEL);
4495 if (!outb)
4496 return -ENOMEM;
4497
4498 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4499 outlen);
4500 if (err)
4501 goto out;
4502
4503 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4504 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4505
4506 mlx5_state = be32_to_cpu(context->flags) >> 28;
4507
4508 qp->state = to_ib_qp_state(mlx5_state);
4509 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4510 qp_attr->path_mig_state =
4511 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4512 qp_attr->qkey = be32_to_cpu(context->qkey);
4513 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4514 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4515 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4516 qp_attr->qp_access_flags =
4517 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4518
4519 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4520 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4521 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4522 qp_attr->alt_pkey_index =
4523 be16_to_cpu(context->alt_path.pkey_index);
4524 qp_attr->alt_port_num =
4525 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4526 }
4527
4528 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4529 qp_attr->port_num = context->pri_path.port;
4530
4531 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4532 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4533
4534 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4535
4536 qp_attr->max_dest_rd_atomic =
4537 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4538 qp_attr->min_rnr_timer =
4539 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4540 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4541 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4542 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4543 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4544
4545 out:
4546 kfree(outb);
4547 return err;
4548 }
4549
4550 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4551 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4552 {
4553 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4554 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4555 int err = 0;
4556 u8 raw_packet_qp_state;
4557
4558 if (ibqp->rwq_ind_tbl)
4559 return -ENOSYS;
4560
4561 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4562 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4563 qp_init_attr);
4564
4565 /* Not all of output fields are applicable, make sure to zero them */
4566 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4567 memset(qp_attr, 0, sizeof(*qp_attr));
4568
4569 mutex_lock(&qp->mutex);
4570
4571 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4572 qp->flags & MLX5_IB_QP_UNDERLAY) {
4573 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4574 if (err)
4575 goto out;
4576 qp->state = raw_packet_qp_state;
4577 qp_attr->port_num = 1;
4578 } else {
4579 err = query_qp_attr(dev, qp, qp_attr);
4580 if (err)
4581 goto out;
4582 }
4583
4584 qp_attr->qp_state = qp->state;
4585 qp_attr->cur_qp_state = qp_attr->qp_state;
4586 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4587 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4588
4589 if (!ibqp->uobject) {
4590 qp_attr->cap.max_send_wr = qp->sq.max_post;
4591 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4592 qp_init_attr->qp_context = ibqp->qp_context;
4593 } else {
4594 qp_attr->cap.max_send_wr = 0;
4595 qp_attr->cap.max_send_sge = 0;
4596 }
4597
4598 qp_init_attr->qp_type = ibqp->qp_type;
4599 qp_init_attr->recv_cq = ibqp->recv_cq;
4600 qp_init_attr->send_cq = ibqp->send_cq;
4601 qp_init_attr->srq = ibqp->srq;
4602 qp_attr->cap.max_inline_data = qp->max_inline_data;
4603
4604 qp_init_attr->cap = qp_attr->cap;
4605
4606 qp_init_attr->create_flags = 0;
4607 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4608 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4609
4610 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4611 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4612 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4613 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4614 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4615 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4616 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4617 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4618
4619 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4620 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4621
4622 out:
4623 mutex_unlock(&qp->mutex);
4624 return err;
4625 }
4626
4627 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4628 struct ib_ucontext *context,
4629 struct ib_udata *udata)
4630 {
4631 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4632 struct mlx5_ib_xrcd *xrcd;
4633 int err;
4634
4635 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4636 return ERR_PTR(-ENOSYS);
4637
4638 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4639 if (!xrcd)
4640 return ERR_PTR(-ENOMEM);
4641
4642 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4643 if (err) {
4644 kfree(xrcd);
4645 return ERR_PTR(-ENOMEM);
4646 }
4647
4648 return &xrcd->ibxrcd;
4649 }
4650
4651 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4652 {
4653 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4654 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4655 int err;
4656
4657 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4658 if (err) {
4659 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4660 return err;
4661 }
4662
4663 kfree(xrcd);
4664
4665 return 0;
4666 }
4667
4668 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4669 {
4670 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4671 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4672 struct ib_event event;
4673
4674 if (rwq->ibwq.event_handler) {
4675 event.device = rwq->ibwq.device;
4676 event.element.wq = &rwq->ibwq;
4677 switch (type) {
4678 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4679 event.event = IB_EVENT_WQ_FATAL;
4680 break;
4681 default:
4682 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4683 return;
4684 }
4685
4686 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4687 }
4688 }
4689
4690 static int set_delay_drop(struct mlx5_ib_dev *dev)
4691 {
4692 int err = 0;
4693
4694 mutex_lock(&dev->delay_drop.lock);
4695 if (dev->delay_drop.activate)
4696 goto out;
4697
4698 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4699 if (err)
4700 goto out;
4701
4702 dev->delay_drop.activate = true;
4703 out:
4704 mutex_unlock(&dev->delay_drop.lock);
4705
4706 if (!err)
4707 atomic_inc(&dev->delay_drop.rqs_cnt);
4708 return err;
4709 }
4710
4711 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4712 struct ib_wq_init_attr *init_attr)
4713 {
4714 struct mlx5_ib_dev *dev;
4715 int has_net_offloads;
4716 __be64 *rq_pas0;
4717 void *in;
4718 void *rqc;
4719 void *wq;
4720 int inlen;
4721 int err;
4722
4723 dev = to_mdev(pd->device);
4724
4725 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4726 in = kvzalloc(inlen, GFP_KERNEL);
4727 if (!in)
4728 return -ENOMEM;
4729
4730 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4731 MLX5_SET(rqc, rqc, mem_rq_type,
4732 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4733 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4734 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4735 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4736 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4737 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4738 MLX5_SET(wq, wq, wq_type,
4739 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4740 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4741 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4742 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4743 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4744 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4745 MLX5_SET(wq, wq, log_wqe_stride_size,
4746 rwq->single_stride_log_num_of_bytes -
4747 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4748 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
4749 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
4750 }
4751 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4752 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4753 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4754 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4755 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4756 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4757 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4758 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4759 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4760 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4761 err = -EOPNOTSUPP;
4762 goto out;
4763 }
4764 } else {
4765 MLX5_SET(rqc, rqc, vsd, 1);
4766 }
4767 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4768 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4769 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4770 err = -EOPNOTSUPP;
4771 goto out;
4772 }
4773 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4774 }
4775 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4776 if (!(dev->ib_dev.attrs.raw_packet_caps &
4777 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4778 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4779 err = -EOPNOTSUPP;
4780 goto out;
4781 }
4782 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4783 }
4784 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4785 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4786 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4787 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4788 err = set_delay_drop(dev);
4789 if (err) {
4790 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4791 err);
4792 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4793 } else {
4794 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4795 }
4796 }
4797 out:
4798 kvfree(in);
4799 return err;
4800 }
4801
4802 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4803 struct ib_wq_init_attr *wq_init_attr,
4804 struct mlx5_ib_create_wq *ucmd,
4805 struct mlx5_ib_rwq *rwq)
4806 {
4807 /* Sanity check RQ size before proceeding */
4808 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4809 return -EINVAL;
4810
4811 if (!ucmd->rq_wqe_count)
4812 return -EINVAL;
4813
4814 rwq->wqe_count = ucmd->rq_wqe_count;
4815 rwq->wqe_shift = ucmd->rq_wqe_shift;
4816 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4817 rwq->log_rq_stride = rwq->wqe_shift;
4818 rwq->log_rq_size = ilog2(rwq->wqe_count);
4819 return 0;
4820 }
4821
4822 static int prepare_user_rq(struct ib_pd *pd,
4823 struct ib_wq_init_attr *init_attr,
4824 struct ib_udata *udata,
4825 struct mlx5_ib_rwq *rwq)
4826 {
4827 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4828 struct mlx5_ib_create_wq ucmd = {};
4829 int err;
4830 size_t required_cmd_sz;
4831
4832 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4833 + sizeof(ucmd.single_stride_log_num_of_bytes);
4834 if (udata->inlen < required_cmd_sz) {
4835 mlx5_ib_dbg(dev, "invalid inlen\n");
4836 return -EINVAL;
4837 }
4838
4839 if (udata->inlen > sizeof(ucmd) &&
4840 !ib_is_udata_cleared(udata, sizeof(ucmd),
4841 udata->inlen - sizeof(ucmd))) {
4842 mlx5_ib_dbg(dev, "inlen is not supported\n");
4843 return -EOPNOTSUPP;
4844 }
4845
4846 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4847 mlx5_ib_dbg(dev, "copy failed\n");
4848 return -EFAULT;
4849 }
4850
4851 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4852 mlx5_ib_dbg(dev, "invalid comp mask\n");
4853 return -EOPNOTSUPP;
4854 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4855 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4856 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4857 return -EOPNOTSUPP;
4858 }
4859 if ((ucmd.single_stride_log_num_of_bytes <
4860 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4861 (ucmd.single_stride_log_num_of_bytes >
4862 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4863 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4864 ucmd.single_stride_log_num_of_bytes,
4865 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4866 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4867 return -EINVAL;
4868 }
4869 if ((ucmd.single_wqe_log_num_of_strides >
4870 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4871 (ucmd.single_wqe_log_num_of_strides <
4872 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
4873 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
4874 ucmd.single_wqe_log_num_of_strides,
4875 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4876 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4877 return -EINVAL;
4878 }
4879 rwq->single_stride_log_num_of_bytes =
4880 ucmd.single_stride_log_num_of_bytes;
4881 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4882 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4883 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4884 }
4885
4886 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4887 if (err) {
4888 mlx5_ib_dbg(dev, "err %d\n", err);
4889 return err;
4890 }
4891
4892 err = create_user_rq(dev, pd, rwq, &ucmd);
4893 if (err) {
4894 mlx5_ib_dbg(dev, "err %d\n", err);
4895 if (err)
4896 return err;
4897 }
4898
4899 rwq->user_index = ucmd.user_index;
4900 return 0;
4901 }
4902
4903 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4904 struct ib_wq_init_attr *init_attr,
4905 struct ib_udata *udata)
4906 {
4907 struct mlx5_ib_dev *dev;
4908 struct mlx5_ib_rwq *rwq;
4909 struct mlx5_ib_create_wq_resp resp = {};
4910 size_t min_resp_len;
4911 int err;
4912
4913 if (!udata)
4914 return ERR_PTR(-ENOSYS);
4915
4916 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4917 if (udata->outlen && udata->outlen < min_resp_len)
4918 return ERR_PTR(-EINVAL);
4919
4920 dev = to_mdev(pd->device);
4921 switch (init_attr->wq_type) {
4922 case IB_WQT_RQ:
4923 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4924 if (!rwq)
4925 return ERR_PTR(-ENOMEM);
4926 err = prepare_user_rq(pd, init_attr, udata, rwq);
4927 if (err)
4928 goto err;
4929 err = create_rq(rwq, pd, init_attr);
4930 if (err)
4931 goto err_user_rq;
4932 break;
4933 default:
4934 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4935 init_attr->wq_type);
4936 return ERR_PTR(-EINVAL);
4937 }
4938
4939 rwq->ibwq.wq_num = rwq->core_qp.qpn;
4940 rwq->ibwq.state = IB_WQS_RESET;
4941 if (udata->outlen) {
4942 resp.response_length = offsetof(typeof(resp), response_length) +
4943 sizeof(resp.response_length);
4944 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4945 if (err)
4946 goto err_copy;
4947 }
4948
4949 rwq->core_qp.event = mlx5_ib_wq_event;
4950 rwq->ibwq.event_handler = init_attr->event_handler;
4951 return &rwq->ibwq;
4952
4953 err_copy:
4954 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4955 err_user_rq:
4956 destroy_user_rq(dev, pd, rwq);
4957 err:
4958 kfree(rwq);
4959 return ERR_PTR(err);
4960 }
4961
4962 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4963 {
4964 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4965 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4966
4967 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4968 destroy_user_rq(dev, wq->pd, rwq);
4969 kfree(rwq);
4970
4971 return 0;
4972 }
4973
4974 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4975 struct ib_rwq_ind_table_init_attr *init_attr,
4976 struct ib_udata *udata)
4977 {
4978 struct mlx5_ib_dev *dev = to_mdev(device);
4979 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4980 int sz = 1 << init_attr->log_ind_tbl_size;
4981 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4982 size_t min_resp_len;
4983 int inlen;
4984 int err;
4985 int i;
4986 u32 *in;
4987 void *rqtc;
4988
4989 if (udata->inlen > 0 &&
4990 !ib_is_udata_cleared(udata, 0,
4991 udata->inlen))
4992 return ERR_PTR(-EOPNOTSUPP);
4993
4994 if (init_attr->log_ind_tbl_size >
4995 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4996 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4997 init_attr->log_ind_tbl_size,
4998 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4999 return ERR_PTR(-EINVAL);
5000 }
5001
5002 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5003 if (udata->outlen && udata->outlen < min_resp_len)
5004 return ERR_PTR(-EINVAL);
5005
5006 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5007 if (!rwq_ind_tbl)
5008 return ERR_PTR(-ENOMEM);
5009
5010 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5011 in = kvzalloc(inlen, GFP_KERNEL);
5012 if (!in) {
5013 err = -ENOMEM;
5014 goto err;
5015 }
5016
5017 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5018
5019 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5020 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5021
5022 for (i = 0; i < sz; i++)
5023 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5024
5025 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5026 kvfree(in);
5027
5028 if (err)
5029 goto err;
5030
5031 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5032 if (udata->outlen) {
5033 resp.response_length = offsetof(typeof(resp), response_length) +
5034 sizeof(resp.response_length);
5035 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5036 if (err)
5037 goto err_copy;
5038 }
5039
5040 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5041
5042 err_copy:
5043 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5044 err:
5045 kfree(rwq_ind_tbl);
5046 return ERR_PTR(err);
5047 }
5048
5049 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5050 {
5051 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5052 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5053
5054 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5055
5056 kfree(rwq_ind_tbl);
5057 return 0;
5058 }
5059
5060 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5061 u32 wq_attr_mask, struct ib_udata *udata)
5062 {
5063 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5064 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5065 struct mlx5_ib_modify_wq ucmd = {};
5066 size_t required_cmd_sz;
5067 int curr_wq_state;
5068 int wq_state;
5069 int inlen;
5070 int err;
5071 void *rqc;
5072 void *in;
5073
5074 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5075 if (udata->inlen < required_cmd_sz)
5076 return -EINVAL;
5077
5078 if (udata->inlen > sizeof(ucmd) &&
5079 !ib_is_udata_cleared(udata, sizeof(ucmd),
5080 udata->inlen - sizeof(ucmd)))
5081 return -EOPNOTSUPP;
5082
5083 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5084 return -EFAULT;
5085
5086 if (ucmd.comp_mask || ucmd.reserved)
5087 return -EOPNOTSUPP;
5088
5089 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5090 in = kvzalloc(inlen, GFP_KERNEL);
5091 if (!in)
5092 return -ENOMEM;
5093
5094 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5095
5096 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5097 wq_attr->curr_wq_state : wq->state;
5098 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5099 wq_attr->wq_state : curr_wq_state;
5100 if (curr_wq_state == IB_WQS_ERR)
5101 curr_wq_state = MLX5_RQC_STATE_ERR;
5102 if (wq_state == IB_WQS_ERR)
5103 wq_state = MLX5_RQC_STATE_ERR;
5104 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5105 MLX5_SET(rqc, rqc, state, wq_state);
5106
5107 if (wq_attr_mask & IB_WQ_FLAGS) {
5108 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5109 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5110 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5111 mlx5_ib_dbg(dev, "VLAN offloads are not "
5112 "supported\n");
5113 err = -EOPNOTSUPP;
5114 goto out;
5115 }
5116 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5117 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5118 MLX5_SET(rqc, rqc, vsd,
5119 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5120 }
5121 }
5122
5123 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5124 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5125 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5126 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5127 MLX5_SET(rqc, rqc, counter_set_id,
5128 dev->port->cnts.set_id);
5129 } else
5130 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5131 dev->ib_dev.name);
5132 }
5133
5134 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5135 if (!err)
5136 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5137
5138 out:
5139 kvfree(in);
5140 return err;
5141 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git