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IB/mlx5: Add support for DEVX query UAR
[thirdparty/kernel/stable.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_ib.h"
39 #include "ib_rep.h"
40
41 /* not supported currently */
42 static int wq_signature;
43
44 enum {
45 MLX5_IB_ACK_REQ_FREQ = 8,
46 };
47
48 enum {
49 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
51 MLX5_IB_LINK_TYPE_IB = 0,
52 MLX5_IB_LINK_TYPE_ETH = 1
53 };
54
55 enum {
56 MLX5_IB_SQ_STRIDE = 6,
57 MLX5_IB_SQ_UMR_INLINE_THRESHOLD = 64,
58 };
59
60 static const u32 mlx5_ib_opcode[] = {
61 [IB_WR_SEND] = MLX5_OPCODE_SEND,
62 [IB_WR_LSO] = MLX5_OPCODE_LSO,
63 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
64 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
65 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
66 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
67 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
68 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
69 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
70 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
71 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
72 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
73 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
74 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
75 };
76
77 struct mlx5_wqe_eth_pad {
78 u8 rsvd0[16];
79 };
80
81 enum raw_qp_set_mask_map {
82 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
83 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
84 };
85
86 struct mlx5_modify_raw_qp_param {
87 u16 operation;
88
89 u32 set_mask; /* raw_qp_set_mask_map */
90
91 struct mlx5_rate_limit rl;
92
93 u8 rq_q_ctr_id;
94 };
95
96 static void get_cqs(enum ib_qp_type qp_type,
97 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
98 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
99
100 static int is_qp0(enum ib_qp_type qp_type)
101 {
102 return qp_type == IB_QPT_SMI;
103 }
104
105 static int is_sqp(enum ib_qp_type qp_type)
106 {
107 return is_qp0(qp_type) || is_qp1(qp_type);
108 }
109
110 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
111 {
112 return mlx5_buf_offset(&qp->buf, offset);
113 }
114
115 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
116 {
117 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
118 }
119
120 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
121 {
122 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
123 }
124
125 /**
126 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
127 *
128 * @qp: QP to copy from.
129 * @send: copy from the send queue when non-zero, use the receive queue
130 * otherwise.
131 * @wqe_index: index to start copying from. For send work queues, the
132 * wqe_index is in units of MLX5_SEND_WQE_BB.
133 * For receive work queue, it is the number of work queue
134 * element in the queue.
135 * @buffer: destination buffer.
136 * @length: maximum number of bytes to copy.
137 *
138 * Copies at least a single WQE, but may copy more data.
139 *
140 * Return: the number of bytes copied, or an error code.
141 */
142 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
143 void *buffer, u32 length,
144 struct mlx5_ib_qp_base *base)
145 {
146 struct ib_device *ibdev = qp->ibqp.device;
147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
148 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
149 size_t offset;
150 size_t wq_end;
151 struct ib_umem *umem = base->ubuffer.umem;
152 u32 first_copy_length;
153 int wqe_length;
154 int ret;
155
156 if (wq->wqe_cnt == 0) {
157 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
158 qp->ibqp.qp_type);
159 return -EINVAL;
160 }
161
162 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
163 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
164
165 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
166 return -EINVAL;
167
168 if (offset > umem->length ||
169 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
170 return -EINVAL;
171
172 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
173 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
174 if (ret)
175 return ret;
176
177 if (send) {
178 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
179 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
180
181 wqe_length = ds * MLX5_WQE_DS_UNITS;
182 } else {
183 wqe_length = 1 << wq->wqe_shift;
184 }
185
186 if (wqe_length <= first_copy_length)
187 return first_copy_length;
188
189 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
190 wqe_length - first_copy_length);
191 if (ret)
192 return ret;
193
194 return wqe_length;
195 }
196
197 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
198 {
199 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
200 struct ib_event event;
201
202 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
203 /* This event is only valid for trans_qps */
204 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
205 }
206
207 if (ibqp->event_handler) {
208 event.device = ibqp->device;
209 event.element.qp = ibqp;
210 switch (type) {
211 case MLX5_EVENT_TYPE_PATH_MIG:
212 event.event = IB_EVENT_PATH_MIG;
213 break;
214 case MLX5_EVENT_TYPE_COMM_EST:
215 event.event = IB_EVENT_COMM_EST;
216 break;
217 case MLX5_EVENT_TYPE_SQ_DRAINED:
218 event.event = IB_EVENT_SQ_DRAINED;
219 break;
220 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
221 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
222 break;
223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
224 event.event = IB_EVENT_QP_FATAL;
225 break;
226 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
227 event.event = IB_EVENT_PATH_MIG_ERR;
228 break;
229 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
230 event.event = IB_EVENT_QP_REQ_ERR;
231 break;
232 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
233 event.event = IB_EVENT_QP_ACCESS_ERR;
234 break;
235 default:
236 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
237 return;
238 }
239
240 ibqp->event_handler(&event, ibqp->qp_context);
241 }
242 }
243
244 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
245 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
246 {
247 int wqe_size;
248 int wq_size;
249
250 /* Sanity check RQ size before proceeding */
251 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
252 return -EINVAL;
253
254 if (!has_rq) {
255 qp->rq.max_gs = 0;
256 qp->rq.wqe_cnt = 0;
257 qp->rq.wqe_shift = 0;
258 cap->max_recv_wr = 0;
259 cap->max_recv_sge = 0;
260 } else {
261 if (ucmd) {
262 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
263 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
264 return -EINVAL;
265 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
266 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
267 return -EINVAL;
268 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
269 qp->rq.max_post = qp->rq.wqe_cnt;
270 } else {
271 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
272 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
273 wqe_size = roundup_pow_of_two(wqe_size);
274 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
275 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
276 qp->rq.wqe_cnt = wq_size / wqe_size;
277 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
278 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
279 wqe_size,
280 MLX5_CAP_GEN(dev->mdev,
281 max_wqe_sz_rq));
282 return -EINVAL;
283 }
284 qp->rq.wqe_shift = ilog2(wqe_size);
285 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
286 qp->rq.max_post = qp->rq.wqe_cnt;
287 }
288 }
289
290 return 0;
291 }
292
293 static int sq_overhead(struct ib_qp_init_attr *attr)
294 {
295 int size = 0;
296
297 switch (attr->qp_type) {
298 case IB_QPT_XRC_INI:
299 size += sizeof(struct mlx5_wqe_xrc_seg);
300 /* fall through */
301 case IB_QPT_RC:
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
303 max(sizeof(struct mlx5_wqe_atomic_seg) +
304 sizeof(struct mlx5_wqe_raddr_seg),
305 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
306 sizeof(struct mlx5_mkey_seg) +
307 MLX5_IB_SQ_UMR_INLINE_THRESHOLD /
308 MLX5_IB_UMR_OCTOWORD);
309 break;
310
311 case IB_QPT_XRC_TGT:
312 return 0;
313
314 case IB_QPT_UC:
315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 max(sizeof(struct mlx5_wqe_raddr_seg),
317 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
318 sizeof(struct mlx5_mkey_seg));
319 break;
320
321 case IB_QPT_UD:
322 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
323 size += sizeof(struct mlx5_wqe_eth_pad) +
324 sizeof(struct mlx5_wqe_eth_seg);
325 /* fall through */
326 case IB_QPT_SMI:
327 case MLX5_IB_QPT_HW_GSI:
328 size += sizeof(struct mlx5_wqe_ctrl_seg) +
329 sizeof(struct mlx5_wqe_datagram_seg);
330 break;
331
332 case MLX5_IB_QPT_REG_UMR:
333 size += sizeof(struct mlx5_wqe_ctrl_seg) +
334 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
335 sizeof(struct mlx5_mkey_seg);
336 break;
337
338 default:
339 return -EINVAL;
340 }
341
342 return size;
343 }
344
345 static int calc_send_wqe(struct ib_qp_init_attr *attr)
346 {
347 int inl_size = 0;
348 int size;
349
350 size = sq_overhead(attr);
351 if (size < 0)
352 return size;
353
354 if (attr->cap.max_inline_data) {
355 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
356 attr->cap.max_inline_data;
357 }
358
359 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
360 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
361 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
362 return MLX5_SIG_WQE_SIZE;
363 else
364 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
365 }
366
367 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
368 {
369 int max_sge;
370
371 if (attr->qp_type == IB_QPT_RC)
372 max_sge = (min_t(int, wqe_size, 512) -
373 sizeof(struct mlx5_wqe_ctrl_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else if (attr->qp_type == IB_QPT_XRC_INI)
377 max_sge = (min_t(int, wqe_size, 512) -
378 sizeof(struct mlx5_wqe_ctrl_seg) -
379 sizeof(struct mlx5_wqe_xrc_seg) -
380 sizeof(struct mlx5_wqe_raddr_seg)) /
381 sizeof(struct mlx5_wqe_data_seg);
382 else
383 max_sge = (wqe_size - sq_overhead(attr)) /
384 sizeof(struct mlx5_wqe_data_seg);
385
386 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
387 sizeof(struct mlx5_wqe_data_seg));
388 }
389
390 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
391 struct mlx5_ib_qp *qp)
392 {
393 int wqe_size;
394 int wq_size;
395
396 if (!attr->cap.max_send_wr)
397 return 0;
398
399 wqe_size = calc_send_wqe(attr);
400 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
401 if (wqe_size < 0)
402 return wqe_size;
403
404 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
405 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
406 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
407 return -EINVAL;
408 }
409
410 qp->max_inline_data = wqe_size - sq_overhead(attr) -
411 sizeof(struct mlx5_wqe_inline_seg);
412 attr->cap.max_inline_data = qp->max_inline_data;
413
414 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
415 qp->signature_en = true;
416
417 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
418 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
420 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
421 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
422 qp->sq.wqe_cnt,
423 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
424 return -ENOMEM;
425 }
426 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
427 qp->sq.max_gs = get_send_sge(attr, wqe_size);
428 if (qp->sq.max_gs < attr->cap.max_send_sge)
429 return -ENOMEM;
430
431 attr->cap.max_send_sge = qp->sq.max_gs;
432 qp->sq.max_post = wq_size / wqe_size;
433 attr->cap.max_send_wr = qp->sq.max_post;
434
435 return wq_size;
436 }
437
438 static int set_user_buf_size(struct mlx5_ib_dev *dev,
439 struct mlx5_ib_qp *qp,
440 struct mlx5_ib_create_qp *ucmd,
441 struct mlx5_ib_qp_base *base,
442 struct ib_qp_init_attr *attr)
443 {
444 int desc_sz = 1 << qp->sq.wqe_shift;
445
446 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
447 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
448 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
449 return -EINVAL;
450 }
451
452 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
453 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
454 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
455 return -EINVAL;
456 }
457
458 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
459
460 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
461 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
462 qp->sq.wqe_cnt,
463 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
464 return -EINVAL;
465 }
466
467 if (attr->qp_type == IB_QPT_RAW_PACKET ||
468 qp->flags & MLX5_IB_QP_UNDERLAY) {
469 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
470 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
471 } else {
472 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
473 (qp->sq.wqe_cnt << 6);
474 }
475
476 return 0;
477 }
478
479 static int qp_has_rq(struct ib_qp_init_attr *attr)
480 {
481 if (attr->qp_type == IB_QPT_XRC_INI ||
482 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
483 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
484 !attr->cap.max_recv_wr)
485 return 0;
486
487 return 1;
488 }
489
490 enum {
491 /* this is the first blue flame register in the array of bfregs assigned
492 * to a processes. Since we do not use it for blue flame but rather
493 * regular 64 bit doorbells, we do not need a lock for maintaiing
494 * "odd/even" order
495 */
496 NUM_NON_BLUE_FLAME_BFREGS = 1,
497 };
498
499 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
500 {
501 return get_num_static_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
502 }
503
504 static int num_med_bfreg(struct mlx5_ib_dev *dev,
505 struct mlx5_bfreg_info *bfregi)
506 {
507 int n;
508
509 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
510 NUM_NON_BLUE_FLAME_BFREGS;
511
512 return n >= 0 ? n : 0;
513 }
514
515 static int first_med_bfreg(struct mlx5_ib_dev *dev,
516 struct mlx5_bfreg_info *bfregi)
517 {
518 return num_med_bfreg(dev, bfregi) ? 1 : -ENOMEM;
519 }
520
521 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
522 struct mlx5_bfreg_info *bfregi)
523 {
524 int med;
525
526 med = num_med_bfreg(dev, bfregi);
527 return ++med;
528 }
529
530 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
531 struct mlx5_bfreg_info *bfregi)
532 {
533 int i;
534
535 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
536 if (!bfregi->count[i]) {
537 bfregi->count[i]++;
538 return i;
539 }
540 }
541
542 return -ENOMEM;
543 }
544
545 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
546 struct mlx5_bfreg_info *bfregi)
547 {
548 int minidx = first_med_bfreg(dev, bfregi);
549 int i;
550
551 if (minidx < 0)
552 return minidx;
553
554 for (i = minidx; i < first_hi_bfreg(dev, bfregi); i++) {
555 if (bfregi->count[i] < bfregi->count[minidx])
556 minidx = i;
557 if (!bfregi->count[minidx])
558 break;
559 }
560
561 bfregi->count[minidx]++;
562 return minidx;
563 }
564
565 static int alloc_bfreg(struct mlx5_ib_dev *dev,
566 struct mlx5_bfreg_info *bfregi,
567 enum mlx5_ib_latency_class lat)
568 {
569 int bfregn = -EINVAL;
570
571 mutex_lock(&bfregi->lock);
572 switch (lat) {
573 case MLX5_IB_LATENCY_CLASS_LOW:
574 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
575 bfregn = 0;
576 bfregi->count[bfregn]++;
577 break;
578
579 case MLX5_IB_LATENCY_CLASS_MEDIUM:
580 if (bfregi->ver < 2)
581 bfregn = -ENOMEM;
582 else
583 bfregn = alloc_med_class_bfreg(dev, bfregi);
584 break;
585
586 case MLX5_IB_LATENCY_CLASS_HIGH:
587 if (bfregi->ver < 2)
588 bfregn = -ENOMEM;
589 else
590 bfregn = alloc_high_class_bfreg(dev, bfregi);
591 break;
592 }
593 mutex_unlock(&bfregi->lock);
594
595 return bfregn;
596 }
597
598 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
599 {
600 mutex_lock(&bfregi->lock);
601 bfregi->count[bfregn]--;
602 mutex_unlock(&bfregi->lock);
603 }
604
605 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
606 {
607 switch (state) {
608 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
609 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
610 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
611 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
612 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
613 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
614 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
615 default: return -1;
616 }
617 }
618
619 static int to_mlx5_st(enum ib_qp_type type)
620 {
621 switch (type) {
622 case IB_QPT_RC: return MLX5_QP_ST_RC;
623 case IB_QPT_UC: return MLX5_QP_ST_UC;
624 case IB_QPT_UD: return MLX5_QP_ST_UD;
625 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
626 case IB_QPT_XRC_INI:
627 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
628 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
629 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
630 case MLX5_IB_QPT_DCI: return MLX5_QP_ST_DCI;
631 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
632 case IB_QPT_RAW_PACKET:
633 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
634 case IB_QPT_MAX:
635 default: return -EINVAL;
636 }
637 }
638
639 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
640 struct mlx5_ib_cq *recv_cq);
641 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
642 struct mlx5_ib_cq *recv_cq);
643
644 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
645 struct mlx5_bfreg_info *bfregi, int bfregn,
646 bool dyn_bfreg)
647 {
648 int bfregs_per_sys_page;
649 int index_of_sys_page;
650 int offset;
651
652 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
653 MLX5_NON_FP_BFREGS_PER_UAR;
654 index_of_sys_page = bfregn / bfregs_per_sys_page;
655
656 if (index_of_sys_page >= bfregi->num_sys_pages)
657 return -EINVAL;
658
659 if (dyn_bfreg) {
660 index_of_sys_page += bfregi->num_static_sys_pages;
661 if (bfregn > bfregi->num_dyn_bfregs ||
662 bfregi->sys_pages[index_of_sys_page] == MLX5_IB_INVALID_UAR_INDEX) {
663 mlx5_ib_dbg(dev, "Invalid dynamic uar index\n");
664 return -EINVAL;
665 }
666 }
667
668 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
669 return bfregi->sys_pages[index_of_sys_page] + offset;
670 }
671
672 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
673 struct ib_pd *pd,
674 unsigned long addr, size_t size,
675 struct ib_umem **umem,
676 int *npages, int *page_shift, int *ncont,
677 u32 *offset)
678 {
679 int err;
680
681 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
682 if (IS_ERR(*umem)) {
683 mlx5_ib_dbg(dev, "umem_get failed\n");
684 return PTR_ERR(*umem);
685 }
686
687 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
688
689 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
690 if (err) {
691 mlx5_ib_warn(dev, "bad offset\n");
692 goto err_umem;
693 }
694
695 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
696 addr, size, *npages, *page_shift, *ncont, *offset);
697
698 return 0;
699
700 err_umem:
701 ib_umem_release(*umem);
702 *umem = NULL;
703
704 return err;
705 }
706
707 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
708 struct mlx5_ib_rwq *rwq)
709 {
710 struct mlx5_ib_ucontext *context;
711
712 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
713 atomic_dec(&dev->delay_drop.rqs_cnt);
714
715 context = to_mucontext(pd->uobject->context);
716 mlx5_ib_db_unmap_user(context, &rwq->db);
717 if (rwq->umem)
718 ib_umem_release(rwq->umem);
719 }
720
721 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
722 struct mlx5_ib_rwq *rwq,
723 struct mlx5_ib_create_wq *ucmd)
724 {
725 struct mlx5_ib_ucontext *context;
726 int page_shift = 0;
727 int npages;
728 u32 offset = 0;
729 int ncont = 0;
730 int err;
731
732 if (!ucmd->buf_addr)
733 return -EINVAL;
734
735 context = to_mucontext(pd->uobject->context);
736 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
737 rwq->buf_size, 0, 0);
738 if (IS_ERR(rwq->umem)) {
739 mlx5_ib_dbg(dev, "umem_get failed\n");
740 err = PTR_ERR(rwq->umem);
741 return err;
742 }
743
744 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
745 &ncont, NULL);
746 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
747 &rwq->rq_page_offset);
748 if (err) {
749 mlx5_ib_warn(dev, "bad offset\n");
750 goto err_umem;
751 }
752
753 rwq->rq_num_pas = ncont;
754 rwq->page_shift = page_shift;
755 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
756 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
757
758 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
759 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
760 npages, page_shift, ncont, offset);
761
762 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
763 if (err) {
764 mlx5_ib_dbg(dev, "map failed\n");
765 goto err_umem;
766 }
767
768 rwq->create_type = MLX5_WQ_USER;
769 return 0;
770
771 err_umem:
772 ib_umem_release(rwq->umem);
773 return err;
774 }
775
776 static int adjust_bfregn(struct mlx5_ib_dev *dev,
777 struct mlx5_bfreg_info *bfregi, int bfregn)
778 {
779 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
780 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
781 }
782
783 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
784 struct mlx5_ib_qp *qp, struct ib_udata *udata,
785 struct ib_qp_init_attr *attr,
786 u32 **in,
787 struct mlx5_ib_create_qp_resp *resp, int *inlen,
788 struct mlx5_ib_qp_base *base)
789 {
790 struct mlx5_ib_ucontext *context;
791 struct mlx5_ib_create_qp ucmd;
792 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
793 int page_shift = 0;
794 int uar_index = 0;
795 int npages;
796 u32 offset = 0;
797 int bfregn;
798 int ncont = 0;
799 __be64 *pas;
800 void *qpc;
801 int err;
802
803 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
804 if (err) {
805 mlx5_ib_dbg(dev, "copy failed\n");
806 return err;
807 }
808
809 context = to_mucontext(pd->uobject->context);
810 if (ucmd.flags & MLX5_QP_FLAG_BFREG_INDEX) {
811 uar_index = bfregn_to_uar_index(dev, &context->bfregi,
812 ucmd.bfreg_index, true);
813 if (uar_index < 0)
814 return uar_index;
815
816 bfregn = MLX5_IB_INVALID_BFREG;
817 } else if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL) {
818 /*
819 * TBD: should come from the verbs when we have the API
820 */
821 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
822 bfregn = MLX5_CROSS_CHANNEL_BFREG;
823 }
824 else {
825 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
826 if (bfregn < 0) {
827 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
828 mlx5_ib_dbg(dev, "reverting to medium latency\n");
829 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
830 if (bfregn < 0) {
831 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
832 mlx5_ib_dbg(dev, "reverting to high latency\n");
833 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
834 if (bfregn < 0) {
835 mlx5_ib_warn(dev, "bfreg allocation failed\n");
836 return bfregn;
837 }
838 }
839 }
840 }
841
842 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
843 if (bfregn != MLX5_IB_INVALID_BFREG)
844 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn,
845 false);
846
847 qp->rq.offset = 0;
848 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
849 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
850
851 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
852 if (err)
853 goto err_bfreg;
854
855 if (ucmd.buf_addr && ubuffer->buf_size) {
856 ubuffer->buf_addr = ucmd.buf_addr;
857 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
858 ubuffer->buf_size,
859 &ubuffer->umem, &npages, &page_shift,
860 &ncont, &offset);
861 if (err)
862 goto err_bfreg;
863 } else {
864 ubuffer->umem = NULL;
865 }
866
867 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
868 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
869 *in = kvzalloc(*inlen, GFP_KERNEL);
870 if (!*in) {
871 err = -ENOMEM;
872 goto err_umem;
873 }
874
875 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
876 if (ubuffer->umem)
877 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
878
879 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
880
881 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
882 MLX5_SET(qpc, qpc, page_offset, offset);
883
884 MLX5_SET(qpc, qpc, uar_page, uar_index);
885 if (bfregn != MLX5_IB_INVALID_BFREG)
886 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
887 else
888 resp->bfreg_index = MLX5_IB_INVALID_BFREG;
889 qp->bfregn = bfregn;
890
891 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
892 if (err) {
893 mlx5_ib_dbg(dev, "map failed\n");
894 goto err_free;
895 }
896
897 err = ib_copy_to_udata(udata, resp, min(udata->outlen, sizeof(*resp)));
898 if (err) {
899 mlx5_ib_dbg(dev, "copy failed\n");
900 goto err_unmap;
901 }
902 qp->create_type = MLX5_QP_USER;
903
904 return 0;
905
906 err_unmap:
907 mlx5_ib_db_unmap_user(context, &qp->db);
908
909 err_free:
910 kvfree(*in);
911
912 err_umem:
913 if (ubuffer->umem)
914 ib_umem_release(ubuffer->umem);
915
916 err_bfreg:
917 if (bfregn != MLX5_IB_INVALID_BFREG)
918 mlx5_ib_free_bfreg(dev, &context->bfregi, bfregn);
919 return err;
920 }
921
922 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
923 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
924 {
925 struct mlx5_ib_ucontext *context;
926
927 context = to_mucontext(pd->uobject->context);
928 mlx5_ib_db_unmap_user(context, &qp->db);
929 if (base->ubuffer.umem)
930 ib_umem_release(base->ubuffer.umem);
931
932 /*
933 * Free only the BFREGs which are handled by the kernel.
934 * BFREGs of UARs allocated dynamically are handled by user.
935 */
936 if (qp->bfregn != MLX5_IB_INVALID_BFREG)
937 mlx5_ib_free_bfreg(dev, &context->bfregi, qp->bfregn);
938 }
939
940 static int create_kernel_qp(struct mlx5_ib_dev *dev,
941 struct ib_qp_init_attr *init_attr,
942 struct mlx5_ib_qp *qp,
943 u32 **in, int *inlen,
944 struct mlx5_ib_qp_base *base)
945 {
946 int uar_index;
947 void *qpc;
948 int err;
949
950 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
951 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
952 IB_QP_CREATE_IPOIB_UD_LSO |
953 IB_QP_CREATE_NETIF_QP |
954 mlx5_ib_create_qp_sqpn_qp1()))
955 return -EINVAL;
956
957 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
958 qp->bf.bfreg = &dev->fp_bfreg;
959 else
960 qp->bf.bfreg = &dev->bfreg;
961
962 /* We need to divide by two since each register is comprised of
963 * two buffers of identical size, namely odd and even
964 */
965 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
966 uar_index = qp->bf.bfreg->index;
967
968 err = calc_sq_size(dev, init_attr, qp);
969 if (err < 0) {
970 mlx5_ib_dbg(dev, "err %d\n", err);
971 return err;
972 }
973
974 qp->rq.offset = 0;
975 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
976 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
977
978 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
979 if (err) {
980 mlx5_ib_dbg(dev, "err %d\n", err);
981 return err;
982 }
983
984 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
985 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
986 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
987 *in = kvzalloc(*inlen, GFP_KERNEL);
988 if (!*in) {
989 err = -ENOMEM;
990 goto err_buf;
991 }
992
993 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
994 MLX5_SET(qpc, qpc, uar_page, uar_index);
995 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
996
997 /* Set "fast registration enabled" for all kernel QPs */
998 MLX5_SET(qpc, qpc, fre, 1);
999 MLX5_SET(qpc, qpc, rlky, 1);
1000
1001 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
1002 MLX5_SET(qpc, qpc, deth_sqpn, 1);
1003 qp->flags |= MLX5_IB_QP_SQPN_QP1;
1004 }
1005
1006 mlx5_fill_page_array(&qp->buf,
1007 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
1008
1009 err = mlx5_db_alloc(dev->mdev, &qp->db);
1010 if (err) {
1011 mlx5_ib_dbg(dev, "err %d\n", err);
1012 goto err_free;
1013 }
1014
1015 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1016 sizeof(*qp->sq.wrid), GFP_KERNEL);
1017 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
1018 sizeof(*qp->sq.wr_data), GFP_KERNEL);
1019 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1020 sizeof(*qp->rq.wrid), GFP_KERNEL);
1021 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
1022 sizeof(*qp->sq.w_list), GFP_KERNEL);
1023 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
1024 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
1025
1026 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
1027 !qp->sq.w_list || !qp->sq.wqe_head) {
1028 err = -ENOMEM;
1029 goto err_wrid;
1030 }
1031 qp->create_type = MLX5_QP_KERNEL;
1032
1033 return 0;
1034
1035 err_wrid:
1036 kvfree(qp->sq.wqe_head);
1037 kvfree(qp->sq.w_list);
1038 kvfree(qp->sq.wrid);
1039 kvfree(qp->sq.wr_data);
1040 kvfree(qp->rq.wrid);
1041 mlx5_db_free(dev->mdev, &qp->db);
1042
1043 err_free:
1044 kvfree(*in);
1045
1046 err_buf:
1047 mlx5_buf_free(dev->mdev, &qp->buf);
1048 return err;
1049 }
1050
1051 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1052 {
1053 kvfree(qp->sq.wqe_head);
1054 kvfree(qp->sq.w_list);
1055 kvfree(qp->sq.wrid);
1056 kvfree(qp->sq.wr_data);
1057 kvfree(qp->rq.wrid);
1058 mlx5_db_free(dev->mdev, &qp->db);
1059 mlx5_buf_free(dev->mdev, &qp->buf);
1060 }
1061
1062 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1063 {
1064 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1065 (attr->qp_type == MLX5_IB_QPT_DCI) ||
1066 (attr->qp_type == IB_QPT_XRC_INI))
1067 return MLX5_SRQ_RQ;
1068 else if (!qp->has_rq)
1069 return MLX5_ZERO_LEN_RQ;
1070 else
1071 return MLX5_NON_ZERO_RQ;
1072 }
1073
1074 static int is_connected(enum ib_qp_type qp_type)
1075 {
1076 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1077 return 1;
1078
1079 return 0;
1080 }
1081
1082 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1083 struct mlx5_ib_qp *qp,
1084 struct mlx5_ib_sq *sq, u32 tdn)
1085 {
1086 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1087 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1088
1089 MLX5_SET(tisc, tisc, transport_domain, tdn);
1090 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1091 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1092
1093 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1094 }
1095
1096 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1097 struct mlx5_ib_sq *sq)
1098 {
1099 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1100 }
1101
1102 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev *dev,
1103 struct mlx5_ib_sq *sq)
1104 {
1105 if (sq->flow_rule)
1106 mlx5_del_flow_rules(sq->flow_rule);
1107 }
1108
1109 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1110 struct mlx5_ib_sq *sq, void *qpin,
1111 struct ib_pd *pd)
1112 {
1113 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1114 __be64 *pas;
1115 void *in;
1116 void *sqc;
1117 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1118 void *wq;
1119 int inlen;
1120 int err;
1121 int page_shift = 0;
1122 int npages;
1123 int ncont = 0;
1124 u32 offset = 0;
1125
1126 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1127 &sq->ubuffer.umem, &npages, &page_shift,
1128 &ncont, &offset);
1129 if (err)
1130 return err;
1131
1132 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1133 in = kvzalloc(inlen, GFP_KERNEL);
1134 if (!in) {
1135 err = -ENOMEM;
1136 goto err_umem;
1137 }
1138
1139 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1140 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1141 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1142 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1143 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1144 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1145 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1146 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1147 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1148 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1149 MLX5_CAP_ETH(dev->mdev, swp))
1150 MLX5_SET(sqc, sqc, allow_swp, 1);
1151
1152 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1153 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1154 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1155 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1156 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1157 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1158 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1159 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1160 MLX5_SET(wq, wq, page_offset, offset);
1161
1162 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1163 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1164
1165 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1166
1167 kvfree(in);
1168
1169 if (err)
1170 goto err_umem;
1171
1172 err = create_flow_rule_vport_sq(dev, sq);
1173 if (err)
1174 goto err_flow;
1175
1176 return 0;
1177
1178 err_flow:
1179 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1180
1181 err_umem:
1182 ib_umem_release(sq->ubuffer.umem);
1183 sq->ubuffer.umem = NULL;
1184
1185 return err;
1186 }
1187
1188 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1189 struct mlx5_ib_sq *sq)
1190 {
1191 destroy_flow_rule_vport_sq(dev, sq);
1192 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1193 ib_umem_release(sq->ubuffer.umem);
1194 }
1195
1196 static size_t get_rq_pas_size(void *qpc)
1197 {
1198 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1199 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1200 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1201 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1202 u32 po_quanta = 1 << (log_page_size - 6);
1203 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1204 u32 page_size = 1 << log_page_size;
1205 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1206 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1207
1208 return rq_num_pas * sizeof(u64);
1209 }
1210
1211 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1212 struct mlx5_ib_rq *rq, void *qpin,
1213 size_t qpinlen)
1214 {
1215 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1216 __be64 *pas;
1217 __be64 *qp_pas;
1218 void *in;
1219 void *rqc;
1220 void *wq;
1221 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1222 size_t rq_pas_size = get_rq_pas_size(qpc);
1223 size_t inlen;
1224 int err;
1225
1226 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1227 return -EINVAL;
1228
1229 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1230 in = kvzalloc(inlen, GFP_KERNEL);
1231 if (!in)
1232 return -ENOMEM;
1233
1234 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1235 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1236 MLX5_SET(rqc, rqc, vsd, 1);
1237 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1238 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1239 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1240 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1241 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1242
1243 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1244 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1245
1246 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1247 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1248 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1249 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1250 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1251 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1252 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1253 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1254 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1255 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1256
1257 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1258 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1259 memcpy(pas, qp_pas, rq_pas_size);
1260
1261 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1262
1263 kvfree(in);
1264
1265 return err;
1266 }
1267
1268 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1269 struct mlx5_ib_rq *rq)
1270 {
1271 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1272 }
1273
1274 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1275 {
1276 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1277 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1278 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1279 }
1280
1281 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1282 struct mlx5_ib_rq *rq, u32 tdn,
1283 bool tunnel_offload_en)
1284 {
1285 u32 *in;
1286 void *tirc;
1287 int inlen;
1288 int err;
1289
1290 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1291 in = kvzalloc(inlen, GFP_KERNEL);
1292 if (!in)
1293 return -ENOMEM;
1294
1295 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1296 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1297 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1298 MLX5_SET(tirc, tirc, transport_domain, tdn);
1299 if (tunnel_offload_en)
1300 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1301
1302 if (dev->rep)
1303 MLX5_SET(tirc, tirc, self_lb_block,
1304 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1305
1306 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1307
1308 kvfree(in);
1309
1310 return err;
1311 }
1312
1313 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1314 struct mlx5_ib_rq *rq)
1315 {
1316 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1317 }
1318
1319 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1320 u32 *in, size_t inlen,
1321 struct ib_pd *pd)
1322 {
1323 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1324 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1325 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1326 struct ib_uobject *uobj = pd->uobject;
1327 struct ib_ucontext *ucontext = uobj->context;
1328 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1329 int err;
1330 u32 tdn = mucontext->tdn;
1331
1332 if (qp->sq.wqe_cnt) {
1333 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1334 if (err)
1335 return err;
1336
1337 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1338 if (err)
1339 goto err_destroy_tis;
1340
1341 sq->base.container_mibqp = qp;
1342 sq->base.mqp.event = mlx5_ib_qp_event;
1343 }
1344
1345 if (qp->rq.wqe_cnt) {
1346 rq->base.container_mibqp = qp;
1347
1348 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1349 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1350 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1351 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1352 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1353 if (err)
1354 goto err_destroy_sq;
1355
1356
1357 err = create_raw_packet_qp_tir(dev, rq, tdn,
1358 qp->tunnel_offload_en);
1359 if (err)
1360 goto err_destroy_rq;
1361 }
1362
1363 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1364 rq->base.mqp.qpn;
1365
1366 return 0;
1367
1368 err_destroy_rq:
1369 destroy_raw_packet_qp_rq(dev, rq);
1370 err_destroy_sq:
1371 if (!qp->sq.wqe_cnt)
1372 return err;
1373 destroy_raw_packet_qp_sq(dev, sq);
1374 err_destroy_tis:
1375 destroy_raw_packet_qp_tis(dev, sq);
1376
1377 return err;
1378 }
1379
1380 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1381 struct mlx5_ib_qp *qp)
1382 {
1383 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1384 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1385 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1386
1387 if (qp->rq.wqe_cnt) {
1388 destroy_raw_packet_qp_tir(dev, rq);
1389 destroy_raw_packet_qp_rq(dev, rq);
1390 }
1391
1392 if (qp->sq.wqe_cnt) {
1393 destroy_raw_packet_qp_sq(dev, sq);
1394 destroy_raw_packet_qp_tis(dev, sq);
1395 }
1396 }
1397
1398 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1399 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1400 {
1401 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1402 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1403
1404 sq->sq = &qp->sq;
1405 rq->rq = &qp->rq;
1406 sq->doorbell = &qp->db;
1407 rq->doorbell = &qp->db;
1408 }
1409
1410 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1411 {
1412 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1413 }
1414
1415 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1416 struct ib_pd *pd,
1417 struct ib_qp_init_attr *init_attr,
1418 struct ib_udata *udata)
1419 {
1420 struct ib_uobject *uobj = pd->uobject;
1421 struct ib_ucontext *ucontext = uobj->context;
1422 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1423 struct mlx5_ib_create_qp_resp resp = {};
1424 int inlen;
1425 int err;
1426 u32 *in;
1427 void *tirc;
1428 void *hfso;
1429 u32 selected_fields = 0;
1430 u32 outer_l4;
1431 size_t min_resp_len;
1432 u32 tdn = mucontext->tdn;
1433 struct mlx5_ib_create_qp_rss ucmd = {};
1434 size_t required_cmd_sz;
1435
1436 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1437 return -EOPNOTSUPP;
1438
1439 if (init_attr->create_flags || init_attr->send_cq)
1440 return -EINVAL;
1441
1442 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1443 if (udata->outlen < min_resp_len)
1444 return -EINVAL;
1445
1446 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1447 if (udata->inlen < required_cmd_sz) {
1448 mlx5_ib_dbg(dev, "invalid inlen\n");
1449 return -EINVAL;
1450 }
1451
1452 if (udata->inlen > sizeof(ucmd) &&
1453 !ib_is_udata_cleared(udata, sizeof(ucmd),
1454 udata->inlen - sizeof(ucmd))) {
1455 mlx5_ib_dbg(dev, "inlen is not supported\n");
1456 return -EOPNOTSUPP;
1457 }
1458
1459 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1460 mlx5_ib_dbg(dev, "copy failed\n");
1461 return -EFAULT;
1462 }
1463
1464 if (ucmd.comp_mask) {
1465 mlx5_ib_dbg(dev, "invalid comp mask\n");
1466 return -EOPNOTSUPP;
1467 }
1468
1469 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1470 mlx5_ib_dbg(dev, "invalid flags\n");
1471 return -EOPNOTSUPP;
1472 }
1473
1474 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1475 !tunnel_offload_supported(dev->mdev)) {
1476 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1477 return -EOPNOTSUPP;
1478 }
1479
1480 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1481 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1482 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1483 return -EOPNOTSUPP;
1484 }
1485
1486 err = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp)));
1487 if (err) {
1488 mlx5_ib_dbg(dev, "copy failed\n");
1489 return -EINVAL;
1490 }
1491
1492 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1493 in = kvzalloc(inlen, GFP_KERNEL);
1494 if (!in)
1495 return -ENOMEM;
1496
1497 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1498 MLX5_SET(tirc, tirc, disp_type,
1499 MLX5_TIRC_DISP_TYPE_INDIRECT);
1500 MLX5_SET(tirc, tirc, indirect_table,
1501 init_attr->rwq_ind_tbl->ind_tbl_num);
1502 MLX5_SET(tirc, tirc, transport_domain, tdn);
1503
1504 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1505
1506 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1507 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1508
1509 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1510 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1511 else
1512 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1513
1514 switch (ucmd.rx_hash_function) {
1515 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1516 {
1517 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1518 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1519
1520 if (len != ucmd.rx_key_len) {
1521 err = -EINVAL;
1522 goto err;
1523 }
1524
1525 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1526 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1527 memcpy(rss_key, ucmd.rx_hash_key, len);
1528 break;
1529 }
1530 default:
1531 err = -EOPNOTSUPP;
1532 goto err;
1533 }
1534
1535 if (!ucmd.rx_hash_fields_mask) {
1536 /* special case when this TIR serves as steering entry without hashing */
1537 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1538 goto create_tir;
1539 err = -EINVAL;
1540 goto err;
1541 }
1542
1543 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1544 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1545 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1546 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1547 err = -EINVAL;
1548 goto err;
1549 }
1550
1551 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1552 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1553 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1554 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1555 MLX5_L3_PROT_TYPE_IPV4);
1556 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1557 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1558 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1559 MLX5_L3_PROT_TYPE_IPV6);
1560
1561 outer_l4 = ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1562 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) << 0 |
1563 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1564 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP)) << 1 |
1565 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI) << 2;
1566
1567 /* Check that only one l4 protocol is set */
1568 if (outer_l4 & (outer_l4 - 1)) {
1569 err = -EINVAL;
1570 goto err;
1571 }
1572
1573 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1574 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1575 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1576 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1577 MLX5_L4_PROT_TYPE_TCP);
1578 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1579 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1580 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1581 MLX5_L4_PROT_TYPE_UDP);
1582
1583 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1584 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1585 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1586
1587 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1588 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1589 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1590
1591 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1592 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1593 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1594
1595 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1596 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1597 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1598
1599 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_IPSEC_SPI)
1600 selected_fields |= MLX5_HASH_FIELD_SEL_IPSEC_SPI;
1601
1602 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1603
1604 create_tir:
1605 if (dev->rep)
1606 MLX5_SET(tirc, tirc, self_lb_block,
1607 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
1608
1609 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1610
1611 if (err)
1612 goto err;
1613
1614 kvfree(in);
1615 /* qpn is reserved for that QP */
1616 qp->trans_qp.base.mqp.qpn = 0;
1617 qp->flags |= MLX5_IB_QP_RSS;
1618 return 0;
1619
1620 err:
1621 kvfree(in);
1622 return err;
1623 }
1624
1625 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1626 struct ib_qp_init_attr *init_attr,
1627 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1628 {
1629 struct mlx5_ib_resources *devr = &dev->devr;
1630 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1631 struct mlx5_core_dev *mdev = dev->mdev;
1632 struct mlx5_ib_create_qp_resp resp;
1633 struct mlx5_ib_cq *send_cq;
1634 struct mlx5_ib_cq *recv_cq;
1635 unsigned long flags;
1636 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1637 struct mlx5_ib_create_qp ucmd;
1638 struct mlx5_ib_qp_base *base;
1639 int mlx5_st;
1640 void *qpc;
1641 u32 *in;
1642 int err;
1643
1644 mutex_init(&qp->mutex);
1645 spin_lock_init(&qp->sq.lock);
1646 spin_lock_init(&qp->rq.lock);
1647
1648 mlx5_st = to_mlx5_st(init_attr->qp_type);
1649 if (mlx5_st < 0)
1650 return -EINVAL;
1651
1652 if (init_attr->rwq_ind_tbl) {
1653 if (!udata)
1654 return -ENOSYS;
1655
1656 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1657 return err;
1658 }
1659
1660 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1661 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1662 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1663 return -EINVAL;
1664 } else {
1665 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1666 }
1667 }
1668
1669 if (init_attr->create_flags &
1670 (IB_QP_CREATE_CROSS_CHANNEL |
1671 IB_QP_CREATE_MANAGED_SEND |
1672 IB_QP_CREATE_MANAGED_RECV)) {
1673 if (!MLX5_CAP_GEN(mdev, cd)) {
1674 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1675 return -EINVAL;
1676 }
1677 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1678 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1679 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1680 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1681 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1682 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1683 }
1684
1685 if (init_attr->qp_type == IB_QPT_UD &&
1686 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1687 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1688 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1689 return -EOPNOTSUPP;
1690 }
1691
1692 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1693 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1694 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1695 return -EOPNOTSUPP;
1696 }
1697 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1698 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1699 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1700 return -EOPNOTSUPP;
1701 }
1702 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1703 }
1704
1705 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1706 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1707
1708 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1709 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1710 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1711 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1712 return -EOPNOTSUPP;
1713 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1714 }
1715
1716 if (pd && pd->uobject) {
1717 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1718 mlx5_ib_dbg(dev, "copy failed\n");
1719 return -EFAULT;
1720 }
1721
1722 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1723 &ucmd, udata->inlen, &uidx);
1724 if (err)
1725 return err;
1726
1727 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1728 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1729 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1730 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1731 !tunnel_offload_supported(mdev)) {
1732 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1733 return -EOPNOTSUPP;
1734 }
1735 qp->tunnel_offload_en = true;
1736 }
1737
1738 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1739 if (init_attr->qp_type != IB_QPT_UD ||
1740 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1741 MLX5_CAP_PORT_TYPE_IB) ||
1742 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1743 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1744 return -EOPNOTSUPP;
1745 }
1746
1747 qp->flags |= MLX5_IB_QP_UNDERLAY;
1748 qp->underlay_qpn = init_attr->source_qpn;
1749 }
1750 } else {
1751 qp->wq_sig = !!wq_signature;
1752 }
1753
1754 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1755 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1756 &qp->raw_packet_qp.rq.base :
1757 &qp->trans_qp.base;
1758
1759 qp->has_rq = qp_has_rq(init_attr);
1760 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1761 qp, (pd && pd->uobject) ? &ucmd : NULL);
1762 if (err) {
1763 mlx5_ib_dbg(dev, "err %d\n", err);
1764 return err;
1765 }
1766
1767 if (pd) {
1768 if (pd->uobject) {
1769 __u32 max_wqes =
1770 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1771 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1772 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1773 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1774 mlx5_ib_dbg(dev, "invalid rq params\n");
1775 return -EINVAL;
1776 }
1777 if (ucmd.sq_wqe_count > max_wqes) {
1778 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1779 ucmd.sq_wqe_count, max_wqes);
1780 return -EINVAL;
1781 }
1782 if (init_attr->create_flags &
1783 mlx5_ib_create_qp_sqpn_qp1()) {
1784 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1785 return -EINVAL;
1786 }
1787 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1788 &resp, &inlen, base);
1789 if (err)
1790 mlx5_ib_dbg(dev, "err %d\n", err);
1791 } else {
1792 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1793 base);
1794 if (err)
1795 mlx5_ib_dbg(dev, "err %d\n", err);
1796 }
1797
1798 if (err)
1799 return err;
1800 } else {
1801 in = kvzalloc(inlen, GFP_KERNEL);
1802 if (!in)
1803 return -ENOMEM;
1804
1805 qp->create_type = MLX5_QP_EMPTY;
1806 }
1807
1808 if (is_sqp(init_attr->qp_type))
1809 qp->port = init_attr->port_num;
1810
1811 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1812
1813 MLX5_SET(qpc, qpc, st, mlx5_st);
1814 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1815
1816 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1817 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1818 else
1819 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1820
1821
1822 if (qp->wq_sig)
1823 MLX5_SET(qpc, qpc, wq_signature, 1);
1824
1825 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1826 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1827
1828 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1829 MLX5_SET(qpc, qpc, cd_master, 1);
1830 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1831 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1832 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1833 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1834
1835 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1836 int rcqe_sz;
1837 int scqe_sz;
1838
1839 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1840 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1841
1842 if (rcqe_sz == 128)
1843 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1844 else
1845 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1846
1847 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1848 if (scqe_sz == 128)
1849 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1850 else
1851 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1852 }
1853 }
1854
1855 if (qp->rq.wqe_cnt) {
1856 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1857 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1858 }
1859
1860 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1861
1862 if (qp->sq.wqe_cnt) {
1863 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1864 } else {
1865 MLX5_SET(qpc, qpc, no_sq, 1);
1866 if (init_attr->srq &&
1867 init_attr->srq->srq_type == IB_SRQT_TM)
1868 MLX5_SET(qpc, qpc, offload_type,
1869 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1870 }
1871
1872 /* Set default resources */
1873 switch (init_attr->qp_type) {
1874 case IB_QPT_XRC_TGT:
1875 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1876 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1877 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1878 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1879 break;
1880 case IB_QPT_XRC_INI:
1881 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1882 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1883 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1884 break;
1885 default:
1886 if (init_attr->srq) {
1887 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1888 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1889 } else {
1890 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1891 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1892 }
1893 }
1894
1895 if (init_attr->send_cq)
1896 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1897
1898 if (init_attr->recv_cq)
1899 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1900
1901 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1902
1903 /* 0xffffff means we ask to work with cqe version 0 */
1904 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1905 MLX5_SET(qpc, qpc, user_index, uidx);
1906
1907 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1908 if (init_attr->qp_type == IB_QPT_UD &&
1909 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1910 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1911 qp->flags |= MLX5_IB_QP_LSO;
1912 }
1913
1914 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1915 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1916 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1917 err = -EOPNOTSUPP;
1918 goto err;
1919 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1920 MLX5_SET(qpc, qpc, end_padding_mode,
1921 MLX5_WQ_END_PAD_MODE_ALIGN);
1922 } else {
1923 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1924 }
1925 }
1926
1927 if (inlen < 0) {
1928 err = -EINVAL;
1929 goto err;
1930 }
1931
1932 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1933 qp->flags & MLX5_IB_QP_UNDERLAY) {
1934 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1935 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1936 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1937 } else {
1938 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1939 }
1940
1941 if (err) {
1942 mlx5_ib_dbg(dev, "create qp failed\n");
1943 goto err_create;
1944 }
1945
1946 kvfree(in);
1947
1948 base->container_mibqp = qp;
1949 base->mqp.event = mlx5_ib_qp_event;
1950
1951 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1952 &send_cq, &recv_cq);
1953 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1954 mlx5_ib_lock_cqs(send_cq, recv_cq);
1955 /* Maintain device to QPs access, needed for further handling via reset
1956 * flow
1957 */
1958 list_add_tail(&qp->qps_list, &dev->qp_list);
1959 /* Maintain CQ to QPs access, needed for further handling via reset flow
1960 */
1961 if (send_cq)
1962 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1963 if (recv_cq)
1964 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1965 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1966 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1967
1968 return 0;
1969
1970 err_create:
1971 if (qp->create_type == MLX5_QP_USER)
1972 destroy_qp_user(dev, pd, qp, base);
1973 else if (qp->create_type == MLX5_QP_KERNEL)
1974 destroy_qp_kernel(dev, qp);
1975
1976 err:
1977 kvfree(in);
1978 return err;
1979 }
1980
1981 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1982 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1983 {
1984 if (send_cq) {
1985 if (recv_cq) {
1986 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1987 spin_lock(&send_cq->lock);
1988 spin_lock_nested(&recv_cq->lock,
1989 SINGLE_DEPTH_NESTING);
1990 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1991 spin_lock(&send_cq->lock);
1992 __acquire(&recv_cq->lock);
1993 } else {
1994 spin_lock(&recv_cq->lock);
1995 spin_lock_nested(&send_cq->lock,
1996 SINGLE_DEPTH_NESTING);
1997 }
1998 } else {
1999 spin_lock(&send_cq->lock);
2000 __acquire(&recv_cq->lock);
2001 }
2002 } else if (recv_cq) {
2003 spin_lock(&recv_cq->lock);
2004 __acquire(&send_cq->lock);
2005 } else {
2006 __acquire(&send_cq->lock);
2007 __acquire(&recv_cq->lock);
2008 }
2009 }
2010
2011 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
2012 __releases(&send_cq->lock) __releases(&recv_cq->lock)
2013 {
2014 if (send_cq) {
2015 if (recv_cq) {
2016 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
2017 spin_unlock(&recv_cq->lock);
2018 spin_unlock(&send_cq->lock);
2019 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
2020 __release(&recv_cq->lock);
2021 spin_unlock(&send_cq->lock);
2022 } else {
2023 spin_unlock(&send_cq->lock);
2024 spin_unlock(&recv_cq->lock);
2025 }
2026 } else {
2027 __release(&recv_cq->lock);
2028 spin_unlock(&send_cq->lock);
2029 }
2030 } else if (recv_cq) {
2031 __release(&send_cq->lock);
2032 spin_unlock(&recv_cq->lock);
2033 } else {
2034 __release(&recv_cq->lock);
2035 __release(&send_cq->lock);
2036 }
2037 }
2038
2039 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
2040 {
2041 return to_mpd(qp->ibqp.pd);
2042 }
2043
2044 static void get_cqs(enum ib_qp_type qp_type,
2045 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
2046 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
2047 {
2048 switch (qp_type) {
2049 case IB_QPT_XRC_TGT:
2050 *send_cq = NULL;
2051 *recv_cq = NULL;
2052 break;
2053 case MLX5_IB_QPT_REG_UMR:
2054 case IB_QPT_XRC_INI:
2055 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2056 *recv_cq = NULL;
2057 break;
2058
2059 case IB_QPT_SMI:
2060 case MLX5_IB_QPT_HW_GSI:
2061 case IB_QPT_RC:
2062 case IB_QPT_UC:
2063 case IB_QPT_UD:
2064 case IB_QPT_RAW_IPV6:
2065 case IB_QPT_RAW_ETHERTYPE:
2066 case IB_QPT_RAW_PACKET:
2067 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
2068 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
2069 break;
2070
2071 case IB_QPT_MAX:
2072 default:
2073 *send_cq = NULL;
2074 *recv_cq = NULL;
2075 break;
2076 }
2077 }
2078
2079 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2080 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2081 u8 lag_tx_affinity);
2082
2083 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2084 {
2085 struct mlx5_ib_cq *send_cq, *recv_cq;
2086 struct mlx5_ib_qp_base *base;
2087 unsigned long flags;
2088 int err;
2089
2090 if (qp->ibqp.rwq_ind_tbl) {
2091 destroy_rss_raw_qp_tir(dev, qp);
2092 return;
2093 }
2094
2095 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2096 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2097 &qp->raw_packet_qp.rq.base :
2098 &qp->trans_qp.base;
2099
2100 if (qp->state != IB_QPS_RESET) {
2101 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2102 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2103 err = mlx5_core_qp_modify(dev->mdev,
2104 MLX5_CMD_OP_2RST_QP, 0,
2105 NULL, &base->mqp);
2106 } else {
2107 struct mlx5_modify_raw_qp_param raw_qp_param = {
2108 .operation = MLX5_CMD_OP_2RST_QP
2109 };
2110
2111 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2112 }
2113 if (err)
2114 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2115 base->mqp.qpn);
2116 }
2117
2118 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2119 &send_cq, &recv_cq);
2120
2121 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2122 mlx5_ib_lock_cqs(send_cq, recv_cq);
2123 /* del from lists under both locks above to protect reset flow paths */
2124 list_del(&qp->qps_list);
2125 if (send_cq)
2126 list_del(&qp->cq_send_list);
2127
2128 if (recv_cq)
2129 list_del(&qp->cq_recv_list);
2130
2131 if (qp->create_type == MLX5_QP_KERNEL) {
2132 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2133 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2134 if (send_cq != recv_cq)
2135 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2136 NULL);
2137 }
2138 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2139 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2140
2141 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2142 qp->flags & MLX5_IB_QP_UNDERLAY) {
2143 destroy_raw_packet_qp(dev, qp);
2144 } else {
2145 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2146 if (err)
2147 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2148 base->mqp.qpn);
2149 }
2150
2151 if (qp->create_type == MLX5_QP_KERNEL)
2152 destroy_qp_kernel(dev, qp);
2153 else if (qp->create_type == MLX5_QP_USER)
2154 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2155 }
2156
2157 static const char *ib_qp_type_str(enum ib_qp_type type)
2158 {
2159 switch (type) {
2160 case IB_QPT_SMI:
2161 return "IB_QPT_SMI";
2162 case IB_QPT_GSI:
2163 return "IB_QPT_GSI";
2164 case IB_QPT_RC:
2165 return "IB_QPT_RC";
2166 case IB_QPT_UC:
2167 return "IB_QPT_UC";
2168 case IB_QPT_UD:
2169 return "IB_QPT_UD";
2170 case IB_QPT_RAW_IPV6:
2171 return "IB_QPT_RAW_IPV6";
2172 case IB_QPT_RAW_ETHERTYPE:
2173 return "IB_QPT_RAW_ETHERTYPE";
2174 case IB_QPT_XRC_INI:
2175 return "IB_QPT_XRC_INI";
2176 case IB_QPT_XRC_TGT:
2177 return "IB_QPT_XRC_TGT";
2178 case IB_QPT_RAW_PACKET:
2179 return "IB_QPT_RAW_PACKET";
2180 case MLX5_IB_QPT_REG_UMR:
2181 return "MLX5_IB_QPT_REG_UMR";
2182 case IB_QPT_DRIVER:
2183 return "IB_QPT_DRIVER";
2184 case IB_QPT_MAX:
2185 default:
2186 return "Invalid QP type";
2187 }
2188 }
2189
2190 static struct ib_qp *mlx5_ib_create_dct(struct ib_pd *pd,
2191 struct ib_qp_init_attr *attr,
2192 struct mlx5_ib_create_qp *ucmd)
2193 {
2194 struct mlx5_ib_qp *qp;
2195 int err = 0;
2196 u32 uidx = MLX5_IB_DEFAULT_UIDX;
2197 void *dctc;
2198
2199 if (!attr->srq || !attr->recv_cq)
2200 return ERR_PTR(-EINVAL);
2201
2202 err = get_qp_user_index(to_mucontext(pd->uobject->context),
2203 ucmd, sizeof(*ucmd), &uidx);
2204 if (err)
2205 return ERR_PTR(err);
2206
2207 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2208 if (!qp)
2209 return ERR_PTR(-ENOMEM);
2210
2211 qp->dct.in = kzalloc(MLX5_ST_SZ_BYTES(create_dct_in), GFP_KERNEL);
2212 if (!qp->dct.in) {
2213 err = -ENOMEM;
2214 goto err_free;
2215 }
2216
2217 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
2218 qp->qp_sub_type = MLX5_IB_QPT_DCT;
2219 MLX5_SET(dctc, dctc, pd, to_mpd(pd)->pdn);
2220 MLX5_SET(dctc, dctc, srqn_xrqn, to_msrq(attr->srq)->msrq.srqn);
2221 MLX5_SET(dctc, dctc, cqn, to_mcq(attr->recv_cq)->mcq.cqn);
2222 MLX5_SET64(dctc, dctc, dc_access_key, ucmd->access_key);
2223 MLX5_SET(dctc, dctc, user_index, uidx);
2224
2225 qp->state = IB_QPS_RESET;
2226
2227 return &qp->ibqp;
2228 err_free:
2229 kfree(qp);
2230 return ERR_PTR(err);
2231 }
2232
2233 static int set_mlx_qp_type(struct mlx5_ib_dev *dev,
2234 struct ib_qp_init_attr *init_attr,
2235 struct mlx5_ib_create_qp *ucmd,
2236 struct ib_udata *udata)
2237 {
2238 enum { MLX_QP_FLAGS = MLX5_QP_FLAG_TYPE_DCT | MLX5_QP_FLAG_TYPE_DCI };
2239 int err;
2240
2241 if (!udata)
2242 return -EINVAL;
2243
2244 if (udata->inlen < sizeof(*ucmd)) {
2245 mlx5_ib_dbg(dev, "create_qp user command is smaller than expected\n");
2246 return -EINVAL;
2247 }
2248 err = ib_copy_from_udata(ucmd, udata, sizeof(*ucmd));
2249 if (err)
2250 return err;
2251
2252 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCI) {
2253 init_attr->qp_type = MLX5_IB_QPT_DCI;
2254 } else {
2255 if ((ucmd->flags & MLX_QP_FLAGS) == MLX5_QP_FLAG_TYPE_DCT) {
2256 init_attr->qp_type = MLX5_IB_QPT_DCT;
2257 } else {
2258 mlx5_ib_dbg(dev, "Invalid QP flags\n");
2259 return -EINVAL;
2260 }
2261 }
2262
2263 if (!MLX5_CAP_GEN(dev->mdev, dct)) {
2264 mlx5_ib_dbg(dev, "DC transport is not supported\n");
2265 return -EOPNOTSUPP;
2266 }
2267
2268 return 0;
2269 }
2270
2271 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2272 struct ib_qp_init_attr *verbs_init_attr,
2273 struct ib_udata *udata)
2274 {
2275 struct mlx5_ib_dev *dev;
2276 struct mlx5_ib_qp *qp;
2277 u16 xrcdn = 0;
2278 int err;
2279 struct ib_qp_init_attr mlx_init_attr;
2280 struct ib_qp_init_attr *init_attr = verbs_init_attr;
2281
2282 if (pd) {
2283 dev = to_mdev(pd->device);
2284
2285 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2286 if (!pd->uobject) {
2287 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2288 return ERR_PTR(-EINVAL);
2289 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2290 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2291 return ERR_PTR(-EINVAL);
2292 }
2293 }
2294 } else {
2295 /* being cautious here */
2296 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2297 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2298 pr_warn("%s: no PD for transport %s\n", __func__,
2299 ib_qp_type_str(init_attr->qp_type));
2300 return ERR_PTR(-EINVAL);
2301 }
2302 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2303 }
2304
2305 if (init_attr->qp_type == IB_QPT_DRIVER) {
2306 struct mlx5_ib_create_qp ucmd;
2307
2308 init_attr = &mlx_init_attr;
2309 memcpy(init_attr, verbs_init_attr, sizeof(*verbs_init_attr));
2310 err = set_mlx_qp_type(dev, init_attr, &ucmd, udata);
2311 if (err)
2312 return ERR_PTR(err);
2313
2314 if (init_attr->qp_type == MLX5_IB_QPT_DCI) {
2315 if (init_attr->cap.max_recv_wr ||
2316 init_attr->cap.max_recv_sge) {
2317 mlx5_ib_dbg(dev, "DCI QP requires zero size receive queue\n");
2318 return ERR_PTR(-EINVAL);
2319 }
2320 } else {
2321 return mlx5_ib_create_dct(pd, init_attr, &ucmd);
2322 }
2323 }
2324
2325 switch (init_attr->qp_type) {
2326 case IB_QPT_XRC_TGT:
2327 case IB_QPT_XRC_INI:
2328 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2329 mlx5_ib_dbg(dev, "XRC not supported\n");
2330 return ERR_PTR(-ENOSYS);
2331 }
2332 init_attr->recv_cq = NULL;
2333 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2334 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2335 init_attr->send_cq = NULL;
2336 }
2337
2338 /* fall through */
2339 case IB_QPT_RAW_PACKET:
2340 case IB_QPT_RC:
2341 case IB_QPT_UC:
2342 case IB_QPT_UD:
2343 case IB_QPT_SMI:
2344 case MLX5_IB_QPT_HW_GSI:
2345 case MLX5_IB_QPT_REG_UMR:
2346 case MLX5_IB_QPT_DCI:
2347 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2348 if (!qp)
2349 return ERR_PTR(-ENOMEM);
2350
2351 err = create_qp_common(dev, pd, init_attr, udata, qp);
2352 if (err) {
2353 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2354 kfree(qp);
2355 return ERR_PTR(err);
2356 }
2357
2358 if (is_qp0(init_attr->qp_type))
2359 qp->ibqp.qp_num = 0;
2360 else if (is_qp1(init_attr->qp_type))
2361 qp->ibqp.qp_num = 1;
2362 else
2363 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2364
2365 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2366 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2367 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2368 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2369
2370 qp->trans_qp.xrcdn = xrcdn;
2371
2372 break;
2373
2374 case IB_QPT_GSI:
2375 return mlx5_ib_gsi_create_qp(pd, init_attr);
2376
2377 case IB_QPT_RAW_IPV6:
2378 case IB_QPT_RAW_ETHERTYPE:
2379 case IB_QPT_MAX:
2380 default:
2381 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2382 init_attr->qp_type);
2383 /* Don't support raw QPs */
2384 return ERR_PTR(-EINVAL);
2385 }
2386
2387 if (verbs_init_attr->qp_type == IB_QPT_DRIVER)
2388 qp->qp_sub_type = init_attr->qp_type;
2389
2390 return &qp->ibqp;
2391 }
2392
2393 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp *mqp)
2394 {
2395 struct mlx5_ib_dev *dev = to_mdev(mqp->ibqp.device);
2396
2397 if (mqp->state == IB_QPS_RTR) {
2398 int err;
2399
2400 err = mlx5_core_destroy_dct(dev->mdev, &mqp->dct.mdct);
2401 if (err) {
2402 mlx5_ib_warn(dev, "failed to destroy DCT %d\n", err);
2403 return err;
2404 }
2405 }
2406
2407 kfree(mqp->dct.in);
2408 kfree(mqp);
2409 return 0;
2410 }
2411
2412 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2413 {
2414 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2415 struct mlx5_ib_qp *mqp = to_mqp(qp);
2416
2417 if (unlikely(qp->qp_type == IB_QPT_GSI))
2418 return mlx5_ib_gsi_destroy_qp(qp);
2419
2420 if (mqp->qp_sub_type == MLX5_IB_QPT_DCT)
2421 return mlx5_ib_destroy_dct(mqp);
2422
2423 destroy_qp_common(dev, mqp);
2424
2425 kfree(mqp);
2426
2427 return 0;
2428 }
2429
2430 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2431 int attr_mask)
2432 {
2433 u32 hw_access_flags = 0;
2434 u8 dest_rd_atomic;
2435 u32 access_flags;
2436
2437 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2438 dest_rd_atomic = attr->max_dest_rd_atomic;
2439 else
2440 dest_rd_atomic = qp->trans_qp.resp_depth;
2441
2442 if (attr_mask & IB_QP_ACCESS_FLAGS)
2443 access_flags = attr->qp_access_flags;
2444 else
2445 access_flags = qp->trans_qp.atomic_rd_en;
2446
2447 if (!dest_rd_atomic)
2448 access_flags &= IB_ACCESS_REMOTE_WRITE;
2449
2450 if (access_flags & IB_ACCESS_REMOTE_READ)
2451 hw_access_flags |= MLX5_QP_BIT_RRE;
2452 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2453 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2454 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2455 hw_access_flags |= MLX5_QP_BIT_RWE;
2456
2457 return cpu_to_be32(hw_access_flags);
2458 }
2459
2460 enum {
2461 MLX5_PATH_FLAG_FL = 1 << 0,
2462 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2463 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2464 };
2465
2466 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2467 {
2468 if (rate == IB_RATE_PORT_CURRENT)
2469 return 0;
2470
2471 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2472 return -EINVAL;
2473
2474 while (rate != IB_RATE_PORT_CURRENT &&
2475 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2476 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2477 --rate;
2478
2479 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2480 }
2481
2482 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2483 struct mlx5_ib_sq *sq, u8 sl)
2484 {
2485 void *in;
2486 void *tisc;
2487 int inlen;
2488 int err;
2489
2490 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2491 in = kvzalloc(inlen, GFP_KERNEL);
2492 if (!in)
2493 return -ENOMEM;
2494
2495 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2496
2497 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2498 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2499
2500 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2501
2502 kvfree(in);
2503
2504 return err;
2505 }
2506
2507 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2508 struct mlx5_ib_sq *sq, u8 tx_affinity)
2509 {
2510 void *in;
2511 void *tisc;
2512 int inlen;
2513 int err;
2514
2515 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2516 in = kvzalloc(inlen, GFP_KERNEL);
2517 if (!in)
2518 return -ENOMEM;
2519
2520 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2521
2522 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2523 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2524
2525 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2526
2527 kvfree(in);
2528
2529 return err;
2530 }
2531
2532 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2533 const struct rdma_ah_attr *ah,
2534 struct mlx5_qp_path *path, u8 port, int attr_mask,
2535 u32 path_flags, const struct ib_qp_attr *attr,
2536 bool alt)
2537 {
2538 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2539 int err;
2540 enum ib_gid_type gid_type;
2541 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2542 u8 sl = rdma_ah_get_sl(ah);
2543
2544 if (attr_mask & IB_QP_PKEY_INDEX)
2545 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2546 attr->pkey_index);
2547
2548 if (ah_flags & IB_AH_GRH) {
2549 if (grh->sgid_index >=
2550 dev->mdev->port_caps[port - 1].gid_table_len) {
2551 pr_err("sgid_index (%u) too large. max is %d\n",
2552 grh->sgid_index,
2553 dev->mdev->port_caps[port - 1].gid_table_len);
2554 return -EINVAL;
2555 }
2556 }
2557
2558 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2559 if (!(ah_flags & IB_AH_GRH))
2560 return -EINVAL;
2561
2562 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2563 if (qp->ibqp.qp_type == IB_QPT_RC ||
2564 qp->ibqp.qp_type == IB_QPT_UC ||
2565 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2566 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2567 path->udp_sport =
2568 mlx5_get_roce_udp_sport(dev, ah->grh.sgid_attr);
2569 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2570 gid_type = ah->grh.sgid_attr->gid_type;
2571 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2572 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2573 } else {
2574 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2575 path->fl_free_ar |=
2576 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2577 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2578 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2579 if (ah_flags & IB_AH_GRH)
2580 path->grh_mlid |= 1 << 7;
2581 path->dci_cfi_prio_sl = sl & 0xf;
2582 }
2583
2584 if (ah_flags & IB_AH_GRH) {
2585 path->mgid_index = grh->sgid_index;
2586 path->hop_limit = grh->hop_limit;
2587 path->tclass_flowlabel =
2588 cpu_to_be32((grh->traffic_class << 20) |
2589 (grh->flow_label));
2590 memcpy(path->rgid, grh->dgid.raw, 16);
2591 }
2592
2593 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2594 if (err < 0)
2595 return err;
2596 path->static_rate = err;
2597 path->port = port;
2598
2599 if (attr_mask & IB_QP_TIMEOUT)
2600 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2601
2602 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2603 return modify_raw_packet_eth_prio(dev->mdev,
2604 &qp->raw_packet_qp.sq,
2605 sl & 0xf);
2606
2607 return 0;
2608 }
2609
2610 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2611 [MLX5_QP_STATE_INIT] = {
2612 [MLX5_QP_STATE_INIT] = {
2613 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2614 MLX5_QP_OPTPAR_RAE |
2615 MLX5_QP_OPTPAR_RWE |
2616 MLX5_QP_OPTPAR_PKEY_INDEX |
2617 MLX5_QP_OPTPAR_PRI_PORT,
2618 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2619 MLX5_QP_OPTPAR_PKEY_INDEX |
2620 MLX5_QP_OPTPAR_PRI_PORT,
2621 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2622 MLX5_QP_OPTPAR_Q_KEY |
2623 MLX5_QP_OPTPAR_PRI_PORT,
2624 },
2625 [MLX5_QP_STATE_RTR] = {
2626 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2627 MLX5_QP_OPTPAR_RRE |
2628 MLX5_QP_OPTPAR_RAE |
2629 MLX5_QP_OPTPAR_RWE |
2630 MLX5_QP_OPTPAR_PKEY_INDEX,
2631 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2632 MLX5_QP_OPTPAR_RWE |
2633 MLX5_QP_OPTPAR_PKEY_INDEX,
2634 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2635 MLX5_QP_OPTPAR_Q_KEY,
2636 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2637 MLX5_QP_OPTPAR_Q_KEY,
2638 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2639 MLX5_QP_OPTPAR_RRE |
2640 MLX5_QP_OPTPAR_RAE |
2641 MLX5_QP_OPTPAR_RWE |
2642 MLX5_QP_OPTPAR_PKEY_INDEX,
2643 },
2644 },
2645 [MLX5_QP_STATE_RTR] = {
2646 [MLX5_QP_STATE_RTS] = {
2647 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2648 MLX5_QP_OPTPAR_RRE |
2649 MLX5_QP_OPTPAR_RAE |
2650 MLX5_QP_OPTPAR_RWE |
2651 MLX5_QP_OPTPAR_PM_STATE |
2652 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2653 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2654 MLX5_QP_OPTPAR_RWE |
2655 MLX5_QP_OPTPAR_PM_STATE,
2656 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2657 },
2658 },
2659 [MLX5_QP_STATE_RTS] = {
2660 [MLX5_QP_STATE_RTS] = {
2661 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2662 MLX5_QP_OPTPAR_RAE |
2663 MLX5_QP_OPTPAR_RWE |
2664 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2665 MLX5_QP_OPTPAR_PM_STATE |
2666 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2667 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2668 MLX5_QP_OPTPAR_PM_STATE |
2669 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2670 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2671 MLX5_QP_OPTPAR_SRQN |
2672 MLX5_QP_OPTPAR_CQN_RCV,
2673 },
2674 },
2675 [MLX5_QP_STATE_SQER] = {
2676 [MLX5_QP_STATE_RTS] = {
2677 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2678 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2679 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2680 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2681 MLX5_QP_OPTPAR_RWE |
2682 MLX5_QP_OPTPAR_RAE |
2683 MLX5_QP_OPTPAR_RRE,
2684 },
2685 },
2686 };
2687
2688 static int ib_nr_to_mlx5_nr(int ib_mask)
2689 {
2690 switch (ib_mask) {
2691 case IB_QP_STATE:
2692 return 0;
2693 case IB_QP_CUR_STATE:
2694 return 0;
2695 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2696 return 0;
2697 case IB_QP_ACCESS_FLAGS:
2698 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2699 MLX5_QP_OPTPAR_RAE;
2700 case IB_QP_PKEY_INDEX:
2701 return MLX5_QP_OPTPAR_PKEY_INDEX;
2702 case IB_QP_PORT:
2703 return MLX5_QP_OPTPAR_PRI_PORT;
2704 case IB_QP_QKEY:
2705 return MLX5_QP_OPTPAR_Q_KEY;
2706 case IB_QP_AV:
2707 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2708 MLX5_QP_OPTPAR_PRI_PORT;
2709 case IB_QP_PATH_MTU:
2710 return 0;
2711 case IB_QP_TIMEOUT:
2712 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2713 case IB_QP_RETRY_CNT:
2714 return MLX5_QP_OPTPAR_RETRY_COUNT;
2715 case IB_QP_RNR_RETRY:
2716 return MLX5_QP_OPTPAR_RNR_RETRY;
2717 case IB_QP_RQ_PSN:
2718 return 0;
2719 case IB_QP_MAX_QP_RD_ATOMIC:
2720 return MLX5_QP_OPTPAR_SRA_MAX;
2721 case IB_QP_ALT_PATH:
2722 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2723 case IB_QP_MIN_RNR_TIMER:
2724 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2725 case IB_QP_SQ_PSN:
2726 return 0;
2727 case IB_QP_MAX_DEST_RD_ATOMIC:
2728 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2729 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2730 case IB_QP_PATH_MIG_STATE:
2731 return MLX5_QP_OPTPAR_PM_STATE;
2732 case IB_QP_CAP:
2733 return 0;
2734 case IB_QP_DEST_QPN:
2735 return 0;
2736 }
2737 return 0;
2738 }
2739
2740 static int ib_mask_to_mlx5_opt(int ib_mask)
2741 {
2742 int result = 0;
2743 int i;
2744
2745 for (i = 0; i < 8 * sizeof(int); i++) {
2746 if ((1 << i) & ib_mask)
2747 result |= ib_nr_to_mlx5_nr(1 << i);
2748 }
2749
2750 return result;
2751 }
2752
2753 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2754 struct mlx5_ib_rq *rq, int new_state,
2755 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2756 {
2757 void *in;
2758 void *rqc;
2759 int inlen;
2760 int err;
2761
2762 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2763 in = kvzalloc(inlen, GFP_KERNEL);
2764 if (!in)
2765 return -ENOMEM;
2766
2767 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2768
2769 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2770 MLX5_SET(rqc, rqc, state, new_state);
2771
2772 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2773 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2774 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2775 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2776 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2777 } else
2778 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2779 dev->ib_dev.name);
2780 }
2781
2782 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2783 if (err)
2784 goto out;
2785
2786 rq->state = new_state;
2787
2788 out:
2789 kvfree(in);
2790 return err;
2791 }
2792
2793 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2794 struct mlx5_ib_sq *sq,
2795 int new_state,
2796 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2797 {
2798 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2799 struct mlx5_rate_limit old_rl = ibqp->rl;
2800 struct mlx5_rate_limit new_rl = old_rl;
2801 bool new_rate_added = false;
2802 u16 rl_index = 0;
2803 void *in;
2804 void *sqc;
2805 int inlen;
2806 int err;
2807
2808 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2809 in = kvzalloc(inlen, GFP_KERNEL);
2810 if (!in)
2811 return -ENOMEM;
2812
2813 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2814
2815 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2816 MLX5_SET(sqc, sqc, state, new_state);
2817
2818 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2819 if (new_state != MLX5_SQC_STATE_RDY)
2820 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2821 __func__);
2822 else
2823 new_rl = raw_qp_param->rl;
2824 }
2825
2826 if (!mlx5_rl_are_equal(&old_rl, &new_rl)) {
2827 if (new_rl.rate) {
2828 err = mlx5_rl_add_rate(dev, &rl_index, &new_rl);
2829 if (err) {
2830 pr_err("Failed configuring rate limit(err %d): \
2831 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2832 err, new_rl.rate, new_rl.max_burst_sz,
2833 new_rl.typical_pkt_sz);
2834
2835 goto out;
2836 }
2837 new_rate_added = true;
2838 }
2839
2840 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2841 /* index 0 means no limit */
2842 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2843 }
2844
2845 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2846 if (err) {
2847 /* Remove new rate from table if failed */
2848 if (new_rate_added)
2849 mlx5_rl_remove_rate(dev, &new_rl);
2850 goto out;
2851 }
2852
2853 /* Only remove the old rate after new rate was set */
2854 if ((old_rl.rate &&
2855 !mlx5_rl_are_equal(&old_rl, &new_rl)) ||
2856 (new_state != MLX5_SQC_STATE_RDY))
2857 mlx5_rl_remove_rate(dev, &old_rl);
2858
2859 ibqp->rl = new_rl;
2860 sq->state = new_state;
2861
2862 out:
2863 kvfree(in);
2864 return err;
2865 }
2866
2867 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2868 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2869 u8 tx_affinity)
2870 {
2871 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2872 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2873 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2874 int modify_rq = !!qp->rq.wqe_cnt;
2875 int modify_sq = !!qp->sq.wqe_cnt;
2876 int rq_state;
2877 int sq_state;
2878 int err;
2879
2880 switch (raw_qp_param->operation) {
2881 case MLX5_CMD_OP_RST2INIT_QP:
2882 rq_state = MLX5_RQC_STATE_RDY;
2883 sq_state = MLX5_SQC_STATE_RDY;
2884 break;
2885 case MLX5_CMD_OP_2ERR_QP:
2886 rq_state = MLX5_RQC_STATE_ERR;
2887 sq_state = MLX5_SQC_STATE_ERR;
2888 break;
2889 case MLX5_CMD_OP_2RST_QP:
2890 rq_state = MLX5_RQC_STATE_RST;
2891 sq_state = MLX5_SQC_STATE_RST;
2892 break;
2893 case MLX5_CMD_OP_RTR2RTS_QP:
2894 case MLX5_CMD_OP_RTS2RTS_QP:
2895 if (raw_qp_param->set_mask ==
2896 MLX5_RAW_QP_RATE_LIMIT) {
2897 modify_rq = 0;
2898 sq_state = sq->state;
2899 } else {
2900 return raw_qp_param->set_mask ? -EINVAL : 0;
2901 }
2902 break;
2903 case MLX5_CMD_OP_INIT2INIT_QP:
2904 case MLX5_CMD_OP_INIT2RTR_QP:
2905 if (raw_qp_param->set_mask)
2906 return -EINVAL;
2907 else
2908 return 0;
2909 default:
2910 WARN_ON(1);
2911 return -EINVAL;
2912 }
2913
2914 if (modify_rq) {
2915 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2916 if (err)
2917 return err;
2918 }
2919
2920 if (modify_sq) {
2921 if (tx_affinity) {
2922 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2923 tx_affinity);
2924 if (err)
2925 return err;
2926 }
2927
2928 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2929 }
2930
2931 return 0;
2932 }
2933
2934 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2935 const struct ib_qp_attr *attr, int attr_mask,
2936 enum ib_qp_state cur_state, enum ib_qp_state new_state,
2937 const struct mlx5_ib_modify_qp *ucmd)
2938 {
2939 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2940 [MLX5_QP_STATE_RST] = {
2941 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2942 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2943 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2944 },
2945 [MLX5_QP_STATE_INIT] = {
2946 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2947 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2948 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2949 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2950 },
2951 [MLX5_QP_STATE_RTR] = {
2952 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2953 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2954 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2955 },
2956 [MLX5_QP_STATE_RTS] = {
2957 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2958 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2959 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2960 },
2961 [MLX5_QP_STATE_SQD] = {
2962 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2963 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2964 },
2965 [MLX5_QP_STATE_SQER] = {
2966 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2967 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2968 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2969 },
2970 [MLX5_QP_STATE_ERR] = {
2971 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2972 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2973 }
2974 };
2975
2976 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2977 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2978 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2979 struct mlx5_ib_cq *send_cq, *recv_cq;
2980 struct mlx5_qp_context *context;
2981 struct mlx5_ib_pd *pd;
2982 struct mlx5_ib_port *mibport = NULL;
2983 enum mlx5_qp_state mlx5_cur, mlx5_new;
2984 enum mlx5_qp_optpar optpar;
2985 int mlx5_st;
2986 int err;
2987 u16 op;
2988 u8 tx_affinity = 0;
2989
2990 mlx5_st = to_mlx5_st(ibqp->qp_type == IB_QPT_DRIVER ?
2991 qp->qp_sub_type : ibqp->qp_type);
2992 if (mlx5_st < 0)
2993 return -EINVAL;
2994
2995 context = kzalloc(sizeof(*context), GFP_KERNEL);
2996 if (!context)
2997 return -ENOMEM;
2998
2999 context->flags = cpu_to_be32(mlx5_st << 16);
3000
3001 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
3002 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3003 } else {
3004 switch (attr->path_mig_state) {
3005 case IB_MIG_MIGRATED:
3006 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
3007 break;
3008 case IB_MIG_REARM:
3009 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
3010 break;
3011 case IB_MIG_ARMED:
3012 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
3013 break;
3014 }
3015 }
3016
3017 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
3018 if ((ibqp->qp_type == IB_QPT_RC) ||
3019 (ibqp->qp_type == IB_QPT_UD &&
3020 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
3021 (ibqp->qp_type == IB_QPT_UC) ||
3022 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
3023 (ibqp->qp_type == IB_QPT_XRC_INI) ||
3024 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
3025 if (mlx5_lag_is_active(dev->mdev)) {
3026 u8 p = mlx5_core_native_port_num(dev->mdev);
3027 tx_affinity = (unsigned int)atomic_add_return(1,
3028 &dev->roce[p].next_port) %
3029 MLX5_MAX_PORTS + 1;
3030 context->flags |= cpu_to_be32(tx_affinity << 24);
3031 }
3032 }
3033 }
3034
3035 if (is_sqp(ibqp->qp_type)) {
3036 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
3037 } else if ((ibqp->qp_type == IB_QPT_UD &&
3038 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
3039 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
3040 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
3041 } else if (attr_mask & IB_QP_PATH_MTU) {
3042 if (attr->path_mtu < IB_MTU_256 ||
3043 attr->path_mtu > IB_MTU_4096) {
3044 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
3045 err = -EINVAL;
3046 goto out;
3047 }
3048 context->mtu_msgmax = (attr->path_mtu << 5) |
3049 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
3050 }
3051
3052 if (attr_mask & IB_QP_DEST_QPN)
3053 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
3054
3055 if (attr_mask & IB_QP_PKEY_INDEX)
3056 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
3057
3058 /* todo implement counter_index functionality */
3059
3060 if (is_sqp(ibqp->qp_type))
3061 context->pri_path.port = qp->port;
3062
3063 if (attr_mask & IB_QP_PORT)
3064 context->pri_path.port = attr->port_num;
3065
3066 if (attr_mask & IB_QP_AV) {
3067 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
3068 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
3069 attr_mask, 0, attr, false);
3070 if (err)
3071 goto out;
3072 }
3073
3074 if (attr_mask & IB_QP_TIMEOUT)
3075 context->pri_path.ackto_lt |= attr->timeout << 3;
3076
3077 if (attr_mask & IB_QP_ALT_PATH) {
3078 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
3079 &context->alt_path,
3080 attr->alt_port_num,
3081 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
3082 0, attr, true);
3083 if (err)
3084 goto out;
3085 }
3086
3087 pd = get_pd(qp);
3088 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
3089 &send_cq, &recv_cq);
3090
3091 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
3092 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
3093 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
3094 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
3095
3096 if (attr_mask & IB_QP_RNR_RETRY)
3097 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
3098
3099 if (attr_mask & IB_QP_RETRY_CNT)
3100 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
3101
3102 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
3103 if (attr->max_rd_atomic)
3104 context->params1 |=
3105 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
3106 }
3107
3108 if (attr_mask & IB_QP_SQ_PSN)
3109 context->next_send_psn = cpu_to_be32(attr->sq_psn);
3110
3111 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
3112 if (attr->max_dest_rd_atomic)
3113 context->params2 |=
3114 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
3115 }
3116
3117 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
3118 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
3119
3120 if (attr_mask & IB_QP_MIN_RNR_TIMER)
3121 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
3122
3123 if (attr_mask & IB_QP_RQ_PSN)
3124 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
3125
3126 if (attr_mask & IB_QP_QKEY)
3127 context->qkey = cpu_to_be32(attr->qkey);
3128
3129 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3130 context->db_rec_addr = cpu_to_be64(qp->db.dma);
3131
3132 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3133 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
3134 qp->port) - 1;
3135
3136 /* Underlay port should be used - index 0 function per port */
3137 if (qp->flags & MLX5_IB_QP_UNDERLAY)
3138 port_num = 0;
3139
3140 mibport = &dev->port[port_num];
3141 context->qp_counter_set_usr_page |=
3142 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
3143 }
3144
3145 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
3146 context->sq_crq_size |= cpu_to_be16(1 << 4);
3147
3148 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
3149 context->deth_sqpn = cpu_to_be32(1);
3150
3151 mlx5_cur = to_mlx5_state(cur_state);
3152 mlx5_new = to_mlx5_state(new_state);
3153
3154 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
3155 !optab[mlx5_cur][mlx5_new]) {
3156 err = -EINVAL;
3157 goto out;
3158 }
3159
3160 op = optab[mlx5_cur][mlx5_new];
3161 optpar = ib_mask_to_mlx5_opt(attr_mask);
3162 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
3163
3164 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
3165 qp->flags & MLX5_IB_QP_UNDERLAY) {
3166 struct mlx5_modify_raw_qp_param raw_qp_param = {};
3167
3168 raw_qp_param.operation = op;
3169 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3170 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
3171 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
3172 }
3173
3174 if (attr_mask & IB_QP_RATE_LIMIT) {
3175 raw_qp_param.rl.rate = attr->rate_limit;
3176
3177 if (ucmd->burst_info.max_burst_sz) {
3178 if (attr->rate_limit &&
3179 MLX5_CAP_QOS(dev->mdev, packet_pacing_burst_bound)) {
3180 raw_qp_param.rl.max_burst_sz =
3181 ucmd->burst_info.max_burst_sz;
3182 } else {
3183 err = -EINVAL;
3184 goto out;
3185 }
3186 }
3187
3188 if (ucmd->burst_info.typical_pkt_sz) {
3189 if (attr->rate_limit &&
3190 MLX5_CAP_QOS(dev->mdev, packet_pacing_typical_size)) {
3191 raw_qp_param.rl.typical_pkt_sz =
3192 ucmd->burst_info.typical_pkt_sz;
3193 } else {
3194 err = -EINVAL;
3195 goto out;
3196 }
3197 }
3198
3199 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
3200 }
3201
3202 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
3203 } else {
3204 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
3205 &base->mqp);
3206 }
3207
3208 if (err)
3209 goto out;
3210
3211 qp->state = new_state;
3212
3213 if (attr_mask & IB_QP_ACCESS_FLAGS)
3214 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
3215 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
3216 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
3217 if (attr_mask & IB_QP_PORT)
3218 qp->port = attr->port_num;
3219 if (attr_mask & IB_QP_ALT_PATH)
3220 qp->trans_qp.alt_port = attr->alt_port_num;
3221
3222 /*
3223 * If we moved a kernel QP to RESET, clean up all old CQ
3224 * entries and reinitialize the QP.
3225 */
3226 if (new_state == IB_QPS_RESET &&
3227 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
3228 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
3229 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
3230 if (send_cq != recv_cq)
3231 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3232
3233 qp->rq.head = 0;
3234 qp->rq.tail = 0;
3235 qp->sq.head = 0;
3236 qp->sq.tail = 0;
3237 qp->sq.cur_post = 0;
3238 qp->sq.last_poll = 0;
3239 qp->db.db[MLX5_RCV_DBR] = 0;
3240 qp->db.db[MLX5_SND_DBR] = 0;
3241 }
3242
3243 out:
3244 kfree(context);
3245 return err;
3246 }
3247
3248 static inline bool is_valid_mask(int mask, int req, int opt)
3249 {
3250 if ((mask & req) != req)
3251 return false;
3252
3253 if (mask & ~(req | opt))
3254 return false;
3255
3256 return true;
3257 }
3258
3259 /* check valid transition for driver QP types
3260 * for now the only QP type that this function supports is DCI
3261 */
3262 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state, enum ib_qp_state new_state,
3263 enum ib_qp_attr_mask attr_mask)
3264 {
3265 int req = IB_QP_STATE;
3266 int opt = 0;
3267
3268 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3269 req |= IB_QP_PKEY_INDEX | IB_QP_PORT;
3270 return is_valid_mask(attr_mask, req, opt);
3271 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
3272 opt = IB_QP_PKEY_INDEX | IB_QP_PORT;
3273 return is_valid_mask(attr_mask, req, opt);
3274 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3275 req |= IB_QP_PATH_MTU;
3276 opt = IB_QP_PKEY_INDEX;
3277 return is_valid_mask(attr_mask, req, opt);
3278 } else if (cur_state == IB_QPS_RTR && new_state == IB_QPS_RTS) {
3279 req |= IB_QP_TIMEOUT | IB_QP_RETRY_CNT | IB_QP_RNR_RETRY |
3280 IB_QP_MAX_QP_RD_ATOMIC | IB_QP_SQ_PSN;
3281 opt = IB_QP_MIN_RNR_TIMER;
3282 return is_valid_mask(attr_mask, req, opt);
3283 } else if (cur_state == IB_QPS_RTS && new_state == IB_QPS_RTS) {
3284 opt = IB_QP_MIN_RNR_TIMER;
3285 return is_valid_mask(attr_mask, req, opt);
3286 } else if (cur_state != IB_QPS_RESET && new_state == IB_QPS_ERR) {
3287 return is_valid_mask(attr_mask, req, opt);
3288 }
3289 return false;
3290 }
3291
3292 /* mlx5_ib_modify_dct: modify a DCT QP
3293 * valid transitions are:
3294 * RESET to INIT: must set access_flags, pkey_index and port
3295 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3296 * mtu, gid_index and hop_limit
3297 * Other transitions and attributes are illegal
3298 */
3299 static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3300 int attr_mask, struct ib_udata *udata)
3301 {
3302 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3303 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3304 enum ib_qp_state cur_state, new_state;
3305 int err = 0;
3306 int required = IB_QP_STATE;
3307 void *dctc;
3308
3309 if (!(attr_mask & IB_QP_STATE))
3310 return -EINVAL;
3311
3312 cur_state = qp->state;
3313 new_state = attr->qp_state;
3314
3315 dctc = MLX5_ADDR_OF(create_dct_in, qp->dct.in, dct_context_entry);
3316 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
3317 required |= IB_QP_ACCESS_FLAGS | IB_QP_PKEY_INDEX | IB_QP_PORT;
3318 if (!is_valid_mask(attr_mask, required, 0))
3319 return -EINVAL;
3320
3321 if (attr->port_num == 0 ||
3322 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) {
3323 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3324 attr->port_num, dev->num_ports);
3325 return -EINVAL;
3326 }
3327 if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ)
3328 MLX5_SET(dctc, dctc, rre, 1);
3329 if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE)
3330 MLX5_SET(dctc, dctc, rwe, 1);
3331 if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) {
3332 if (!mlx5_ib_dc_atomic_is_supported(dev))
3333 return -EOPNOTSUPP;
3334 MLX5_SET(dctc, dctc, rae, 1);
3335 MLX5_SET(dctc, dctc, atomic_mode, MLX5_ATOMIC_MODE_DCT_CX);
3336 }
3337 MLX5_SET(dctc, dctc, pkey_index, attr->pkey_index);
3338 MLX5_SET(dctc, dctc, port, attr->port_num);
3339 MLX5_SET(dctc, dctc, counter_set_id, dev->port[attr->port_num - 1].cnts.set_id);
3340
3341 } else if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
3342 struct mlx5_ib_modify_qp_resp resp = {};
3343 u32 min_resp_len = offsetof(typeof(resp), dctn) +
3344 sizeof(resp.dctn);
3345
3346 if (udata->outlen < min_resp_len)
3347 return -EINVAL;
3348 resp.response_length = min_resp_len;
3349
3350 required |= IB_QP_MIN_RNR_TIMER | IB_QP_AV | IB_QP_PATH_MTU;
3351 if (!is_valid_mask(attr_mask, required, 0))
3352 return -EINVAL;
3353 MLX5_SET(dctc, dctc, min_rnr_nak, attr->min_rnr_timer);
3354 MLX5_SET(dctc, dctc, tclass, attr->ah_attr.grh.traffic_class);
3355 MLX5_SET(dctc, dctc, flow_label, attr->ah_attr.grh.flow_label);
3356 MLX5_SET(dctc, dctc, mtu, attr->path_mtu);
3357 MLX5_SET(dctc, dctc, my_addr_index, attr->ah_attr.grh.sgid_index);
3358 MLX5_SET(dctc, dctc, hop_limit, attr->ah_attr.grh.hop_limit);
3359
3360 err = mlx5_core_create_dct(dev->mdev, &qp->dct.mdct, qp->dct.in,
3361 MLX5_ST_SZ_BYTES(create_dct_in));
3362 if (err)
3363 return err;
3364 resp.dctn = qp->dct.mdct.mqp.qpn;
3365 err = ib_copy_to_udata(udata, &resp, resp.response_length);
3366 if (err) {
3367 mlx5_core_destroy_dct(dev->mdev, &qp->dct.mdct);
3368 return err;
3369 }
3370 } else {
3371 mlx5_ib_warn(dev, "Modify DCT: Invalid transition from %d to %d\n", cur_state, new_state);
3372 return -EINVAL;
3373 }
3374 if (err)
3375 qp->state = IB_QPS_ERR;
3376 else
3377 qp->state = new_state;
3378 return err;
3379 }
3380
3381 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3382 int attr_mask, struct ib_udata *udata)
3383 {
3384 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3385 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3386 struct mlx5_ib_modify_qp ucmd = {};
3387 enum ib_qp_type qp_type;
3388 enum ib_qp_state cur_state, new_state;
3389 size_t required_cmd_sz;
3390 int err = -EINVAL;
3391 int port;
3392 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3393
3394 if (ibqp->rwq_ind_tbl)
3395 return -ENOSYS;
3396
3397 if (udata && udata->inlen) {
3398 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
3399 sizeof(ucmd.reserved);
3400 if (udata->inlen < required_cmd_sz)
3401 return -EINVAL;
3402
3403 if (udata->inlen > sizeof(ucmd) &&
3404 !ib_is_udata_cleared(udata, sizeof(ucmd),
3405 udata->inlen - sizeof(ucmd)))
3406 return -EOPNOTSUPP;
3407
3408 if (ib_copy_from_udata(&ucmd, udata,
3409 min(udata->inlen, sizeof(ucmd))))
3410 return -EFAULT;
3411
3412 if (ucmd.comp_mask ||
3413 memchr_inv(&ucmd.reserved, 0, sizeof(ucmd.reserved)) ||
3414 memchr_inv(&ucmd.burst_info.reserved, 0,
3415 sizeof(ucmd.burst_info.reserved)))
3416 return -EOPNOTSUPP;
3417 }
3418
3419 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3420 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3421
3422 if (ibqp->qp_type == IB_QPT_DRIVER)
3423 qp_type = qp->qp_sub_type;
3424 else
3425 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3426 IB_QPT_GSI : ibqp->qp_type;
3427
3428 if (qp_type == MLX5_IB_QPT_DCT)
3429 return mlx5_ib_modify_dct(ibqp, attr, attr_mask, udata);
3430
3431 mutex_lock(&qp->mutex);
3432
3433 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3434 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3435
3436 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3437 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3438 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3439 }
3440
3441 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3442 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3443 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3444 attr_mask);
3445 goto out;
3446 }
3447 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3448 qp_type != MLX5_IB_QPT_DCI &&
3449 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3450 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3451 cur_state, new_state, ibqp->qp_type, attr_mask);
3452 goto out;
3453 } else if (qp_type == MLX5_IB_QPT_DCI &&
3454 !modify_dci_qp_is_ok(cur_state, new_state, attr_mask)) {
3455 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3456 cur_state, new_state, qp_type, attr_mask);
3457 goto out;
3458 }
3459
3460 if ((attr_mask & IB_QP_PORT) &&
3461 (attr->port_num == 0 ||
3462 attr->port_num > dev->num_ports)) {
3463 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3464 attr->port_num, dev->num_ports);
3465 goto out;
3466 }
3467
3468 if (attr_mask & IB_QP_PKEY_INDEX) {
3469 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3470 if (attr->pkey_index >=
3471 dev->mdev->port_caps[port - 1].pkey_table_len) {
3472 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3473 attr->pkey_index);
3474 goto out;
3475 }
3476 }
3477
3478 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3479 attr->max_rd_atomic >
3480 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3481 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3482 attr->max_rd_atomic);
3483 goto out;
3484 }
3485
3486 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3487 attr->max_dest_rd_atomic >
3488 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3489 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3490 attr->max_dest_rd_atomic);
3491 goto out;
3492 }
3493
3494 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3495 err = 0;
3496 goto out;
3497 }
3498
3499 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state,
3500 new_state, &ucmd);
3501
3502 out:
3503 mutex_unlock(&qp->mutex);
3504 return err;
3505 }
3506
3507 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3508 {
3509 struct mlx5_ib_cq *cq;
3510 unsigned cur;
3511
3512 cur = wq->head - wq->tail;
3513 if (likely(cur + nreq < wq->max_post))
3514 return 0;
3515
3516 cq = to_mcq(ib_cq);
3517 spin_lock(&cq->lock);
3518 cur = wq->head - wq->tail;
3519 spin_unlock(&cq->lock);
3520
3521 return cur + nreq >= wq->max_post;
3522 }
3523
3524 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3525 u64 remote_addr, u32 rkey)
3526 {
3527 rseg->raddr = cpu_to_be64(remote_addr);
3528 rseg->rkey = cpu_to_be32(rkey);
3529 rseg->reserved = 0;
3530 }
3531
3532 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3533 struct ib_send_wr *wr, void *qend,
3534 struct mlx5_ib_qp *qp, int *size)
3535 {
3536 void *seg = eseg;
3537
3538 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3539
3540 if (wr->send_flags & IB_SEND_IP_CSUM)
3541 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3542 MLX5_ETH_WQE_L4_CSUM;
3543
3544 seg += sizeof(struct mlx5_wqe_eth_seg);
3545 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3546
3547 if (wr->opcode == IB_WR_LSO) {
3548 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3549 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3550 u64 left, leftlen, copysz;
3551 void *pdata = ud_wr->header;
3552
3553 left = ud_wr->hlen;
3554 eseg->mss = cpu_to_be16(ud_wr->mss);
3555 eseg->inline_hdr.sz = cpu_to_be16(left);
3556
3557 /*
3558 * check if there is space till the end of queue, if yes,
3559 * copy all in one shot, otherwise copy till the end of queue,
3560 * rollback and than the copy the left
3561 */
3562 leftlen = qend - (void *)eseg->inline_hdr.start;
3563 copysz = min_t(u64, leftlen, left);
3564
3565 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3566
3567 if (likely(copysz > size_of_inl_hdr_start)) {
3568 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3569 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3570 }
3571
3572 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3573 seg = mlx5_get_send_wqe(qp, 0);
3574 left -= copysz;
3575 pdata += copysz;
3576 memcpy(seg, pdata, left);
3577 seg += ALIGN(left, 16);
3578 *size += ALIGN(left, 16) / 16;
3579 }
3580 }
3581
3582 return seg;
3583 }
3584
3585 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3586 struct ib_send_wr *wr)
3587 {
3588 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3589 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3590 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3591 }
3592
3593 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3594 {
3595 dseg->byte_count = cpu_to_be32(sg->length);
3596 dseg->lkey = cpu_to_be32(sg->lkey);
3597 dseg->addr = cpu_to_be64(sg->addr);
3598 }
3599
3600 static u64 get_xlt_octo(u64 bytes)
3601 {
3602 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3603 MLX5_IB_UMR_OCTOWORD;
3604 }
3605
3606 static __be64 frwr_mkey_mask(void)
3607 {
3608 u64 result;
3609
3610 result = MLX5_MKEY_MASK_LEN |
3611 MLX5_MKEY_MASK_PAGE_SIZE |
3612 MLX5_MKEY_MASK_START_ADDR |
3613 MLX5_MKEY_MASK_EN_RINVAL |
3614 MLX5_MKEY_MASK_KEY |
3615 MLX5_MKEY_MASK_LR |
3616 MLX5_MKEY_MASK_LW |
3617 MLX5_MKEY_MASK_RR |
3618 MLX5_MKEY_MASK_RW |
3619 MLX5_MKEY_MASK_A |
3620 MLX5_MKEY_MASK_SMALL_FENCE |
3621 MLX5_MKEY_MASK_FREE;
3622
3623 return cpu_to_be64(result);
3624 }
3625
3626 static __be64 sig_mkey_mask(void)
3627 {
3628 u64 result;
3629
3630 result = MLX5_MKEY_MASK_LEN |
3631 MLX5_MKEY_MASK_PAGE_SIZE |
3632 MLX5_MKEY_MASK_START_ADDR |
3633 MLX5_MKEY_MASK_EN_SIGERR |
3634 MLX5_MKEY_MASK_EN_RINVAL |
3635 MLX5_MKEY_MASK_KEY |
3636 MLX5_MKEY_MASK_LR |
3637 MLX5_MKEY_MASK_LW |
3638 MLX5_MKEY_MASK_RR |
3639 MLX5_MKEY_MASK_RW |
3640 MLX5_MKEY_MASK_SMALL_FENCE |
3641 MLX5_MKEY_MASK_FREE |
3642 MLX5_MKEY_MASK_BSF_EN;
3643
3644 return cpu_to_be64(result);
3645 }
3646
3647 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3648 struct mlx5_ib_mr *mr, bool umr_inline)
3649 {
3650 int size = mr->ndescs * mr->desc_size;
3651
3652 memset(umr, 0, sizeof(*umr));
3653
3654 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3655 if (umr_inline)
3656 umr->flags |= MLX5_UMR_INLINE;
3657 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3658 umr->mkey_mask = frwr_mkey_mask();
3659 }
3660
3661 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3662 {
3663 memset(umr, 0, sizeof(*umr));
3664 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3665 umr->flags = MLX5_UMR_INLINE;
3666 }
3667
3668 static __be64 get_umr_enable_mr_mask(void)
3669 {
3670 u64 result;
3671
3672 result = MLX5_MKEY_MASK_KEY |
3673 MLX5_MKEY_MASK_FREE;
3674
3675 return cpu_to_be64(result);
3676 }
3677
3678 static __be64 get_umr_disable_mr_mask(void)
3679 {
3680 u64 result;
3681
3682 result = MLX5_MKEY_MASK_FREE;
3683
3684 return cpu_to_be64(result);
3685 }
3686
3687 static __be64 get_umr_update_translation_mask(void)
3688 {
3689 u64 result;
3690
3691 result = MLX5_MKEY_MASK_LEN |
3692 MLX5_MKEY_MASK_PAGE_SIZE |
3693 MLX5_MKEY_MASK_START_ADDR;
3694
3695 return cpu_to_be64(result);
3696 }
3697
3698 static __be64 get_umr_update_access_mask(int atomic)
3699 {
3700 u64 result;
3701
3702 result = MLX5_MKEY_MASK_LR |
3703 MLX5_MKEY_MASK_LW |
3704 MLX5_MKEY_MASK_RR |
3705 MLX5_MKEY_MASK_RW;
3706
3707 if (atomic)
3708 result |= MLX5_MKEY_MASK_A;
3709
3710 return cpu_to_be64(result);
3711 }
3712
3713 static __be64 get_umr_update_pd_mask(void)
3714 {
3715 u64 result;
3716
3717 result = MLX5_MKEY_MASK_PD;
3718
3719 return cpu_to_be64(result);
3720 }
3721
3722 static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask)
3723 {
3724 if ((mask & MLX5_MKEY_MASK_PAGE_SIZE &&
3725 MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) ||
3726 (mask & MLX5_MKEY_MASK_A &&
3727 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)))
3728 return -EPERM;
3729 return 0;
3730 }
3731
3732 static int set_reg_umr_segment(struct mlx5_ib_dev *dev,
3733 struct mlx5_wqe_umr_ctrl_seg *umr,
3734 struct ib_send_wr *wr, int atomic)
3735 {
3736 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3737
3738 memset(umr, 0, sizeof(*umr));
3739
3740 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3741 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3742 else
3743 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3744
3745 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3746 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3747 u64 offset = get_xlt_octo(umrwr->offset);
3748
3749 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3750 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3751 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3752 }
3753 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3754 umr->mkey_mask |= get_umr_update_translation_mask();
3755 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3756 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3757 umr->mkey_mask |= get_umr_update_pd_mask();
3758 }
3759 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3760 umr->mkey_mask |= get_umr_enable_mr_mask();
3761 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3762 umr->mkey_mask |= get_umr_disable_mr_mask();
3763
3764 if (!wr->num_sge)
3765 umr->flags |= MLX5_UMR_INLINE;
3766
3767 return umr_check_mkey_mask(dev, be64_to_cpu(umr->mkey_mask));
3768 }
3769
3770 static u8 get_umr_flags(int acc)
3771 {
3772 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3773 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3774 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3775 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3776 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3777 }
3778
3779 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3780 struct mlx5_ib_mr *mr,
3781 u32 key, int access)
3782 {
3783 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3784
3785 memset(seg, 0, sizeof(*seg));
3786
3787 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3788 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3789 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3790 /* KLMs take twice the size of MTTs */
3791 ndescs *= 2;
3792
3793 seg->flags = get_umr_flags(access) | mr->access_mode;
3794 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3795 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3796 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3797 seg->len = cpu_to_be64(mr->ibmr.length);
3798 seg->xlt_oct_size = cpu_to_be32(ndescs);
3799 }
3800
3801 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3802 {
3803 memset(seg, 0, sizeof(*seg));
3804 seg->status = MLX5_MKEY_STATUS_FREE;
3805 }
3806
3807 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3808 {
3809 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3810
3811 memset(seg, 0, sizeof(*seg));
3812 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3813 seg->status = MLX5_MKEY_STATUS_FREE;
3814
3815 seg->flags = convert_access(umrwr->access_flags);
3816 if (umrwr->pd)
3817 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3818 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3819 !umrwr->length)
3820 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3821
3822 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3823 seg->len = cpu_to_be64(umrwr->length);
3824 seg->log2_page_size = umrwr->page_shift;
3825 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3826 mlx5_mkey_variant(umrwr->mkey));
3827 }
3828
3829 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3830 struct mlx5_ib_mr *mr,
3831 struct mlx5_ib_pd *pd)
3832 {
3833 int bcount = mr->desc_size * mr->ndescs;
3834
3835 dseg->addr = cpu_to_be64(mr->desc_map);
3836 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3837 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3838 }
3839
3840 static void set_reg_umr_inline_seg(void *seg, struct mlx5_ib_qp *qp,
3841 struct mlx5_ib_mr *mr, int mr_list_size)
3842 {
3843 void *qend = qp->sq.qend;
3844 void *addr = mr->descs;
3845 int copy;
3846
3847 if (unlikely(seg + mr_list_size > qend)) {
3848 copy = qend - seg;
3849 memcpy(seg, addr, copy);
3850 addr += copy;
3851 mr_list_size -= copy;
3852 seg = mlx5_get_send_wqe(qp, 0);
3853 }
3854 memcpy(seg, addr, mr_list_size);
3855 seg += mr_list_size;
3856 }
3857
3858 static __be32 send_ieth(struct ib_send_wr *wr)
3859 {
3860 switch (wr->opcode) {
3861 case IB_WR_SEND_WITH_IMM:
3862 case IB_WR_RDMA_WRITE_WITH_IMM:
3863 return wr->ex.imm_data;
3864
3865 case IB_WR_SEND_WITH_INV:
3866 return cpu_to_be32(wr->ex.invalidate_rkey);
3867
3868 default:
3869 return 0;
3870 }
3871 }
3872
3873 static u8 calc_sig(void *wqe, int size)
3874 {
3875 u8 *p = wqe;
3876 u8 res = 0;
3877 int i;
3878
3879 for (i = 0; i < size; i++)
3880 res ^= p[i];
3881
3882 return ~res;
3883 }
3884
3885 static u8 wq_sig(void *wqe)
3886 {
3887 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3888 }
3889
3890 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3891 void *wqe, int *sz)
3892 {
3893 struct mlx5_wqe_inline_seg *seg;
3894 void *qend = qp->sq.qend;
3895 void *addr;
3896 int inl = 0;
3897 int copy;
3898 int len;
3899 int i;
3900
3901 seg = wqe;
3902 wqe += sizeof(*seg);
3903 for (i = 0; i < wr->num_sge; i++) {
3904 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3905 len = wr->sg_list[i].length;
3906 inl += len;
3907
3908 if (unlikely(inl > qp->max_inline_data))
3909 return -ENOMEM;
3910
3911 if (unlikely(wqe + len > qend)) {
3912 copy = qend - wqe;
3913 memcpy(wqe, addr, copy);
3914 addr += copy;
3915 len -= copy;
3916 wqe = mlx5_get_send_wqe(qp, 0);
3917 }
3918 memcpy(wqe, addr, len);
3919 wqe += len;
3920 }
3921
3922 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3923
3924 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3925
3926 return 0;
3927 }
3928
3929 static u16 prot_field_size(enum ib_signature_type type)
3930 {
3931 switch (type) {
3932 case IB_SIG_TYPE_T10_DIF:
3933 return MLX5_DIF_SIZE;
3934 default:
3935 return 0;
3936 }
3937 }
3938
3939 static u8 bs_selector(int block_size)
3940 {
3941 switch (block_size) {
3942 case 512: return 0x1;
3943 case 520: return 0x2;
3944 case 4096: return 0x3;
3945 case 4160: return 0x4;
3946 case 1073741824: return 0x5;
3947 default: return 0;
3948 }
3949 }
3950
3951 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3952 struct mlx5_bsf_inl *inl)
3953 {
3954 /* Valid inline section and allow BSF refresh */
3955 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3956 MLX5_BSF_REFRESH_DIF);
3957 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3958 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3959 /* repeating block */
3960 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3961 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3962 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3963
3964 if (domain->sig.dif.ref_remap)
3965 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3966
3967 if (domain->sig.dif.app_escape) {
3968 if (domain->sig.dif.ref_escape)
3969 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3970 else
3971 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3972 }
3973
3974 inl->dif_app_bitmask_check =
3975 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3976 }
3977
3978 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3979 struct ib_sig_attrs *sig_attrs,
3980 struct mlx5_bsf *bsf, u32 data_size)
3981 {
3982 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3983 struct mlx5_bsf_basic *basic = &bsf->basic;
3984 struct ib_sig_domain *mem = &sig_attrs->mem;
3985 struct ib_sig_domain *wire = &sig_attrs->wire;
3986
3987 memset(bsf, 0, sizeof(*bsf));
3988
3989 /* Basic + Extended + Inline */
3990 basic->bsf_size_sbs = 1 << 7;
3991 /* Input domain check byte mask */
3992 basic->check_byte_mask = sig_attrs->check_mask;
3993 basic->raw_data_size = cpu_to_be32(data_size);
3994
3995 /* Memory domain */
3996 switch (sig_attrs->mem.sig_type) {
3997 case IB_SIG_TYPE_NONE:
3998 break;
3999 case IB_SIG_TYPE_T10_DIF:
4000 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
4001 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
4002 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
4003 break;
4004 default:
4005 return -EINVAL;
4006 }
4007
4008 /* Wire domain */
4009 switch (sig_attrs->wire.sig_type) {
4010 case IB_SIG_TYPE_NONE:
4011 break;
4012 case IB_SIG_TYPE_T10_DIF:
4013 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
4014 mem->sig_type == wire->sig_type) {
4015 /* Same block structure */
4016 basic->bsf_size_sbs |= 1 << 4;
4017 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
4018 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
4019 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
4020 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
4021 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
4022 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
4023 } else
4024 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
4025
4026 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
4027 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
4028 break;
4029 default:
4030 return -EINVAL;
4031 }
4032
4033 return 0;
4034 }
4035
4036 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
4037 struct mlx5_ib_qp *qp, void **seg, int *size)
4038 {
4039 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
4040 struct ib_mr *sig_mr = wr->sig_mr;
4041 struct mlx5_bsf *bsf;
4042 u32 data_len = wr->wr.sg_list->length;
4043 u32 data_key = wr->wr.sg_list->lkey;
4044 u64 data_va = wr->wr.sg_list->addr;
4045 int ret;
4046 int wqe_size;
4047
4048 if (!wr->prot ||
4049 (data_key == wr->prot->lkey &&
4050 data_va == wr->prot->addr &&
4051 data_len == wr->prot->length)) {
4052 /**
4053 * Source domain doesn't contain signature information
4054 * or data and protection are interleaved in memory.
4055 * So need construct:
4056 * ------------------
4057 * | data_klm |
4058 * ------------------
4059 * | BSF |
4060 * ------------------
4061 **/
4062 struct mlx5_klm *data_klm = *seg;
4063
4064 data_klm->bcount = cpu_to_be32(data_len);
4065 data_klm->key = cpu_to_be32(data_key);
4066 data_klm->va = cpu_to_be64(data_va);
4067 wqe_size = ALIGN(sizeof(*data_klm), 64);
4068 } else {
4069 /**
4070 * Source domain contains signature information
4071 * So need construct a strided block format:
4072 * ---------------------------
4073 * | stride_block_ctrl |
4074 * ---------------------------
4075 * | data_klm |
4076 * ---------------------------
4077 * | prot_klm |
4078 * ---------------------------
4079 * | BSF |
4080 * ---------------------------
4081 **/
4082 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
4083 struct mlx5_stride_block_entry *data_sentry;
4084 struct mlx5_stride_block_entry *prot_sentry;
4085 u32 prot_key = wr->prot->lkey;
4086 u64 prot_va = wr->prot->addr;
4087 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
4088 int prot_size;
4089
4090 sblock_ctrl = *seg;
4091 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
4092 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
4093
4094 prot_size = prot_field_size(sig_attrs->mem.sig_type);
4095 if (!prot_size) {
4096 pr_err("Bad block size given: %u\n", block_size);
4097 return -EINVAL;
4098 }
4099 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
4100 prot_size);
4101 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
4102 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
4103 sblock_ctrl->num_entries = cpu_to_be16(2);
4104
4105 data_sentry->bcount = cpu_to_be16(block_size);
4106 data_sentry->key = cpu_to_be32(data_key);
4107 data_sentry->va = cpu_to_be64(data_va);
4108 data_sentry->stride = cpu_to_be16(block_size);
4109
4110 prot_sentry->bcount = cpu_to_be16(prot_size);
4111 prot_sentry->key = cpu_to_be32(prot_key);
4112 prot_sentry->va = cpu_to_be64(prot_va);
4113 prot_sentry->stride = cpu_to_be16(prot_size);
4114
4115 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
4116 sizeof(*prot_sentry), 64);
4117 }
4118
4119 *seg += wqe_size;
4120 *size += wqe_size / 16;
4121 if (unlikely((*seg == qp->sq.qend)))
4122 *seg = mlx5_get_send_wqe(qp, 0);
4123
4124 bsf = *seg;
4125 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
4126 if (ret)
4127 return -EINVAL;
4128
4129 *seg += sizeof(*bsf);
4130 *size += sizeof(*bsf) / 16;
4131 if (unlikely((*seg == qp->sq.qend)))
4132 *seg = mlx5_get_send_wqe(qp, 0);
4133
4134 return 0;
4135 }
4136
4137 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
4138 struct ib_sig_handover_wr *wr, u32 size,
4139 u32 length, u32 pdn)
4140 {
4141 struct ib_mr *sig_mr = wr->sig_mr;
4142 u32 sig_key = sig_mr->rkey;
4143 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
4144
4145 memset(seg, 0, sizeof(*seg));
4146
4147 seg->flags = get_umr_flags(wr->access_flags) |
4148 MLX5_MKC_ACCESS_MODE_KLMS;
4149 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
4150 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
4151 MLX5_MKEY_BSF_EN | pdn);
4152 seg->len = cpu_to_be64(length);
4153 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
4154 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
4155 }
4156
4157 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
4158 u32 size)
4159 {
4160 memset(umr, 0, sizeof(*umr));
4161
4162 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
4163 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
4164 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
4165 umr->mkey_mask = sig_mkey_mask();
4166 }
4167
4168
4169 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
4170 void **seg, int *size)
4171 {
4172 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
4173 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
4174 u32 pdn = get_pd(qp)->pdn;
4175 u32 xlt_size;
4176 int region_len, ret;
4177
4178 if (unlikely(wr->wr.num_sge != 1) ||
4179 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
4180 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
4181 unlikely(!sig_mr->sig->sig_status_checked))
4182 return -EINVAL;
4183
4184 /* length of the protected region, data + protection */
4185 region_len = wr->wr.sg_list->length;
4186 if (wr->prot &&
4187 (wr->prot->lkey != wr->wr.sg_list->lkey ||
4188 wr->prot->addr != wr->wr.sg_list->addr ||
4189 wr->prot->length != wr->wr.sg_list->length))
4190 region_len += wr->prot->length;
4191
4192 /**
4193 * KLM octoword size - if protection was provided
4194 * then we use strided block format (3 octowords),
4195 * else we use single KLM (1 octoword)
4196 **/
4197 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
4198
4199 set_sig_umr_segment(*seg, xlt_size);
4200 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4201 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4202 if (unlikely((*seg == qp->sq.qend)))
4203 *seg = mlx5_get_send_wqe(qp, 0);
4204
4205 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
4206 *seg += sizeof(struct mlx5_mkey_seg);
4207 *size += sizeof(struct mlx5_mkey_seg) / 16;
4208 if (unlikely((*seg == qp->sq.qend)))
4209 *seg = mlx5_get_send_wqe(qp, 0);
4210
4211 ret = set_sig_data_segment(wr, qp, seg, size);
4212 if (ret)
4213 return ret;
4214
4215 sig_mr->sig->sig_status_checked = false;
4216 return 0;
4217 }
4218
4219 static int set_psv_wr(struct ib_sig_domain *domain,
4220 u32 psv_idx, void **seg, int *size)
4221 {
4222 struct mlx5_seg_set_psv *psv_seg = *seg;
4223
4224 memset(psv_seg, 0, sizeof(*psv_seg));
4225 psv_seg->psv_num = cpu_to_be32(psv_idx);
4226 switch (domain->sig_type) {
4227 case IB_SIG_TYPE_NONE:
4228 break;
4229 case IB_SIG_TYPE_T10_DIF:
4230 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
4231 domain->sig.dif.app_tag);
4232 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
4233 break;
4234 default:
4235 pr_err("Bad signature type (%d) is given.\n",
4236 domain->sig_type);
4237 return -EINVAL;
4238 }
4239
4240 *seg += sizeof(*psv_seg);
4241 *size += sizeof(*psv_seg) / 16;
4242
4243 return 0;
4244 }
4245
4246 static int set_reg_wr(struct mlx5_ib_qp *qp,
4247 struct ib_reg_wr *wr,
4248 void **seg, int *size)
4249 {
4250 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
4251 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
4252 int mr_list_size = mr->ndescs * mr->desc_size;
4253 bool umr_inline = mr_list_size <= MLX5_IB_SQ_UMR_INLINE_THRESHOLD;
4254
4255 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
4256 mlx5_ib_warn(to_mdev(qp->ibqp.device),
4257 "Invalid IB_SEND_INLINE send flag\n");
4258 return -EINVAL;
4259 }
4260
4261 set_reg_umr_seg(*seg, mr, umr_inline);
4262 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4263 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4264 if (unlikely((*seg == qp->sq.qend)))
4265 *seg = mlx5_get_send_wqe(qp, 0);
4266
4267 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
4268 *seg += sizeof(struct mlx5_mkey_seg);
4269 *size += sizeof(struct mlx5_mkey_seg) / 16;
4270 if (unlikely((*seg == qp->sq.qend)))
4271 *seg = mlx5_get_send_wqe(qp, 0);
4272
4273 if (umr_inline) {
4274 set_reg_umr_inline_seg(*seg, qp, mr, mr_list_size);
4275 *size += get_xlt_octo(mr_list_size);
4276 } else {
4277 set_reg_data_seg(*seg, mr, pd);
4278 *seg += sizeof(struct mlx5_wqe_data_seg);
4279 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
4280 }
4281 return 0;
4282 }
4283
4284 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
4285 {
4286 set_linv_umr_seg(*seg);
4287 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4288 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4289 if (unlikely((*seg == qp->sq.qend)))
4290 *seg = mlx5_get_send_wqe(qp, 0);
4291 set_linv_mkey_seg(*seg);
4292 *seg += sizeof(struct mlx5_mkey_seg);
4293 *size += sizeof(struct mlx5_mkey_seg) / 16;
4294 if (unlikely((*seg == qp->sq.qend)))
4295 *seg = mlx5_get_send_wqe(qp, 0);
4296 }
4297
4298 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
4299 {
4300 __be32 *p = NULL;
4301 int tidx = idx;
4302 int i, j;
4303
4304 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
4305 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
4306 if ((i & 0xf) == 0) {
4307 void *buf = mlx5_get_send_wqe(qp, tidx);
4308 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
4309 p = buf;
4310 j = 0;
4311 }
4312 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
4313 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
4314 be32_to_cpu(p[j + 3]));
4315 }
4316 }
4317
4318 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
4319 struct mlx5_wqe_ctrl_seg **ctrl,
4320 struct ib_send_wr *wr, unsigned *idx,
4321 int *size, int nreq)
4322 {
4323 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
4324 return -ENOMEM;
4325
4326 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
4327 *seg = mlx5_get_send_wqe(qp, *idx);
4328 *ctrl = *seg;
4329 *(uint32_t *)(*seg + 8) = 0;
4330 (*ctrl)->imm = send_ieth(wr);
4331 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
4332 (wr->send_flags & IB_SEND_SIGNALED ?
4333 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
4334 (wr->send_flags & IB_SEND_SOLICITED ?
4335 MLX5_WQE_CTRL_SOLICITED : 0);
4336
4337 *seg += sizeof(**ctrl);
4338 *size = sizeof(**ctrl) / 16;
4339
4340 return 0;
4341 }
4342
4343 static void finish_wqe(struct mlx5_ib_qp *qp,
4344 struct mlx5_wqe_ctrl_seg *ctrl,
4345 u8 size, unsigned idx, u64 wr_id,
4346 int nreq, u8 fence, u32 mlx5_opcode)
4347 {
4348 u8 opmod = 0;
4349
4350 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
4351 mlx5_opcode | ((u32)opmod << 24));
4352 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
4353 ctrl->fm_ce_se |= fence;
4354 if (unlikely(qp->wq_sig))
4355 ctrl->signature = wq_sig(ctrl);
4356
4357 qp->sq.wrid[idx] = wr_id;
4358 qp->sq.w_list[idx].opcode = mlx5_opcode;
4359 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
4360 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
4361 qp->sq.w_list[idx].next = qp->sq.cur_post;
4362 }
4363
4364
4365 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
4366 struct ib_send_wr **bad_wr)
4367 {
4368 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
4369 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4370 struct mlx5_core_dev *mdev = dev->mdev;
4371 struct mlx5_ib_qp *qp;
4372 struct mlx5_ib_mr *mr;
4373 struct mlx5_wqe_data_seg *dpseg;
4374 struct mlx5_wqe_xrc_seg *xrc;
4375 struct mlx5_bf *bf;
4376 int uninitialized_var(size);
4377 void *qend;
4378 unsigned long flags;
4379 unsigned idx;
4380 int err = 0;
4381 int num_sge;
4382 void *seg;
4383 int nreq;
4384 int i;
4385 u8 next_fence = 0;
4386 u8 fence;
4387
4388 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4389 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
4390
4391 qp = to_mqp(ibqp);
4392 bf = &qp->bf;
4393 qend = qp->sq.qend;
4394
4395 spin_lock_irqsave(&qp->sq.lock, flags);
4396
4397 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4398 err = -EIO;
4399 *bad_wr = wr;
4400 nreq = 0;
4401 goto out;
4402 }
4403
4404 for (nreq = 0; wr; nreq++, wr = wr->next) {
4405 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
4406 mlx5_ib_warn(dev, "\n");
4407 err = -EINVAL;
4408 *bad_wr = wr;
4409 goto out;
4410 }
4411
4412 num_sge = wr->num_sge;
4413 if (unlikely(num_sge > qp->sq.max_gs)) {
4414 mlx5_ib_warn(dev, "\n");
4415 err = -EINVAL;
4416 *bad_wr = wr;
4417 goto out;
4418 }
4419
4420 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
4421 if (err) {
4422 mlx5_ib_warn(dev, "\n");
4423 err = -ENOMEM;
4424 *bad_wr = wr;
4425 goto out;
4426 }
4427
4428 if (wr->opcode == IB_WR_LOCAL_INV ||
4429 wr->opcode == IB_WR_REG_MR) {
4430 fence = dev->umr_fence;
4431 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4432 } else if (wr->send_flags & IB_SEND_FENCE) {
4433 if (qp->next_fence)
4434 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
4435 else
4436 fence = MLX5_FENCE_MODE_FENCE;
4437 } else {
4438 fence = qp->next_fence;
4439 }
4440
4441 switch (ibqp->qp_type) {
4442 case IB_QPT_XRC_INI:
4443 xrc = seg;
4444 seg += sizeof(*xrc);
4445 size += sizeof(*xrc) / 16;
4446 /* fall through */
4447 case IB_QPT_RC:
4448 switch (wr->opcode) {
4449 case IB_WR_RDMA_READ:
4450 case IB_WR_RDMA_WRITE:
4451 case IB_WR_RDMA_WRITE_WITH_IMM:
4452 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4453 rdma_wr(wr)->rkey);
4454 seg += sizeof(struct mlx5_wqe_raddr_seg);
4455 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4456 break;
4457
4458 case IB_WR_ATOMIC_CMP_AND_SWP:
4459 case IB_WR_ATOMIC_FETCH_AND_ADD:
4460 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4461 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4462 err = -ENOSYS;
4463 *bad_wr = wr;
4464 goto out;
4465
4466 case IB_WR_LOCAL_INV:
4467 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4468 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4469 set_linv_wr(qp, &seg, &size);
4470 num_sge = 0;
4471 break;
4472
4473 case IB_WR_REG_MR:
4474 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4475 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4476 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4477 if (err) {
4478 *bad_wr = wr;
4479 goto out;
4480 }
4481 num_sge = 0;
4482 break;
4483
4484 case IB_WR_REG_SIG_MR:
4485 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4486 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4487
4488 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4489 err = set_sig_umr_wr(wr, qp, &seg, &size);
4490 if (err) {
4491 mlx5_ib_warn(dev, "\n");
4492 *bad_wr = wr;
4493 goto out;
4494 }
4495
4496 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4497 fence, MLX5_OPCODE_UMR);
4498 /*
4499 * SET_PSV WQEs are not signaled and solicited
4500 * on error
4501 */
4502 wr->send_flags &= ~IB_SEND_SIGNALED;
4503 wr->send_flags |= IB_SEND_SOLICITED;
4504 err = begin_wqe(qp, &seg, &ctrl, wr,
4505 &idx, &size, nreq);
4506 if (err) {
4507 mlx5_ib_warn(dev, "\n");
4508 err = -ENOMEM;
4509 *bad_wr = wr;
4510 goto out;
4511 }
4512
4513 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4514 mr->sig->psv_memory.psv_idx, &seg,
4515 &size);
4516 if (err) {
4517 mlx5_ib_warn(dev, "\n");
4518 *bad_wr = wr;
4519 goto out;
4520 }
4521
4522 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4523 fence, MLX5_OPCODE_SET_PSV);
4524 err = begin_wqe(qp, &seg, &ctrl, wr,
4525 &idx, &size, nreq);
4526 if (err) {
4527 mlx5_ib_warn(dev, "\n");
4528 err = -ENOMEM;
4529 *bad_wr = wr;
4530 goto out;
4531 }
4532
4533 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4534 mr->sig->psv_wire.psv_idx, &seg,
4535 &size);
4536 if (err) {
4537 mlx5_ib_warn(dev, "\n");
4538 *bad_wr = wr;
4539 goto out;
4540 }
4541
4542 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4543 fence, MLX5_OPCODE_SET_PSV);
4544 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4545 num_sge = 0;
4546 goto skip_psv;
4547
4548 default:
4549 break;
4550 }
4551 break;
4552
4553 case IB_QPT_UC:
4554 switch (wr->opcode) {
4555 case IB_WR_RDMA_WRITE:
4556 case IB_WR_RDMA_WRITE_WITH_IMM:
4557 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4558 rdma_wr(wr)->rkey);
4559 seg += sizeof(struct mlx5_wqe_raddr_seg);
4560 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4561 break;
4562
4563 default:
4564 break;
4565 }
4566 break;
4567
4568 case IB_QPT_SMI:
4569 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4570 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4571 err = -EPERM;
4572 *bad_wr = wr;
4573 goto out;
4574 }
4575 /* fall through */
4576 case MLX5_IB_QPT_HW_GSI:
4577 set_datagram_seg(seg, wr);
4578 seg += sizeof(struct mlx5_wqe_datagram_seg);
4579 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4580 if (unlikely((seg == qend)))
4581 seg = mlx5_get_send_wqe(qp, 0);
4582 break;
4583 case IB_QPT_UD:
4584 set_datagram_seg(seg, wr);
4585 seg += sizeof(struct mlx5_wqe_datagram_seg);
4586 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4587
4588 if (unlikely((seg == qend)))
4589 seg = mlx5_get_send_wqe(qp, 0);
4590
4591 /* handle qp that supports ud offload */
4592 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4593 struct mlx5_wqe_eth_pad *pad;
4594
4595 pad = seg;
4596 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4597 seg += sizeof(struct mlx5_wqe_eth_pad);
4598 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4599
4600 seg = set_eth_seg(seg, wr, qend, qp, &size);
4601
4602 if (unlikely((seg == qend)))
4603 seg = mlx5_get_send_wqe(qp, 0);
4604 }
4605 break;
4606 case MLX5_IB_QPT_REG_UMR:
4607 if (wr->opcode != MLX5_IB_WR_UMR) {
4608 err = -EINVAL;
4609 mlx5_ib_warn(dev, "bad opcode\n");
4610 goto out;
4611 }
4612 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4613 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4614 err = set_reg_umr_segment(dev, seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4615 if (unlikely(err))
4616 goto out;
4617 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4618 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4619 if (unlikely((seg == qend)))
4620 seg = mlx5_get_send_wqe(qp, 0);
4621 set_reg_mkey_segment(seg, wr);
4622 seg += sizeof(struct mlx5_mkey_seg);
4623 size += sizeof(struct mlx5_mkey_seg) / 16;
4624 if (unlikely((seg == qend)))
4625 seg = mlx5_get_send_wqe(qp, 0);
4626 break;
4627
4628 default:
4629 break;
4630 }
4631
4632 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4633 int uninitialized_var(sz);
4634
4635 err = set_data_inl_seg(qp, wr, seg, &sz);
4636 if (unlikely(err)) {
4637 mlx5_ib_warn(dev, "\n");
4638 *bad_wr = wr;
4639 goto out;
4640 }
4641 size += sz;
4642 } else {
4643 dpseg = seg;
4644 for (i = 0; i < num_sge; i++) {
4645 if (unlikely(dpseg == qend)) {
4646 seg = mlx5_get_send_wqe(qp, 0);
4647 dpseg = seg;
4648 }
4649 if (likely(wr->sg_list[i].length)) {
4650 set_data_ptr_seg(dpseg, wr->sg_list + i);
4651 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4652 dpseg++;
4653 }
4654 }
4655 }
4656
4657 qp->next_fence = next_fence;
4658 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4659 mlx5_ib_opcode[wr->opcode]);
4660 skip_psv:
4661 if (0)
4662 dump_wqe(qp, idx, size);
4663 }
4664
4665 out:
4666 if (likely(nreq)) {
4667 qp->sq.head += nreq;
4668
4669 /* Make sure that descriptors are written before
4670 * updating doorbell record and ringing the doorbell
4671 */
4672 wmb();
4673
4674 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4675
4676 /* Make sure doorbell record is visible to the HCA before
4677 * we hit doorbell */
4678 wmb();
4679
4680 /* currently we support only regular doorbells */
4681 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4682 /* Make sure doorbells don't leak out of SQ spinlock
4683 * and reach the HCA out of order.
4684 */
4685 mmiowb();
4686 bf->offset ^= bf->buf_size;
4687 }
4688
4689 spin_unlock_irqrestore(&qp->sq.lock, flags);
4690
4691 return err;
4692 }
4693
4694 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4695 {
4696 sig->signature = calc_sig(sig, size);
4697 }
4698
4699 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4700 struct ib_recv_wr **bad_wr)
4701 {
4702 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4703 struct mlx5_wqe_data_seg *scat;
4704 struct mlx5_rwqe_sig *sig;
4705 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4706 struct mlx5_core_dev *mdev = dev->mdev;
4707 unsigned long flags;
4708 int err = 0;
4709 int nreq;
4710 int ind;
4711 int i;
4712
4713 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4714 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4715
4716 spin_lock_irqsave(&qp->rq.lock, flags);
4717
4718 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4719 err = -EIO;
4720 *bad_wr = wr;
4721 nreq = 0;
4722 goto out;
4723 }
4724
4725 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4726
4727 for (nreq = 0; wr; nreq++, wr = wr->next) {
4728 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4729 err = -ENOMEM;
4730 *bad_wr = wr;
4731 goto out;
4732 }
4733
4734 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4735 err = -EINVAL;
4736 *bad_wr = wr;
4737 goto out;
4738 }
4739
4740 scat = get_recv_wqe(qp, ind);
4741 if (qp->wq_sig)
4742 scat++;
4743
4744 for (i = 0; i < wr->num_sge; i++)
4745 set_data_ptr_seg(scat + i, wr->sg_list + i);
4746
4747 if (i < qp->rq.max_gs) {
4748 scat[i].byte_count = 0;
4749 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4750 scat[i].addr = 0;
4751 }
4752
4753 if (qp->wq_sig) {
4754 sig = (struct mlx5_rwqe_sig *)scat;
4755 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4756 }
4757
4758 qp->rq.wrid[ind] = wr->wr_id;
4759
4760 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4761 }
4762
4763 out:
4764 if (likely(nreq)) {
4765 qp->rq.head += nreq;
4766
4767 /* Make sure that descriptors are written before
4768 * doorbell record.
4769 */
4770 wmb();
4771
4772 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4773 }
4774
4775 spin_unlock_irqrestore(&qp->rq.lock, flags);
4776
4777 return err;
4778 }
4779
4780 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4781 {
4782 switch (mlx5_state) {
4783 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4784 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4785 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4786 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4787 case MLX5_QP_STATE_SQ_DRAINING:
4788 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4789 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4790 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4791 default: return -1;
4792 }
4793 }
4794
4795 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4796 {
4797 switch (mlx5_mig_state) {
4798 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4799 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4800 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4801 default: return -1;
4802 }
4803 }
4804
4805 static int to_ib_qp_access_flags(int mlx5_flags)
4806 {
4807 int ib_flags = 0;
4808
4809 if (mlx5_flags & MLX5_QP_BIT_RRE)
4810 ib_flags |= IB_ACCESS_REMOTE_READ;
4811 if (mlx5_flags & MLX5_QP_BIT_RWE)
4812 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4813 if (mlx5_flags & MLX5_QP_BIT_RAE)
4814 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4815
4816 return ib_flags;
4817 }
4818
4819 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4820 struct rdma_ah_attr *ah_attr,
4821 struct mlx5_qp_path *path)
4822 {
4823
4824 memset(ah_attr, 0, sizeof(*ah_attr));
4825
4826 if (!path->port || path->port > ibdev->num_ports)
4827 return;
4828
4829 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4830
4831 rdma_ah_set_port_num(ah_attr, path->port);
4832 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4833
4834 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4835 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4836 rdma_ah_set_static_rate(ah_attr,
4837 path->static_rate ? path->static_rate - 5 : 0);
4838 if (path->grh_mlid & (1 << 7)) {
4839 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4840
4841 rdma_ah_set_grh(ah_attr, NULL,
4842 tc_fl & 0xfffff,
4843 path->mgid_index,
4844 path->hop_limit,
4845 (tc_fl >> 20) & 0xff);
4846 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4847 }
4848 }
4849
4850 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4851 struct mlx5_ib_sq *sq,
4852 u8 *sq_state)
4853 {
4854 int err;
4855
4856 err = mlx5_core_query_sq_state(dev->mdev, sq->base.mqp.qpn, sq_state);
4857 if (err)
4858 goto out;
4859 sq->state = *sq_state;
4860
4861 out:
4862 return err;
4863 }
4864
4865 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4866 struct mlx5_ib_rq *rq,
4867 u8 *rq_state)
4868 {
4869 void *out;
4870 void *rqc;
4871 int inlen;
4872 int err;
4873
4874 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4875 out = kvzalloc(inlen, GFP_KERNEL);
4876 if (!out)
4877 return -ENOMEM;
4878
4879 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4880 if (err)
4881 goto out;
4882
4883 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4884 *rq_state = MLX5_GET(rqc, rqc, state);
4885 rq->state = *rq_state;
4886
4887 out:
4888 kvfree(out);
4889 return err;
4890 }
4891
4892 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4893 struct mlx5_ib_qp *qp, u8 *qp_state)
4894 {
4895 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4896 [MLX5_RQC_STATE_RST] = {
4897 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4898 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4899 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4900 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4901 },
4902 [MLX5_RQC_STATE_RDY] = {
4903 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4904 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4905 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4906 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4907 },
4908 [MLX5_RQC_STATE_ERR] = {
4909 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4910 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4911 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4912 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4913 },
4914 [MLX5_RQ_STATE_NA] = {
4915 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4916 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4917 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4918 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4919 },
4920 };
4921
4922 *qp_state = sqrq_trans[rq_state][sq_state];
4923
4924 if (*qp_state == MLX5_QP_STATE_BAD) {
4925 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4926 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4927 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4928 return -EINVAL;
4929 }
4930
4931 if (*qp_state == MLX5_QP_STATE)
4932 *qp_state = qp->state;
4933
4934 return 0;
4935 }
4936
4937 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4938 struct mlx5_ib_qp *qp,
4939 u8 *raw_packet_qp_state)
4940 {
4941 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4942 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4943 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4944 int err;
4945 u8 sq_state = MLX5_SQ_STATE_NA;
4946 u8 rq_state = MLX5_RQ_STATE_NA;
4947
4948 if (qp->sq.wqe_cnt) {
4949 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4950 if (err)
4951 return err;
4952 }
4953
4954 if (qp->rq.wqe_cnt) {
4955 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4956 if (err)
4957 return err;
4958 }
4959
4960 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4961 raw_packet_qp_state);
4962 }
4963
4964 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4965 struct ib_qp_attr *qp_attr)
4966 {
4967 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4968 struct mlx5_qp_context *context;
4969 int mlx5_state;
4970 u32 *outb;
4971 int err = 0;
4972
4973 outb = kzalloc(outlen, GFP_KERNEL);
4974 if (!outb)
4975 return -ENOMEM;
4976
4977 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4978 outlen);
4979 if (err)
4980 goto out;
4981
4982 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4983 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4984
4985 mlx5_state = be32_to_cpu(context->flags) >> 28;
4986
4987 qp->state = to_ib_qp_state(mlx5_state);
4988 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4989 qp_attr->path_mig_state =
4990 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4991 qp_attr->qkey = be32_to_cpu(context->qkey);
4992 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4993 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4994 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4995 qp_attr->qp_access_flags =
4996 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4997
4998 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4999 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
5000 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
5001 qp_attr->alt_pkey_index =
5002 be16_to_cpu(context->alt_path.pkey_index);
5003 qp_attr->alt_port_num =
5004 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
5005 }
5006
5007 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
5008 qp_attr->port_num = context->pri_path.port;
5009
5010 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
5011 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
5012
5013 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
5014
5015 qp_attr->max_dest_rd_atomic =
5016 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
5017 qp_attr->min_rnr_timer =
5018 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
5019 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
5020 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
5021 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
5022 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
5023
5024 out:
5025 kfree(outb);
5026 return err;
5027 }
5028
5029 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *mqp,
5030 struct ib_qp_attr *qp_attr, int qp_attr_mask,
5031 struct ib_qp_init_attr *qp_init_attr)
5032 {
5033 struct mlx5_core_dct *dct = &mqp->dct.mdct;
5034 u32 *out;
5035 u32 access_flags = 0;
5036 int outlen = MLX5_ST_SZ_BYTES(query_dct_out);
5037 void *dctc;
5038 int err;
5039 int supported_mask = IB_QP_STATE |
5040 IB_QP_ACCESS_FLAGS |
5041 IB_QP_PORT |
5042 IB_QP_MIN_RNR_TIMER |
5043 IB_QP_AV |
5044 IB_QP_PATH_MTU |
5045 IB_QP_PKEY_INDEX;
5046
5047 if (qp_attr_mask & ~supported_mask)
5048 return -EINVAL;
5049 if (mqp->state != IB_QPS_RTR)
5050 return -EINVAL;
5051
5052 out = kzalloc(outlen, GFP_KERNEL);
5053 if (!out)
5054 return -ENOMEM;
5055
5056 err = mlx5_core_dct_query(dev->mdev, dct, out, outlen);
5057 if (err)
5058 goto out;
5059
5060 dctc = MLX5_ADDR_OF(query_dct_out, out, dct_context_entry);
5061
5062 if (qp_attr_mask & IB_QP_STATE)
5063 qp_attr->qp_state = IB_QPS_RTR;
5064
5065 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
5066 if (MLX5_GET(dctc, dctc, rre))
5067 access_flags |= IB_ACCESS_REMOTE_READ;
5068 if (MLX5_GET(dctc, dctc, rwe))
5069 access_flags |= IB_ACCESS_REMOTE_WRITE;
5070 if (MLX5_GET(dctc, dctc, rae))
5071 access_flags |= IB_ACCESS_REMOTE_ATOMIC;
5072 qp_attr->qp_access_flags = access_flags;
5073 }
5074
5075 if (qp_attr_mask & IB_QP_PORT)
5076 qp_attr->port_num = MLX5_GET(dctc, dctc, port);
5077 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER)
5078 qp_attr->min_rnr_timer = MLX5_GET(dctc, dctc, min_rnr_nak);
5079 if (qp_attr_mask & IB_QP_AV) {
5080 qp_attr->ah_attr.grh.traffic_class = MLX5_GET(dctc, dctc, tclass);
5081 qp_attr->ah_attr.grh.flow_label = MLX5_GET(dctc, dctc, flow_label);
5082 qp_attr->ah_attr.grh.sgid_index = MLX5_GET(dctc, dctc, my_addr_index);
5083 qp_attr->ah_attr.grh.hop_limit = MLX5_GET(dctc, dctc, hop_limit);
5084 }
5085 if (qp_attr_mask & IB_QP_PATH_MTU)
5086 qp_attr->path_mtu = MLX5_GET(dctc, dctc, mtu);
5087 if (qp_attr_mask & IB_QP_PKEY_INDEX)
5088 qp_attr->pkey_index = MLX5_GET(dctc, dctc, pkey_index);
5089 out:
5090 kfree(out);
5091 return err;
5092 }
5093
5094 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
5095 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
5096 {
5097 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
5098 struct mlx5_ib_qp *qp = to_mqp(ibqp);
5099 int err = 0;
5100 u8 raw_packet_qp_state;
5101
5102 if (ibqp->rwq_ind_tbl)
5103 return -ENOSYS;
5104
5105 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
5106 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
5107 qp_init_attr);
5108
5109 /* Not all of output fields are applicable, make sure to zero them */
5110 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
5111 memset(qp_attr, 0, sizeof(*qp_attr));
5112
5113 if (unlikely(qp->qp_sub_type == MLX5_IB_QPT_DCT))
5114 return mlx5_ib_dct_query_qp(dev, qp, qp_attr,
5115 qp_attr_mask, qp_init_attr);
5116
5117 mutex_lock(&qp->mutex);
5118
5119 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
5120 qp->flags & MLX5_IB_QP_UNDERLAY) {
5121 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
5122 if (err)
5123 goto out;
5124 qp->state = raw_packet_qp_state;
5125 qp_attr->port_num = 1;
5126 } else {
5127 err = query_qp_attr(dev, qp, qp_attr);
5128 if (err)
5129 goto out;
5130 }
5131
5132 qp_attr->qp_state = qp->state;
5133 qp_attr->cur_qp_state = qp_attr->qp_state;
5134 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
5135 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
5136
5137 if (!ibqp->uobject) {
5138 qp_attr->cap.max_send_wr = qp->sq.max_post;
5139 qp_attr->cap.max_send_sge = qp->sq.max_gs;
5140 qp_init_attr->qp_context = ibqp->qp_context;
5141 } else {
5142 qp_attr->cap.max_send_wr = 0;
5143 qp_attr->cap.max_send_sge = 0;
5144 }
5145
5146 qp_init_attr->qp_type = ibqp->qp_type;
5147 qp_init_attr->recv_cq = ibqp->recv_cq;
5148 qp_init_attr->send_cq = ibqp->send_cq;
5149 qp_init_attr->srq = ibqp->srq;
5150 qp_attr->cap.max_inline_data = qp->max_inline_data;
5151
5152 qp_init_attr->cap = qp_attr->cap;
5153
5154 qp_init_attr->create_flags = 0;
5155 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
5156 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
5157
5158 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
5159 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
5160 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
5161 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
5162 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
5163 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
5164 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
5165 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
5166
5167 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
5168 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
5169
5170 out:
5171 mutex_unlock(&qp->mutex);
5172 return err;
5173 }
5174
5175 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
5176 struct ib_ucontext *context,
5177 struct ib_udata *udata)
5178 {
5179 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5180 struct mlx5_ib_xrcd *xrcd;
5181 int err;
5182
5183 if (!MLX5_CAP_GEN(dev->mdev, xrc))
5184 return ERR_PTR(-ENOSYS);
5185
5186 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
5187 if (!xrcd)
5188 return ERR_PTR(-ENOMEM);
5189
5190 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
5191 if (err) {
5192 kfree(xrcd);
5193 return ERR_PTR(-ENOMEM);
5194 }
5195
5196 return &xrcd->ibxrcd;
5197 }
5198
5199 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
5200 {
5201 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
5202 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
5203 int err;
5204
5205 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
5206 if (err)
5207 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
5208
5209 kfree(xrcd);
5210 return 0;
5211 }
5212
5213 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
5214 {
5215 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
5216 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
5217 struct ib_event event;
5218
5219 if (rwq->ibwq.event_handler) {
5220 event.device = rwq->ibwq.device;
5221 event.element.wq = &rwq->ibwq;
5222 switch (type) {
5223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
5224 event.event = IB_EVENT_WQ_FATAL;
5225 break;
5226 default:
5227 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
5228 return;
5229 }
5230
5231 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
5232 }
5233 }
5234
5235 static int set_delay_drop(struct mlx5_ib_dev *dev)
5236 {
5237 int err = 0;
5238
5239 mutex_lock(&dev->delay_drop.lock);
5240 if (dev->delay_drop.activate)
5241 goto out;
5242
5243 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
5244 if (err)
5245 goto out;
5246
5247 dev->delay_drop.activate = true;
5248 out:
5249 mutex_unlock(&dev->delay_drop.lock);
5250
5251 if (!err)
5252 atomic_inc(&dev->delay_drop.rqs_cnt);
5253 return err;
5254 }
5255
5256 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
5257 struct ib_wq_init_attr *init_attr)
5258 {
5259 struct mlx5_ib_dev *dev;
5260 int has_net_offloads;
5261 __be64 *rq_pas0;
5262 void *in;
5263 void *rqc;
5264 void *wq;
5265 int inlen;
5266 int err;
5267
5268 dev = to_mdev(pd->device);
5269
5270 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
5271 in = kvzalloc(inlen, GFP_KERNEL);
5272 if (!in)
5273 return -ENOMEM;
5274
5275 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
5276 MLX5_SET(rqc, rqc, mem_rq_type,
5277 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
5278 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
5279 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
5280 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
5281 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
5282 wq = MLX5_ADDR_OF(rqc, rqc, wq);
5283 MLX5_SET(wq, wq, wq_type,
5284 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
5285 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
5286 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5287 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
5288 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
5289 err = -EOPNOTSUPP;
5290 goto out;
5291 } else {
5292 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
5293 }
5294 }
5295 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
5296 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
5297 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
5298 MLX5_SET(wq, wq, log_wqe_stride_size,
5299 rwq->single_stride_log_num_of_bytes -
5300 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
5301 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
5302 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
5303 }
5304 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
5305 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
5306 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
5307 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
5308 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
5309 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
5310 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
5311 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5312 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5313 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
5314 err = -EOPNOTSUPP;
5315 goto out;
5316 }
5317 } else {
5318 MLX5_SET(rqc, rqc, vsd, 1);
5319 }
5320 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
5321 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
5322 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
5323 err = -EOPNOTSUPP;
5324 goto out;
5325 }
5326 MLX5_SET(rqc, rqc, scatter_fcs, 1);
5327 }
5328 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5329 if (!(dev->ib_dev.attrs.raw_packet_caps &
5330 IB_RAW_PACKET_CAP_DELAY_DROP)) {
5331 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
5332 err = -EOPNOTSUPP;
5333 goto out;
5334 }
5335 MLX5_SET(rqc, rqc, delay_drop_en, 1);
5336 }
5337 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
5338 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
5339 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
5340 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
5341 err = set_delay_drop(dev);
5342 if (err) {
5343 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
5344 err);
5345 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5346 } else {
5347 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
5348 }
5349 }
5350 out:
5351 kvfree(in);
5352 return err;
5353 }
5354
5355 static int set_user_rq_size(struct mlx5_ib_dev *dev,
5356 struct ib_wq_init_attr *wq_init_attr,
5357 struct mlx5_ib_create_wq *ucmd,
5358 struct mlx5_ib_rwq *rwq)
5359 {
5360 /* Sanity check RQ size before proceeding */
5361 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
5362 return -EINVAL;
5363
5364 if (!ucmd->rq_wqe_count)
5365 return -EINVAL;
5366
5367 rwq->wqe_count = ucmd->rq_wqe_count;
5368 rwq->wqe_shift = ucmd->rq_wqe_shift;
5369 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
5370 rwq->log_rq_stride = rwq->wqe_shift;
5371 rwq->log_rq_size = ilog2(rwq->wqe_count);
5372 return 0;
5373 }
5374
5375 static int prepare_user_rq(struct ib_pd *pd,
5376 struct ib_wq_init_attr *init_attr,
5377 struct ib_udata *udata,
5378 struct mlx5_ib_rwq *rwq)
5379 {
5380 struct mlx5_ib_dev *dev = to_mdev(pd->device);
5381 struct mlx5_ib_create_wq ucmd = {};
5382 int err;
5383 size_t required_cmd_sz;
5384
5385 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
5386 + sizeof(ucmd.single_stride_log_num_of_bytes);
5387 if (udata->inlen < required_cmd_sz) {
5388 mlx5_ib_dbg(dev, "invalid inlen\n");
5389 return -EINVAL;
5390 }
5391
5392 if (udata->inlen > sizeof(ucmd) &&
5393 !ib_is_udata_cleared(udata, sizeof(ucmd),
5394 udata->inlen - sizeof(ucmd))) {
5395 mlx5_ib_dbg(dev, "inlen is not supported\n");
5396 return -EOPNOTSUPP;
5397 }
5398
5399 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
5400 mlx5_ib_dbg(dev, "copy failed\n");
5401 return -EFAULT;
5402 }
5403
5404 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
5405 mlx5_ib_dbg(dev, "invalid comp mask\n");
5406 return -EOPNOTSUPP;
5407 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
5408 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
5409 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
5410 return -EOPNOTSUPP;
5411 }
5412 if ((ucmd.single_stride_log_num_of_bytes <
5413 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
5414 (ucmd.single_stride_log_num_of_bytes >
5415 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
5416 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
5417 ucmd.single_stride_log_num_of_bytes,
5418 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
5419 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
5420 return -EINVAL;
5421 }
5422 if ((ucmd.single_wqe_log_num_of_strides >
5423 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
5424 (ucmd.single_wqe_log_num_of_strides <
5425 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
5426 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
5427 ucmd.single_wqe_log_num_of_strides,
5428 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
5429 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
5430 return -EINVAL;
5431 }
5432 rwq->single_stride_log_num_of_bytes =
5433 ucmd.single_stride_log_num_of_bytes;
5434 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
5435 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
5436 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
5437 }
5438
5439 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
5440 if (err) {
5441 mlx5_ib_dbg(dev, "err %d\n", err);
5442 return err;
5443 }
5444
5445 err = create_user_rq(dev, pd, rwq, &ucmd);
5446 if (err) {
5447 mlx5_ib_dbg(dev, "err %d\n", err);
5448 if (err)
5449 return err;
5450 }
5451
5452 rwq->user_index = ucmd.user_index;
5453 return 0;
5454 }
5455
5456 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
5457 struct ib_wq_init_attr *init_attr,
5458 struct ib_udata *udata)
5459 {
5460 struct mlx5_ib_dev *dev;
5461 struct mlx5_ib_rwq *rwq;
5462 struct mlx5_ib_create_wq_resp resp = {};
5463 size_t min_resp_len;
5464 int err;
5465
5466 if (!udata)
5467 return ERR_PTR(-ENOSYS);
5468
5469 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5470 if (udata->outlen && udata->outlen < min_resp_len)
5471 return ERR_PTR(-EINVAL);
5472
5473 dev = to_mdev(pd->device);
5474 switch (init_attr->wq_type) {
5475 case IB_WQT_RQ:
5476 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
5477 if (!rwq)
5478 return ERR_PTR(-ENOMEM);
5479 err = prepare_user_rq(pd, init_attr, udata, rwq);
5480 if (err)
5481 goto err;
5482 err = create_rq(rwq, pd, init_attr);
5483 if (err)
5484 goto err_user_rq;
5485 break;
5486 default:
5487 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
5488 init_attr->wq_type);
5489 return ERR_PTR(-EINVAL);
5490 }
5491
5492 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5493 rwq->ibwq.state = IB_WQS_RESET;
5494 if (udata->outlen) {
5495 resp.response_length = offsetof(typeof(resp), response_length) +
5496 sizeof(resp.response_length);
5497 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5498 if (err)
5499 goto err_copy;
5500 }
5501
5502 rwq->core_qp.event = mlx5_ib_wq_event;
5503 rwq->ibwq.event_handler = init_attr->event_handler;
5504 return &rwq->ibwq;
5505
5506 err_copy:
5507 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5508 err_user_rq:
5509 destroy_user_rq(dev, pd, rwq);
5510 err:
5511 kfree(rwq);
5512 return ERR_PTR(err);
5513 }
5514
5515 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5516 {
5517 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5518 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5519
5520 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5521 destroy_user_rq(dev, wq->pd, rwq);
5522 kfree(rwq);
5523
5524 return 0;
5525 }
5526
5527 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5528 struct ib_rwq_ind_table_init_attr *init_attr,
5529 struct ib_udata *udata)
5530 {
5531 struct mlx5_ib_dev *dev = to_mdev(device);
5532 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5533 int sz = 1 << init_attr->log_ind_tbl_size;
5534 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5535 size_t min_resp_len;
5536 int inlen;
5537 int err;
5538 int i;
5539 u32 *in;
5540 void *rqtc;
5541
5542 if (udata->inlen > 0 &&
5543 !ib_is_udata_cleared(udata, 0,
5544 udata->inlen))
5545 return ERR_PTR(-EOPNOTSUPP);
5546
5547 if (init_attr->log_ind_tbl_size >
5548 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5549 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5550 init_attr->log_ind_tbl_size,
5551 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5552 return ERR_PTR(-EINVAL);
5553 }
5554
5555 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5556 if (udata->outlen && udata->outlen < min_resp_len)
5557 return ERR_PTR(-EINVAL);
5558
5559 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5560 if (!rwq_ind_tbl)
5561 return ERR_PTR(-ENOMEM);
5562
5563 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5564 in = kvzalloc(inlen, GFP_KERNEL);
5565 if (!in) {
5566 err = -ENOMEM;
5567 goto err;
5568 }
5569
5570 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5571
5572 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5573 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5574
5575 for (i = 0; i < sz; i++)
5576 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5577
5578 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5579 kvfree(in);
5580
5581 if (err)
5582 goto err;
5583
5584 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5585 if (udata->outlen) {
5586 resp.response_length = offsetof(typeof(resp), response_length) +
5587 sizeof(resp.response_length);
5588 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5589 if (err)
5590 goto err_copy;
5591 }
5592
5593 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5594
5595 err_copy:
5596 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5597 err:
5598 kfree(rwq_ind_tbl);
5599 return ERR_PTR(err);
5600 }
5601
5602 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5603 {
5604 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5605 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5606
5607 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5608
5609 kfree(rwq_ind_tbl);
5610 return 0;
5611 }
5612
5613 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5614 u32 wq_attr_mask, struct ib_udata *udata)
5615 {
5616 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5617 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5618 struct mlx5_ib_modify_wq ucmd = {};
5619 size_t required_cmd_sz;
5620 int curr_wq_state;
5621 int wq_state;
5622 int inlen;
5623 int err;
5624 void *rqc;
5625 void *in;
5626
5627 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5628 if (udata->inlen < required_cmd_sz)
5629 return -EINVAL;
5630
5631 if (udata->inlen > sizeof(ucmd) &&
5632 !ib_is_udata_cleared(udata, sizeof(ucmd),
5633 udata->inlen - sizeof(ucmd)))
5634 return -EOPNOTSUPP;
5635
5636 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5637 return -EFAULT;
5638
5639 if (ucmd.comp_mask || ucmd.reserved)
5640 return -EOPNOTSUPP;
5641
5642 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5643 in = kvzalloc(inlen, GFP_KERNEL);
5644 if (!in)
5645 return -ENOMEM;
5646
5647 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5648
5649 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5650 wq_attr->curr_wq_state : wq->state;
5651 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5652 wq_attr->wq_state : curr_wq_state;
5653 if (curr_wq_state == IB_WQS_ERR)
5654 curr_wq_state = MLX5_RQC_STATE_ERR;
5655 if (wq_state == IB_WQS_ERR)
5656 wq_state = MLX5_RQC_STATE_ERR;
5657 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5658 MLX5_SET(rqc, rqc, state, wq_state);
5659
5660 if (wq_attr_mask & IB_WQ_FLAGS) {
5661 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5662 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5663 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5664 mlx5_ib_dbg(dev, "VLAN offloads are not "
5665 "supported\n");
5666 err = -EOPNOTSUPP;
5667 goto out;
5668 }
5669 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5670 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5671 MLX5_SET(rqc, rqc, vsd,
5672 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5673 }
5674
5675 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5676 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5677 err = -EOPNOTSUPP;
5678 goto out;
5679 }
5680 }
5681
5682 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5683 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5684 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5685 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5686 MLX5_SET(rqc, rqc, counter_set_id,
5687 dev->port->cnts.set_id);
5688 } else
5689 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5690 dev->ib_dev.name);
5691 }
5692
5693 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5694 if (!err)
5695 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5696
5697 out:
5698 kvfree(in);
5699 return err;
5700 }
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git