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[thirdparty/linux.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #define pr_fmt(fmt) "AMD-Vi: " fmt
21 #define dev_fmt(fmt) pr_fmt(fmt)
22
23 #include <linux/ratelimit.h>
24 #include <linux/pci.h>
25 #include <linux/acpi.h>
26 #include <linux/amba/bus.h>
27 #include <linux/platform_device.h>
28 #include <linux/pci-ats.h>
29 #include <linux/bitmap.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <linux/scatterlist.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/dma-direct.h>
35 #include <linux/iommu-helper.h>
36 #include <linux/iommu.h>
37 #include <linux/delay.h>
38 #include <linux/amd-iommu.h>
39 #include <linux/notifier.h>
40 #include <linux/export.h>
41 #include <linux/irq.h>
42 #include <linux/msi.h>
43 #include <linux/dma-contiguous.h>
44 #include <linux/irqdomain.h>
45 #include <linux/percpu.h>
46 #include <linux/iova.h>
47 #include <asm/irq_remapping.h>
48 #include <asm/io_apic.h>
49 #include <asm/apic.h>
50 #include <asm/hw_irq.h>
51 #include <asm/msidef.h>
52 #include <asm/proto.h>
53 #include <asm/iommu.h>
54 #include <asm/gart.h>
55 #include <asm/dma.h>
56
57 #include "amd_iommu_proto.h"
58 #include "amd_iommu_types.h"
59 #include "irq_remapping.h"
60
61 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
62
63 #define LOOP_TIMEOUT 100000
64
65 /* IO virtual address start page frame number */
66 #define IOVA_START_PFN (1)
67 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
68
69 /* Reserved IOVA ranges */
70 #define MSI_RANGE_START (0xfee00000)
71 #define MSI_RANGE_END (0xfeefffff)
72 #define HT_RANGE_START (0xfd00000000ULL)
73 #define HT_RANGE_END (0xffffffffffULL)
74
75 /*
76 * This bitmap is used to advertise the page sizes our hardware support
77 * to the IOMMU core, which will then use this information to split
78 * physically contiguous memory regions it is mapping into page sizes
79 * that we support.
80 *
81 * 512GB Pages are not supported due to a hardware bug
82 */
83 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84
85 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
86 static DEFINE_SPINLOCK(pd_bitmap_lock);
87
88 /* List of all available dev_data structures */
89 static LLIST_HEAD(dev_data_list);
90
91 LIST_HEAD(ioapic_map);
92 LIST_HEAD(hpet_map);
93 LIST_HEAD(acpihid_map);
94
95 /*
96 * Domain for untranslated devices - only allocated
97 * if iommu=pt passed on kernel cmd line.
98 */
99 const struct iommu_ops amd_iommu_ops;
100
101 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
102 int amd_iommu_max_glx_val = -1;
103
104 static const struct dma_map_ops amd_iommu_dma_ops;
105
106 /*
107 * general struct to manage commands send to an IOMMU
108 */
109 struct iommu_cmd {
110 u32 data[4];
111 };
112
113 struct kmem_cache *amd_iommu_irq_cache;
114
115 static void update_domain(struct protection_domain *domain);
116 static int protection_domain_init(struct protection_domain *domain);
117 static void detach_device(struct device *dev);
118 static void iova_domain_flush_tlb(struct iova_domain *iovad);
119
120 /*
121 * Data container for a dma_ops specific protection domain
122 */
123 struct dma_ops_domain {
124 /* generic protection domain information */
125 struct protection_domain domain;
126
127 /* IOVA RB-Tree */
128 struct iova_domain iovad;
129 };
130
131 static struct iova_domain reserved_iova_ranges;
132 static struct lock_class_key reserved_rbtree_key;
133
134 /****************************************************************************
135 *
136 * Helper functions
137 *
138 ****************************************************************************/
139
140 static inline int match_hid_uid(struct device *dev,
141 struct acpihid_map_entry *entry)
142 {
143 struct acpi_device *adev = ACPI_COMPANION(dev);
144 const char *hid, *uid;
145
146 if (!adev)
147 return -ENODEV;
148
149 hid = acpi_device_hid(adev);
150 uid = acpi_device_uid(adev);
151
152 if (!hid || !(*hid))
153 return -ENODEV;
154
155 if (!uid || !(*uid))
156 return strcmp(hid, entry->hid);
157
158 if (!(*entry->uid))
159 return strcmp(hid, entry->hid);
160
161 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
162 }
163
164 static inline u16 get_pci_device_id(struct device *dev)
165 {
166 struct pci_dev *pdev = to_pci_dev(dev);
167
168 return pci_dev_id(pdev);
169 }
170
171 static inline int get_acpihid_device_id(struct device *dev,
172 struct acpihid_map_entry **entry)
173 {
174 struct acpihid_map_entry *p;
175
176 list_for_each_entry(p, &acpihid_map, list) {
177 if (!match_hid_uid(dev, p)) {
178 if (entry)
179 *entry = p;
180 return p->devid;
181 }
182 }
183 return -EINVAL;
184 }
185
186 static inline int get_device_id(struct device *dev)
187 {
188 int devid;
189
190 if (dev_is_pci(dev))
191 devid = get_pci_device_id(dev);
192 else
193 devid = get_acpihid_device_id(dev, NULL);
194
195 return devid;
196 }
197
198 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
199 {
200 return container_of(dom, struct protection_domain, domain);
201 }
202
203 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
204 {
205 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
206 return container_of(domain, struct dma_ops_domain, domain);
207 }
208
209 static struct iommu_dev_data *alloc_dev_data(u16 devid)
210 {
211 struct iommu_dev_data *dev_data;
212
213 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
214 if (!dev_data)
215 return NULL;
216
217 dev_data->devid = devid;
218 ratelimit_default_init(&dev_data->rs);
219
220 llist_add(&dev_data->dev_data_list, &dev_data_list);
221 return dev_data;
222 }
223
224 static struct iommu_dev_data *search_dev_data(u16 devid)
225 {
226 struct iommu_dev_data *dev_data;
227 struct llist_node *node;
228
229 if (llist_empty(&dev_data_list))
230 return NULL;
231
232 node = dev_data_list.first;
233 llist_for_each_entry(dev_data, node, dev_data_list) {
234 if (dev_data->devid == devid)
235 return dev_data;
236 }
237
238 return NULL;
239 }
240
241 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
242 {
243 *(u16 *)data = alias;
244 return 0;
245 }
246
247 static u16 get_alias(struct device *dev)
248 {
249 struct pci_dev *pdev = to_pci_dev(dev);
250 u16 devid, ivrs_alias, pci_alias;
251
252 /* The callers make sure that get_device_id() does not fail here */
253 devid = get_device_id(dev);
254
255 /* For ACPI HID devices, we simply return the devid as such */
256 if (!dev_is_pci(dev))
257 return devid;
258
259 ivrs_alias = amd_iommu_alias_table[devid];
260
261 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
262
263 if (ivrs_alias == pci_alias)
264 return ivrs_alias;
265
266 /*
267 * DMA alias showdown
268 *
269 * The IVRS is fairly reliable in telling us about aliases, but it
270 * can't know about every screwy device. If we don't have an IVRS
271 * reported alias, use the PCI reported alias. In that case we may
272 * still need to initialize the rlookup and dev_table entries if the
273 * alias is to a non-existent device.
274 */
275 if (ivrs_alias == devid) {
276 if (!amd_iommu_rlookup_table[pci_alias]) {
277 amd_iommu_rlookup_table[pci_alias] =
278 amd_iommu_rlookup_table[devid];
279 memcpy(amd_iommu_dev_table[pci_alias].data,
280 amd_iommu_dev_table[devid].data,
281 sizeof(amd_iommu_dev_table[pci_alias].data));
282 }
283
284 return pci_alias;
285 }
286
287 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
288 "for device [%04x:%04x], kernel reported alias "
289 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
290 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
291 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
292 PCI_FUNC(pci_alias));
293
294 /*
295 * If we don't have a PCI DMA alias and the IVRS alias is on the same
296 * bus, then the IVRS table may know about a quirk that we don't.
297 */
298 if (pci_alias == devid &&
299 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
300 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
301 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
302 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
303 }
304
305 return ivrs_alias;
306 }
307
308 static struct iommu_dev_data *find_dev_data(u16 devid)
309 {
310 struct iommu_dev_data *dev_data;
311 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
312
313 dev_data = search_dev_data(devid);
314
315 if (dev_data == NULL) {
316 dev_data = alloc_dev_data(devid);
317 if (!dev_data)
318 return NULL;
319
320 if (translation_pre_enabled(iommu))
321 dev_data->defer_attach = true;
322 }
323
324 return dev_data;
325 }
326
327 struct iommu_dev_data *get_dev_data(struct device *dev)
328 {
329 return dev->archdata.iommu;
330 }
331 EXPORT_SYMBOL(get_dev_data);
332
333 /*
334 * Find or create an IOMMU group for a acpihid device.
335 */
336 static struct iommu_group *acpihid_device_group(struct device *dev)
337 {
338 struct acpihid_map_entry *p, *entry = NULL;
339 int devid;
340
341 devid = get_acpihid_device_id(dev, &entry);
342 if (devid < 0)
343 return ERR_PTR(devid);
344
345 list_for_each_entry(p, &acpihid_map, list) {
346 if ((devid == p->devid) && p->group)
347 entry->group = p->group;
348 }
349
350 if (!entry->group)
351 entry->group = generic_device_group(dev);
352 else
353 iommu_group_ref_get(entry->group);
354
355 return entry->group;
356 }
357
358 static bool pci_iommuv2_capable(struct pci_dev *pdev)
359 {
360 static const int caps[] = {
361 PCI_EXT_CAP_ID_ATS,
362 PCI_EXT_CAP_ID_PRI,
363 PCI_EXT_CAP_ID_PASID,
364 };
365 int i, pos;
366
367 if (pci_ats_disabled())
368 return false;
369
370 for (i = 0; i < 3; ++i) {
371 pos = pci_find_ext_capability(pdev, caps[i]);
372 if (pos == 0)
373 return false;
374 }
375
376 return true;
377 }
378
379 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
380 {
381 struct iommu_dev_data *dev_data;
382
383 dev_data = get_dev_data(&pdev->dev);
384
385 return dev_data->errata & (1 << erratum) ? true : false;
386 }
387
388 /*
389 * This function checks if the driver got a valid device from the caller to
390 * avoid dereferencing invalid pointers.
391 */
392 static bool check_device(struct device *dev)
393 {
394 int devid;
395
396 if (!dev || !dev->dma_mask)
397 return false;
398
399 devid = get_device_id(dev);
400 if (devid < 0)
401 return false;
402
403 /* Out of our scope? */
404 if (devid > amd_iommu_last_bdf)
405 return false;
406
407 if (amd_iommu_rlookup_table[devid] == NULL)
408 return false;
409
410 return true;
411 }
412
413 static void init_iommu_group(struct device *dev)
414 {
415 struct iommu_group *group;
416
417 group = iommu_group_get_for_dev(dev);
418 if (IS_ERR(group))
419 return;
420
421 iommu_group_put(group);
422 }
423
424 static int iommu_init_device(struct device *dev)
425 {
426 struct iommu_dev_data *dev_data;
427 struct amd_iommu *iommu;
428 int devid;
429
430 if (dev->archdata.iommu)
431 return 0;
432
433 devid = get_device_id(dev);
434 if (devid < 0)
435 return devid;
436
437 iommu = amd_iommu_rlookup_table[devid];
438
439 dev_data = find_dev_data(devid);
440 if (!dev_data)
441 return -ENOMEM;
442
443 dev_data->alias = get_alias(dev);
444
445 /*
446 * By default we use passthrough mode for IOMMUv2 capable device.
447 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
448 * invalid address), we ignore the capability for the device so
449 * it'll be forced to go into translation mode.
450 */
451 if ((iommu_pass_through || !amd_iommu_force_isolation) &&
452 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
453 struct amd_iommu *iommu;
454
455 iommu = amd_iommu_rlookup_table[dev_data->devid];
456 dev_data->iommu_v2 = iommu->is_iommu_v2;
457 }
458
459 dev->archdata.iommu = dev_data;
460
461 iommu_device_link(&iommu->iommu, dev);
462
463 return 0;
464 }
465
466 static void iommu_ignore_device(struct device *dev)
467 {
468 u16 alias;
469 int devid;
470
471 devid = get_device_id(dev);
472 if (devid < 0)
473 return;
474
475 alias = get_alias(dev);
476
477 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
478 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
479
480 amd_iommu_rlookup_table[devid] = NULL;
481 amd_iommu_rlookup_table[alias] = NULL;
482 }
483
484 static void iommu_uninit_device(struct device *dev)
485 {
486 struct iommu_dev_data *dev_data;
487 struct amd_iommu *iommu;
488 int devid;
489
490 devid = get_device_id(dev);
491 if (devid < 0)
492 return;
493
494 iommu = amd_iommu_rlookup_table[devid];
495
496 dev_data = search_dev_data(devid);
497 if (!dev_data)
498 return;
499
500 if (dev_data->domain)
501 detach_device(dev);
502
503 iommu_device_unlink(&iommu->iommu, dev);
504
505 iommu_group_remove_device(dev);
506
507 /* Remove dma-ops */
508 dev->dma_ops = NULL;
509
510 /*
511 * We keep dev_data around for unplugged devices and reuse it when the
512 * device is re-plugged - not doing so would introduce a ton of races.
513 */
514 }
515
516 /****************************************************************************
517 *
518 * Interrupt handling functions
519 *
520 ****************************************************************************/
521
522 static void dump_dte_entry(u16 devid)
523 {
524 int i;
525
526 for (i = 0; i < 4; ++i)
527 pr_err("DTE[%d]: %016llx\n", i,
528 amd_iommu_dev_table[devid].data[i]);
529 }
530
531 static void dump_command(unsigned long phys_addr)
532 {
533 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
534 int i;
535
536 for (i = 0; i < 4; ++i)
537 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
538 }
539
540 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
541 u64 address, int flags)
542 {
543 struct iommu_dev_data *dev_data = NULL;
544 struct pci_dev *pdev;
545
546 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
547 devid & 0xff);
548 if (pdev)
549 dev_data = get_dev_data(&pdev->dev);
550
551 if (dev_data && __ratelimit(&dev_data->rs)) {
552 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
553 domain_id, address, flags);
554 } else if (printk_ratelimit()) {
555 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
556 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
557 domain_id, address, flags);
558 }
559
560 if (pdev)
561 pci_dev_put(pdev);
562 }
563
564 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
565 {
566 struct device *dev = iommu->iommu.dev;
567 int type, devid, pasid, flags, tag;
568 volatile u32 *event = __evt;
569 int count = 0;
570 u64 address;
571
572 retry:
573 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
574 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
575 pasid = PPR_PASID(*(u64 *)&event[0]);
576 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
577 address = (u64)(((u64)event[3]) << 32) | event[2];
578
579 if (type == 0) {
580 /* Did we hit the erratum? */
581 if (++count == LOOP_TIMEOUT) {
582 pr_err("No event written to event log\n");
583 return;
584 }
585 udelay(1);
586 goto retry;
587 }
588
589 if (type == EVENT_TYPE_IO_FAULT) {
590 amd_iommu_report_page_fault(devid, pasid, address, flags);
591 return;
592 }
593
594 switch (type) {
595 case EVENT_TYPE_ILL_DEV:
596 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
599 dump_dte_entry(devid);
600 break;
601 case EVENT_TYPE_DEV_TAB_ERR:
602 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
603 "address=0x%llx flags=0x%04x]\n",
604 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
605 address, flags);
606 break;
607 case EVENT_TYPE_PAGE_TAB_ERR:
608 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
609 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
610 pasid, address, flags);
611 break;
612 case EVENT_TYPE_ILL_CMD:
613 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
614 dump_command(address);
615 break;
616 case EVENT_TYPE_CMD_HARD_ERR:
617 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
618 address, flags);
619 break;
620 case EVENT_TYPE_IOTLB_INV_TO:
621 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
622 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
623 address);
624 break;
625 case EVENT_TYPE_INV_DEV_REQ:
626 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 pasid, address, flags);
629 break;
630 case EVENT_TYPE_INV_PPR_REQ:
631 pasid = ((event[0] >> 16) & 0xFFFF)
632 | ((event[1] << 6) & 0xF0000);
633 tag = event[1] & 0x03FF;
634 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
635 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
636 pasid, address, flags);
637 break;
638 default:
639 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
640 event[0], event[1], event[2], event[3]);
641 }
642
643 memset(__evt, 0, 4 * sizeof(u32));
644 }
645
646 static void iommu_poll_events(struct amd_iommu *iommu)
647 {
648 u32 head, tail;
649
650 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
651 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
652
653 while (head != tail) {
654 iommu_print_event(iommu, iommu->evt_buf + head);
655 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
656 }
657
658 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
659 }
660
661 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
662 {
663 struct amd_iommu_fault fault;
664
665 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
666 pr_err_ratelimited("Unknown PPR request received\n");
667 return;
668 }
669
670 fault.address = raw[1];
671 fault.pasid = PPR_PASID(raw[0]);
672 fault.device_id = PPR_DEVID(raw[0]);
673 fault.tag = PPR_TAG(raw[0]);
674 fault.flags = PPR_FLAGS(raw[0]);
675
676 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
677 }
678
679 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
680 {
681 u32 head, tail;
682
683 if (iommu->ppr_log == NULL)
684 return;
685
686 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
687 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
688
689 while (head != tail) {
690 volatile u64 *raw;
691 u64 entry[2];
692 int i;
693
694 raw = (u64 *)(iommu->ppr_log + head);
695
696 /*
697 * Hardware bug: Interrupt may arrive before the entry is
698 * written to memory. If this happens we need to wait for the
699 * entry to arrive.
700 */
701 for (i = 0; i < LOOP_TIMEOUT; ++i) {
702 if (PPR_REQ_TYPE(raw[0]) != 0)
703 break;
704 udelay(1);
705 }
706
707 /* Avoid memcpy function-call overhead */
708 entry[0] = raw[0];
709 entry[1] = raw[1];
710
711 /*
712 * To detect the hardware bug we need to clear the entry
713 * back to zero.
714 */
715 raw[0] = raw[1] = 0UL;
716
717 /* Update head pointer of hardware ring-buffer */
718 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
719 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
720
721 /* Handle PPR entry */
722 iommu_handle_ppr_entry(iommu, entry);
723
724 /* Refresh ring-buffer information */
725 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
726 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
727 }
728 }
729
730 #ifdef CONFIG_IRQ_REMAP
731 static int (*iommu_ga_log_notifier)(u32);
732
733 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
734 {
735 iommu_ga_log_notifier = notifier;
736
737 return 0;
738 }
739 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
740
741 static void iommu_poll_ga_log(struct amd_iommu *iommu)
742 {
743 u32 head, tail, cnt = 0;
744
745 if (iommu->ga_log == NULL)
746 return;
747
748 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
749 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
750
751 while (head != tail) {
752 volatile u64 *raw;
753 u64 log_entry;
754
755 raw = (u64 *)(iommu->ga_log + head);
756 cnt++;
757
758 /* Avoid memcpy function-call overhead */
759 log_entry = *raw;
760
761 /* Update head pointer of hardware ring-buffer */
762 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
763 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
764
765 /* Handle GA entry */
766 switch (GA_REQ_TYPE(log_entry)) {
767 case GA_GUEST_NR:
768 if (!iommu_ga_log_notifier)
769 break;
770
771 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
772 __func__, GA_DEVID(log_entry),
773 GA_TAG(log_entry));
774
775 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
776 pr_err("GA log notifier failed.\n");
777 break;
778 default:
779 break;
780 }
781 }
782 }
783 #endif /* CONFIG_IRQ_REMAP */
784
785 #define AMD_IOMMU_INT_MASK \
786 (MMIO_STATUS_EVT_INT_MASK | \
787 MMIO_STATUS_PPR_INT_MASK | \
788 MMIO_STATUS_GALOG_INT_MASK)
789
790 irqreturn_t amd_iommu_int_thread(int irq, void *data)
791 {
792 struct amd_iommu *iommu = (struct amd_iommu *) data;
793 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
794
795 while (status & AMD_IOMMU_INT_MASK) {
796 /* Enable EVT and PPR and GA interrupts again */
797 writel(AMD_IOMMU_INT_MASK,
798 iommu->mmio_base + MMIO_STATUS_OFFSET);
799
800 if (status & MMIO_STATUS_EVT_INT_MASK) {
801 pr_devel("Processing IOMMU Event Log\n");
802 iommu_poll_events(iommu);
803 }
804
805 if (status & MMIO_STATUS_PPR_INT_MASK) {
806 pr_devel("Processing IOMMU PPR Log\n");
807 iommu_poll_ppr_log(iommu);
808 }
809
810 #ifdef CONFIG_IRQ_REMAP
811 if (status & MMIO_STATUS_GALOG_INT_MASK) {
812 pr_devel("Processing IOMMU GA Log\n");
813 iommu_poll_ga_log(iommu);
814 }
815 #endif
816
817 /*
818 * Hardware bug: ERBT1312
819 * When re-enabling interrupt (by writing 1
820 * to clear the bit), the hardware might also try to set
821 * the interrupt bit in the event status register.
822 * In this scenario, the bit will be set, and disable
823 * subsequent interrupts.
824 *
825 * Workaround: The IOMMU driver should read back the
826 * status register and check if the interrupt bits are cleared.
827 * If not, driver will need to go through the interrupt handler
828 * again and re-clear the bits
829 */
830 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
831 }
832 return IRQ_HANDLED;
833 }
834
835 irqreturn_t amd_iommu_int_handler(int irq, void *data)
836 {
837 return IRQ_WAKE_THREAD;
838 }
839
840 /****************************************************************************
841 *
842 * IOMMU command queuing functions
843 *
844 ****************************************************************************/
845
846 static int wait_on_sem(volatile u64 *sem)
847 {
848 int i = 0;
849
850 while (*sem == 0 && i < LOOP_TIMEOUT) {
851 udelay(1);
852 i += 1;
853 }
854
855 if (i == LOOP_TIMEOUT) {
856 pr_alert("Completion-Wait loop timed out\n");
857 return -EIO;
858 }
859
860 return 0;
861 }
862
863 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
864 struct iommu_cmd *cmd)
865 {
866 u8 *target;
867
868 target = iommu->cmd_buf + iommu->cmd_buf_tail;
869
870 iommu->cmd_buf_tail += sizeof(*cmd);
871 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
872
873 /* Copy command to buffer */
874 memcpy(target, cmd, sizeof(*cmd));
875
876 /* Tell the IOMMU about it */
877 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
878 }
879
880 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
881 {
882 u64 paddr = iommu_virt_to_phys((void *)address);
883
884 WARN_ON(address & 0x7ULL);
885
886 memset(cmd, 0, sizeof(*cmd));
887 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
888 cmd->data[1] = upper_32_bits(paddr);
889 cmd->data[2] = 1;
890 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
891 }
892
893 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
894 {
895 memset(cmd, 0, sizeof(*cmd));
896 cmd->data[0] = devid;
897 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
898 }
899
900 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
901 size_t size, u16 domid, int pde)
902 {
903 u64 pages;
904 bool s;
905
906 pages = iommu_num_pages(address, size, PAGE_SIZE);
907 s = false;
908
909 if (pages > 1) {
910 /*
911 * If we have to flush more than one page, flush all
912 * TLB entries for this domain
913 */
914 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
915 s = true;
916 }
917
918 address &= PAGE_MASK;
919
920 memset(cmd, 0, sizeof(*cmd));
921 cmd->data[1] |= domid;
922 cmd->data[2] = lower_32_bits(address);
923 cmd->data[3] = upper_32_bits(address);
924 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
925 if (s) /* size bit - we flush more than one 4kb page */
926 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
927 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
928 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
929 }
930
931 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
932 u64 address, size_t size)
933 {
934 u64 pages;
935 bool s;
936
937 pages = iommu_num_pages(address, size, PAGE_SIZE);
938 s = false;
939
940 if (pages > 1) {
941 /*
942 * If we have to flush more than one page, flush all
943 * TLB entries for this domain
944 */
945 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
946 s = true;
947 }
948
949 address &= PAGE_MASK;
950
951 memset(cmd, 0, sizeof(*cmd));
952 cmd->data[0] = devid;
953 cmd->data[0] |= (qdep & 0xff) << 24;
954 cmd->data[1] = devid;
955 cmd->data[2] = lower_32_bits(address);
956 cmd->data[3] = upper_32_bits(address);
957 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
958 if (s)
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
960 }
961
962 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
963 u64 address, bool size)
964 {
965 memset(cmd, 0, sizeof(*cmd));
966
967 address &= ~(0xfffULL);
968
969 cmd->data[0] = pasid;
970 cmd->data[1] = domid;
971 cmd->data[2] = lower_32_bits(address);
972 cmd->data[3] = upper_32_bits(address);
973 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
975 if (size)
976 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
977 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
978 }
979
980 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
981 int qdep, u64 address, bool size)
982 {
983 memset(cmd, 0, sizeof(*cmd));
984
985 address &= ~(0xfffULL);
986
987 cmd->data[0] = devid;
988 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
989 cmd->data[0] |= (qdep & 0xff) << 24;
990 cmd->data[1] = devid;
991 cmd->data[1] |= (pasid & 0xff) << 16;
992 cmd->data[2] = lower_32_bits(address);
993 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
994 cmd->data[3] = upper_32_bits(address);
995 if (size)
996 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
997 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
998 }
999
1000 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1001 int status, int tag, bool gn)
1002 {
1003 memset(cmd, 0, sizeof(*cmd));
1004
1005 cmd->data[0] = devid;
1006 if (gn) {
1007 cmd->data[1] = pasid;
1008 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1009 }
1010 cmd->data[3] = tag & 0x1ff;
1011 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1012
1013 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1014 }
1015
1016 static void build_inv_all(struct iommu_cmd *cmd)
1017 {
1018 memset(cmd, 0, sizeof(*cmd));
1019 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1020 }
1021
1022 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1023 {
1024 memset(cmd, 0, sizeof(*cmd));
1025 cmd->data[0] = devid;
1026 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1027 }
1028
1029 /*
1030 * Writes the command to the IOMMUs command buffer and informs the
1031 * hardware about the new command.
1032 */
1033 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1034 struct iommu_cmd *cmd,
1035 bool sync)
1036 {
1037 unsigned int count = 0;
1038 u32 left, next_tail;
1039
1040 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1041 again:
1042 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1043
1044 if (left <= 0x20) {
1045 /* Skip udelay() the first time around */
1046 if (count++) {
1047 if (count == LOOP_TIMEOUT) {
1048 pr_err("Command buffer timeout\n");
1049 return -EIO;
1050 }
1051
1052 udelay(1);
1053 }
1054
1055 /* Update head and recheck remaining space */
1056 iommu->cmd_buf_head = readl(iommu->mmio_base +
1057 MMIO_CMD_HEAD_OFFSET);
1058
1059 goto again;
1060 }
1061
1062 copy_cmd_to_buffer(iommu, cmd);
1063
1064 /* Do we need to make sure all commands are processed? */
1065 iommu->need_sync = sync;
1066
1067 return 0;
1068 }
1069
1070 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1071 struct iommu_cmd *cmd,
1072 bool sync)
1073 {
1074 unsigned long flags;
1075 int ret;
1076
1077 raw_spin_lock_irqsave(&iommu->lock, flags);
1078 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1079 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1080
1081 return ret;
1082 }
1083
1084 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1085 {
1086 return iommu_queue_command_sync(iommu, cmd, true);
1087 }
1088
1089 /*
1090 * This function queues a completion wait command into the command
1091 * buffer of an IOMMU
1092 */
1093 static int iommu_completion_wait(struct amd_iommu *iommu)
1094 {
1095 struct iommu_cmd cmd;
1096 unsigned long flags;
1097 int ret;
1098
1099 if (!iommu->need_sync)
1100 return 0;
1101
1102
1103 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1104
1105 raw_spin_lock_irqsave(&iommu->lock, flags);
1106
1107 iommu->cmd_sem = 0;
1108
1109 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1110 if (ret)
1111 goto out_unlock;
1112
1113 ret = wait_on_sem(&iommu->cmd_sem);
1114
1115 out_unlock:
1116 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1117
1118 return ret;
1119 }
1120
1121 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1122 {
1123 struct iommu_cmd cmd;
1124
1125 build_inv_dte(&cmd, devid);
1126
1127 return iommu_queue_command(iommu, &cmd);
1128 }
1129
1130 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1131 {
1132 u32 devid;
1133
1134 for (devid = 0; devid <= 0xffff; ++devid)
1135 iommu_flush_dte(iommu, devid);
1136
1137 iommu_completion_wait(iommu);
1138 }
1139
1140 /*
1141 * This function uses heavy locking and may disable irqs for some time. But
1142 * this is no issue because it is only called during resume.
1143 */
1144 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1145 {
1146 u32 dom_id;
1147
1148 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1149 struct iommu_cmd cmd;
1150 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1151 dom_id, 1);
1152 iommu_queue_command(iommu, &cmd);
1153 }
1154
1155 iommu_completion_wait(iommu);
1156 }
1157
1158 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1159 {
1160 struct iommu_cmd cmd;
1161
1162 build_inv_all(&cmd);
1163
1164 iommu_queue_command(iommu, &cmd);
1165 iommu_completion_wait(iommu);
1166 }
1167
1168 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1169 {
1170 struct iommu_cmd cmd;
1171
1172 build_inv_irt(&cmd, devid);
1173
1174 iommu_queue_command(iommu, &cmd);
1175 }
1176
1177 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1178 {
1179 u32 devid;
1180
1181 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1182 iommu_flush_irt(iommu, devid);
1183
1184 iommu_completion_wait(iommu);
1185 }
1186
1187 void iommu_flush_all_caches(struct amd_iommu *iommu)
1188 {
1189 if (iommu_feature(iommu, FEATURE_IA)) {
1190 amd_iommu_flush_all(iommu);
1191 } else {
1192 amd_iommu_flush_dte_all(iommu);
1193 amd_iommu_flush_irt_all(iommu);
1194 amd_iommu_flush_tlb_all(iommu);
1195 }
1196 }
1197
1198 /*
1199 * Command send function for flushing on-device TLB
1200 */
1201 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1202 u64 address, size_t size)
1203 {
1204 struct amd_iommu *iommu;
1205 struct iommu_cmd cmd;
1206 int qdep;
1207
1208 qdep = dev_data->ats.qdep;
1209 iommu = amd_iommu_rlookup_table[dev_data->devid];
1210
1211 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1212
1213 return iommu_queue_command(iommu, &cmd);
1214 }
1215
1216 /*
1217 * Command send function for invalidating a device table entry
1218 */
1219 static int device_flush_dte(struct iommu_dev_data *dev_data)
1220 {
1221 struct amd_iommu *iommu;
1222 u16 alias;
1223 int ret;
1224
1225 iommu = amd_iommu_rlookup_table[dev_data->devid];
1226 alias = dev_data->alias;
1227
1228 ret = iommu_flush_dte(iommu, dev_data->devid);
1229 if (!ret && alias != dev_data->devid)
1230 ret = iommu_flush_dte(iommu, alias);
1231 if (ret)
1232 return ret;
1233
1234 if (dev_data->ats.enabled)
1235 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1236
1237 return ret;
1238 }
1239
1240 /*
1241 * TLB invalidation function which is called from the mapping functions.
1242 * It invalidates a single PTE if the range to flush is within a single
1243 * page. Otherwise it flushes the whole TLB of the IOMMU.
1244 */
1245 static void __domain_flush_pages(struct protection_domain *domain,
1246 u64 address, size_t size, int pde)
1247 {
1248 struct iommu_dev_data *dev_data;
1249 struct iommu_cmd cmd;
1250 int ret = 0, i;
1251
1252 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1253
1254 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1255 if (!domain->dev_iommu[i])
1256 continue;
1257
1258 /*
1259 * Devices of this domain are behind this IOMMU
1260 * We need a TLB flush
1261 */
1262 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1263 }
1264
1265 list_for_each_entry(dev_data, &domain->dev_list, list) {
1266
1267 if (!dev_data->ats.enabled)
1268 continue;
1269
1270 ret |= device_flush_iotlb(dev_data, address, size);
1271 }
1272
1273 WARN_ON(ret);
1274 }
1275
1276 static void domain_flush_pages(struct protection_domain *domain,
1277 u64 address, size_t size)
1278 {
1279 __domain_flush_pages(domain, address, size, 0);
1280 }
1281
1282 /* Flush the whole IO/TLB for a given protection domain */
1283 static void domain_flush_tlb(struct protection_domain *domain)
1284 {
1285 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1286 }
1287
1288 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1289 static void domain_flush_tlb_pde(struct protection_domain *domain)
1290 {
1291 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1292 }
1293
1294 static void domain_flush_complete(struct protection_domain *domain)
1295 {
1296 int i;
1297
1298 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1299 if (domain && !domain->dev_iommu[i])
1300 continue;
1301
1302 /*
1303 * Devices of this domain are behind this IOMMU
1304 * We need to wait for completion of all commands.
1305 */
1306 iommu_completion_wait(amd_iommus[i]);
1307 }
1308 }
1309
1310
1311 /*
1312 * This function flushes the DTEs for all devices in domain
1313 */
1314 static void domain_flush_devices(struct protection_domain *domain)
1315 {
1316 struct iommu_dev_data *dev_data;
1317
1318 list_for_each_entry(dev_data, &domain->dev_list, list)
1319 device_flush_dte(dev_data);
1320 }
1321
1322 /****************************************************************************
1323 *
1324 * The functions below are used the create the page table mappings for
1325 * unity mapped regions.
1326 *
1327 ****************************************************************************/
1328
1329 static void free_page_list(struct page *freelist)
1330 {
1331 while (freelist != NULL) {
1332 unsigned long p = (unsigned long)page_address(freelist);
1333 freelist = freelist->freelist;
1334 free_page(p);
1335 }
1336 }
1337
1338 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1339 {
1340 struct page *p = virt_to_page((void *)pt);
1341
1342 p->freelist = freelist;
1343
1344 return p;
1345 }
1346
1347 #define DEFINE_FREE_PT_FN(LVL, FN) \
1348 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1349 { \
1350 unsigned long p; \
1351 u64 *pt; \
1352 int i; \
1353 \
1354 pt = (u64 *)__pt; \
1355 \
1356 for (i = 0; i < 512; ++i) { \
1357 /* PTE present? */ \
1358 if (!IOMMU_PTE_PRESENT(pt[i])) \
1359 continue; \
1360 \
1361 /* Large PTE? */ \
1362 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1363 PM_PTE_LEVEL(pt[i]) == 7) \
1364 continue; \
1365 \
1366 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1367 freelist = FN(p, freelist); \
1368 } \
1369 \
1370 return free_pt_page((unsigned long)pt, freelist); \
1371 }
1372
1373 DEFINE_FREE_PT_FN(l2, free_pt_page)
1374 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1375 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1376 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1377 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1378
1379 static struct page *free_sub_pt(unsigned long root, int mode,
1380 struct page *freelist)
1381 {
1382 switch (mode) {
1383 case PAGE_MODE_NONE:
1384 case PAGE_MODE_7_LEVEL:
1385 break;
1386 case PAGE_MODE_1_LEVEL:
1387 freelist = free_pt_page(root, freelist);
1388 break;
1389 case PAGE_MODE_2_LEVEL:
1390 freelist = free_pt_l2(root, freelist);
1391 break;
1392 case PAGE_MODE_3_LEVEL:
1393 freelist = free_pt_l3(root, freelist);
1394 break;
1395 case PAGE_MODE_4_LEVEL:
1396 freelist = free_pt_l4(root, freelist);
1397 break;
1398 case PAGE_MODE_5_LEVEL:
1399 freelist = free_pt_l5(root, freelist);
1400 break;
1401 case PAGE_MODE_6_LEVEL:
1402 freelist = free_pt_l6(root, freelist);
1403 break;
1404 default:
1405 BUG();
1406 }
1407
1408 return freelist;
1409 }
1410
1411 static void free_pagetable(struct protection_domain *domain)
1412 {
1413 unsigned long root = (unsigned long)domain->pt_root;
1414 struct page *freelist = NULL;
1415
1416 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1417 domain->mode > PAGE_MODE_6_LEVEL);
1418
1419 free_sub_pt(root, domain->mode, freelist);
1420
1421 free_page_list(freelist);
1422 }
1423
1424 /*
1425 * This function is used to add another level to an IO page table. Adding
1426 * another level increases the size of the address space by 9 bits to a size up
1427 * to 64 bits.
1428 */
1429 static bool increase_address_space(struct protection_domain *domain,
1430 gfp_t gfp)
1431 {
1432 u64 *pte;
1433
1434 if (domain->mode == PAGE_MODE_6_LEVEL)
1435 /* address space already 64 bit large */
1436 return false;
1437
1438 pte = (void *)get_zeroed_page(gfp);
1439 if (!pte)
1440 return false;
1441
1442 *pte = PM_LEVEL_PDE(domain->mode,
1443 iommu_virt_to_phys(domain->pt_root));
1444 domain->pt_root = pte;
1445 domain->mode += 1;
1446 domain->updated = true;
1447
1448 return true;
1449 }
1450
1451 static u64 *alloc_pte(struct protection_domain *domain,
1452 unsigned long address,
1453 unsigned long page_size,
1454 u64 **pte_page,
1455 gfp_t gfp)
1456 {
1457 int level, end_lvl;
1458 u64 *pte, *page;
1459
1460 BUG_ON(!is_power_of_2(page_size));
1461
1462 while (address > PM_LEVEL_SIZE(domain->mode))
1463 increase_address_space(domain, gfp);
1464
1465 level = domain->mode - 1;
1466 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1467 address = PAGE_SIZE_ALIGN(address, page_size);
1468 end_lvl = PAGE_SIZE_LEVEL(page_size);
1469
1470 while (level > end_lvl) {
1471 u64 __pte, __npte;
1472 int pte_level;
1473
1474 __pte = *pte;
1475 pte_level = PM_PTE_LEVEL(__pte);
1476
1477 if (!IOMMU_PTE_PRESENT(__pte) ||
1478 pte_level == PAGE_MODE_7_LEVEL) {
1479 page = (u64 *)get_zeroed_page(gfp);
1480 if (!page)
1481 return NULL;
1482
1483 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1484
1485 /* pte could have been changed somewhere. */
1486 if (cmpxchg64(pte, __pte, __npte) != __pte)
1487 free_page((unsigned long)page);
1488 else if (pte_level == PAGE_MODE_7_LEVEL)
1489 domain->updated = true;
1490
1491 continue;
1492 }
1493
1494 /* No level skipping support yet */
1495 if (pte_level != level)
1496 return NULL;
1497
1498 level -= 1;
1499
1500 pte = IOMMU_PTE_PAGE(__pte);
1501
1502 if (pte_page && level == end_lvl)
1503 *pte_page = pte;
1504
1505 pte = &pte[PM_LEVEL_INDEX(level, address)];
1506 }
1507
1508 return pte;
1509 }
1510
1511 /*
1512 * This function checks if there is a PTE for a given dma address. If
1513 * there is one, it returns the pointer to it.
1514 */
1515 static u64 *fetch_pte(struct protection_domain *domain,
1516 unsigned long address,
1517 unsigned long *page_size)
1518 {
1519 int level;
1520 u64 *pte;
1521
1522 *page_size = 0;
1523
1524 if (address > PM_LEVEL_SIZE(domain->mode))
1525 return NULL;
1526
1527 level = domain->mode - 1;
1528 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1529 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1530
1531 while (level > 0) {
1532
1533 /* Not Present */
1534 if (!IOMMU_PTE_PRESENT(*pte))
1535 return NULL;
1536
1537 /* Large PTE */
1538 if (PM_PTE_LEVEL(*pte) == 7 ||
1539 PM_PTE_LEVEL(*pte) == 0)
1540 break;
1541
1542 /* No level skipping support yet */
1543 if (PM_PTE_LEVEL(*pte) != level)
1544 return NULL;
1545
1546 level -= 1;
1547
1548 /* Walk to the next level */
1549 pte = IOMMU_PTE_PAGE(*pte);
1550 pte = &pte[PM_LEVEL_INDEX(level, address)];
1551 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1552 }
1553
1554 if (PM_PTE_LEVEL(*pte) == 0x07) {
1555 unsigned long pte_mask;
1556
1557 /*
1558 * If we have a series of large PTEs, make
1559 * sure to return a pointer to the first one.
1560 */
1561 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1562 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1563 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1564 }
1565
1566 return pte;
1567 }
1568
1569 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1570 {
1571 unsigned long pt;
1572 int mode;
1573
1574 while (cmpxchg64(pte, pteval, 0) != pteval) {
1575 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1576 pteval = *pte;
1577 }
1578
1579 if (!IOMMU_PTE_PRESENT(pteval))
1580 return freelist;
1581
1582 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1583 mode = IOMMU_PTE_MODE(pteval);
1584
1585 return free_sub_pt(pt, mode, freelist);
1586 }
1587
1588 /*
1589 * Generic mapping functions. It maps a physical address into a DMA
1590 * address space. It allocates the page table pages if necessary.
1591 * In the future it can be extended to a generic mapping function
1592 * supporting all features of AMD IOMMU page tables like level skipping
1593 * and full 64 bit address spaces.
1594 */
1595 static int iommu_map_page(struct protection_domain *dom,
1596 unsigned long bus_addr,
1597 unsigned long phys_addr,
1598 unsigned long page_size,
1599 int prot,
1600 gfp_t gfp)
1601 {
1602 struct page *freelist = NULL;
1603 u64 __pte, *pte;
1604 int i, count;
1605
1606 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1607 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1608
1609 if (!(prot & IOMMU_PROT_MASK))
1610 return -EINVAL;
1611
1612 count = PAGE_SIZE_PTE_COUNT(page_size);
1613 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1614
1615 if (!pte)
1616 return -ENOMEM;
1617
1618 for (i = 0; i < count; ++i)
1619 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1620
1621 if (freelist != NULL)
1622 dom->updated = true;
1623
1624 if (count > 1) {
1625 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1626 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1627 } else
1628 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1629
1630 if (prot & IOMMU_PROT_IR)
1631 __pte |= IOMMU_PTE_IR;
1632 if (prot & IOMMU_PROT_IW)
1633 __pte |= IOMMU_PTE_IW;
1634
1635 for (i = 0; i < count; ++i)
1636 pte[i] = __pte;
1637
1638 update_domain(dom);
1639
1640 /* Everything flushed out, free pages now */
1641 free_page_list(freelist);
1642
1643 return 0;
1644 }
1645
1646 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1647 unsigned long bus_addr,
1648 unsigned long page_size)
1649 {
1650 unsigned long long unmapped;
1651 unsigned long unmap_size;
1652 u64 *pte;
1653
1654 BUG_ON(!is_power_of_2(page_size));
1655
1656 unmapped = 0;
1657
1658 while (unmapped < page_size) {
1659
1660 pte = fetch_pte(dom, bus_addr, &unmap_size);
1661
1662 if (pte) {
1663 int i, count;
1664
1665 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1666 for (i = 0; i < count; i++)
1667 pte[i] = 0ULL;
1668 }
1669
1670 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1671 unmapped += unmap_size;
1672 }
1673
1674 BUG_ON(unmapped && !is_power_of_2(unmapped));
1675
1676 return unmapped;
1677 }
1678
1679 /****************************************************************************
1680 *
1681 * The next functions belong to the address allocator for the dma_ops
1682 * interface functions.
1683 *
1684 ****************************************************************************/
1685
1686
1687 static unsigned long dma_ops_alloc_iova(struct device *dev,
1688 struct dma_ops_domain *dma_dom,
1689 unsigned int pages, u64 dma_mask)
1690 {
1691 unsigned long pfn = 0;
1692
1693 pages = __roundup_pow_of_two(pages);
1694
1695 if (dma_mask > DMA_BIT_MASK(32))
1696 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1697 IOVA_PFN(DMA_BIT_MASK(32)), false);
1698
1699 if (!pfn)
1700 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1701 IOVA_PFN(dma_mask), true);
1702
1703 return (pfn << PAGE_SHIFT);
1704 }
1705
1706 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1707 unsigned long address,
1708 unsigned int pages)
1709 {
1710 pages = __roundup_pow_of_two(pages);
1711 address >>= PAGE_SHIFT;
1712
1713 free_iova_fast(&dma_dom->iovad, address, pages);
1714 }
1715
1716 /****************************************************************************
1717 *
1718 * The next functions belong to the domain allocation. A domain is
1719 * allocated for every IOMMU as the default domain. If device isolation
1720 * is enabled, every device get its own domain. The most important thing
1721 * about domains is the page table mapping the DMA address space they
1722 * contain.
1723 *
1724 ****************************************************************************/
1725
1726 static u16 domain_id_alloc(void)
1727 {
1728 int id;
1729
1730 spin_lock(&pd_bitmap_lock);
1731 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1732 BUG_ON(id == 0);
1733 if (id > 0 && id < MAX_DOMAIN_ID)
1734 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1735 else
1736 id = 0;
1737 spin_unlock(&pd_bitmap_lock);
1738
1739 return id;
1740 }
1741
1742 static void domain_id_free(int id)
1743 {
1744 spin_lock(&pd_bitmap_lock);
1745 if (id > 0 && id < MAX_DOMAIN_ID)
1746 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1747 spin_unlock(&pd_bitmap_lock);
1748 }
1749
1750 static void free_gcr3_tbl_level1(u64 *tbl)
1751 {
1752 u64 *ptr;
1753 int i;
1754
1755 for (i = 0; i < 512; ++i) {
1756 if (!(tbl[i] & GCR3_VALID))
1757 continue;
1758
1759 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1760
1761 free_page((unsigned long)ptr);
1762 }
1763 }
1764
1765 static void free_gcr3_tbl_level2(u64 *tbl)
1766 {
1767 u64 *ptr;
1768 int i;
1769
1770 for (i = 0; i < 512; ++i) {
1771 if (!(tbl[i] & GCR3_VALID))
1772 continue;
1773
1774 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1775
1776 free_gcr3_tbl_level1(ptr);
1777 }
1778 }
1779
1780 static void free_gcr3_table(struct protection_domain *domain)
1781 {
1782 if (domain->glx == 2)
1783 free_gcr3_tbl_level2(domain->gcr3_tbl);
1784 else if (domain->glx == 1)
1785 free_gcr3_tbl_level1(domain->gcr3_tbl);
1786 else
1787 BUG_ON(domain->glx != 0);
1788
1789 free_page((unsigned long)domain->gcr3_tbl);
1790 }
1791
1792 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1793 {
1794 domain_flush_tlb(&dom->domain);
1795 domain_flush_complete(&dom->domain);
1796 }
1797
1798 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1799 {
1800 struct dma_ops_domain *dom;
1801
1802 dom = container_of(iovad, struct dma_ops_domain, iovad);
1803
1804 dma_ops_domain_flush_tlb(dom);
1805 }
1806
1807 /*
1808 * Free a domain, only used if something went wrong in the
1809 * allocation path and we need to free an already allocated page table
1810 */
1811 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1812 {
1813 if (!dom)
1814 return;
1815
1816 put_iova_domain(&dom->iovad);
1817
1818 free_pagetable(&dom->domain);
1819
1820 if (dom->domain.id)
1821 domain_id_free(dom->domain.id);
1822
1823 kfree(dom);
1824 }
1825
1826 /*
1827 * Allocates a new protection domain usable for the dma_ops functions.
1828 * It also initializes the page table and the address allocator data
1829 * structures required for the dma_ops interface
1830 */
1831 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1832 {
1833 struct dma_ops_domain *dma_dom;
1834
1835 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1836 if (!dma_dom)
1837 return NULL;
1838
1839 if (protection_domain_init(&dma_dom->domain))
1840 goto free_dma_dom;
1841
1842 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1843 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1844 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1845 if (!dma_dom->domain.pt_root)
1846 goto free_dma_dom;
1847
1848 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1849
1850 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1851 goto free_dma_dom;
1852
1853 /* Initialize reserved ranges */
1854 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1855
1856 return dma_dom;
1857
1858 free_dma_dom:
1859 dma_ops_domain_free(dma_dom);
1860
1861 return NULL;
1862 }
1863
1864 /*
1865 * little helper function to check whether a given protection domain is a
1866 * dma_ops domain
1867 */
1868 static bool dma_ops_domain(struct protection_domain *domain)
1869 {
1870 return domain->flags & PD_DMA_OPS_MASK;
1871 }
1872
1873 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1874 bool ats, bool ppr)
1875 {
1876 u64 pte_root = 0;
1877 u64 flags = 0;
1878
1879 if (domain->mode != PAGE_MODE_NONE)
1880 pte_root = iommu_virt_to_phys(domain->pt_root);
1881
1882 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1883 << DEV_ENTRY_MODE_SHIFT;
1884 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1885
1886 flags = amd_iommu_dev_table[devid].data[1];
1887
1888 if (ats)
1889 flags |= DTE_FLAG_IOTLB;
1890
1891 if (ppr) {
1892 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1893
1894 if (iommu_feature(iommu, FEATURE_EPHSUP))
1895 pte_root |= 1ULL << DEV_ENTRY_PPR;
1896 }
1897
1898 if (domain->flags & PD_IOMMUV2_MASK) {
1899 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1900 u64 glx = domain->glx;
1901 u64 tmp;
1902
1903 pte_root |= DTE_FLAG_GV;
1904 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1905
1906 /* First mask out possible old values for GCR3 table */
1907 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1908 flags &= ~tmp;
1909
1910 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1911 flags &= ~tmp;
1912
1913 /* Encode GCR3 table into DTE */
1914 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1915 pte_root |= tmp;
1916
1917 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1918 flags |= tmp;
1919
1920 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1921 flags |= tmp;
1922 }
1923
1924 flags &= ~DEV_DOMID_MASK;
1925 flags |= domain->id;
1926
1927 amd_iommu_dev_table[devid].data[1] = flags;
1928 amd_iommu_dev_table[devid].data[0] = pte_root;
1929 }
1930
1931 static void clear_dte_entry(u16 devid)
1932 {
1933 /* remove entry from the device table seen by the hardware */
1934 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1935 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1936
1937 amd_iommu_apply_erratum_63(devid);
1938 }
1939
1940 static void do_attach(struct iommu_dev_data *dev_data,
1941 struct protection_domain *domain)
1942 {
1943 struct amd_iommu *iommu;
1944 u16 alias;
1945 bool ats;
1946
1947 iommu = amd_iommu_rlookup_table[dev_data->devid];
1948 alias = dev_data->alias;
1949 ats = dev_data->ats.enabled;
1950
1951 /* Update data structures */
1952 dev_data->domain = domain;
1953 list_add(&dev_data->list, &domain->dev_list);
1954
1955 /* Do reference counting */
1956 domain->dev_iommu[iommu->index] += 1;
1957 domain->dev_cnt += 1;
1958
1959 /* Update device table */
1960 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1961 if (alias != dev_data->devid)
1962 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1963
1964 device_flush_dte(dev_data);
1965 }
1966
1967 static void do_detach(struct iommu_dev_data *dev_data)
1968 {
1969 struct protection_domain *domain = dev_data->domain;
1970 struct amd_iommu *iommu;
1971 u16 alias;
1972
1973 iommu = amd_iommu_rlookup_table[dev_data->devid];
1974 alias = dev_data->alias;
1975
1976 /* Update data structures */
1977 dev_data->domain = NULL;
1978 list_del(&dev_data->list);
1979 clear_dte_entry(dev_data->devid);
1980 if (alias != dev_data->devid)
1981 clear_dte_entry(alias);
1982
1983 /* Flush the DTE entry */
1984 device_flush_dte(dev_data);
1985
1986 /* Flush IOTLB */
1987 domain_flush_tlb_pde(domain);
1988
1989 /* Wait for the flushes to finish */
1990 domain_flush_complete(domain);
1991
1992 /* decrease reference counters - needs to happen after the flushes */
1993 domain->dev_iommu[iommu->index] -= 1;
1994 domain->dev_cnt -= 1;
1995 }
1996
1997 /*
1998 * If a device is not yet associated with a domain, this function makes the
1999 * device visible in the domain
2000 */
2001 static int __attach_device(struct iommu_dev_data *dev_data,
2002 struct protection_domain *domain)
2003 {
2004 int ret;
2005
2006 /* lock domain */
2007 spin_lock(&domain->lock);
2008
2009 ret = -EBUSY;
2010 if (dev_data->domain != NULL)
2011 goto out_unlock;
2012
2013 /* Attach alias group root */
2014 do_attach(dev_data, domain);
2015
2016 ret = 0;
2017
2018 out_unlock:
2019
2020 /* ready */
2021 spin_unlock(&domain->lock);
2022
2023 return ret;
2024 }
2025
2026
2027 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2028 {
2029 pci_disable_ats(pdev);
2030 pci_disable_pri(pdev);
2031 pci_disable_pasid(pdev);
2032 }
2033
2034 /* FIXME: Change generic reset-function to do the same */
2035 static int pri_reset_while_enabled(struct pci_dev *pdev)
2036 {
2037 u16 control;
2038 int pos;
2039
2040 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2041 if (!pos)
2042 return -EINVAL;
2043
2044 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2045 control |= PCI_PRI_CTRL_RESET;
2046 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2047
2048 return 0;
2049 }
2050
2051 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2052 {
2053 bool reset_enable;
2054 int reqs, ret;
2055
2056 /* FIXME: Hardcode number of outstanding requests for now */
2057 reqs = 32;
2058 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2059 reqs = 1;
2060 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2061
2062 /* Only allow access to user-accessible pages */
2063 ret = pci_enable_pasid(pdev, 0);
2064 if (ret)
2065 goto out_err;
2066
2067 /* First reset the PRI state of the device */
2068 ret = pci_reset_pri(pdev);
2069 if (ret)
2070 goto out_err;
2071
2072 /* Enable PRI */
2073 ret = pci_enable_pri(pdev, reqs);
2074 if (ret)
2075 goto out_err;
2076
2077 if (reset_enable) {
2078 ret = pri_reset_while_enabled(pdev);
2079 if (ret)
2080 goto out_err;
2081 }
2082
2083 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2084 if (ret)
2085 goto out_err;
2086
2087 return 0;
2088
2089 out_err:
2090 pci_disable_pri(pdev);
2091 pci_disable_pasid(pdev);
2092
2093 return ret;
2094 }
2095
2096 /*
2097 * If a device is not yet associated with a domain, this function makes the
2098 * device visible in the domain
2099 */
2100 static int attach_device(struct device *dev,
2101 struct protection_domain *domain)
2102 {
2103 struct pci_dev *pdev;
2104 struct iommu_dev_data *dev_data;
2105 unsigned long flags;
2106 int ret;
2107
2108 dev_data = get_dev_data(dev);
2109
2110 if (!dev_is_pci(dev))
2111 goto skip_ats_check;
2112
2113 pdev = to_pci_dev(dev);
2114 if (domain->flags & PD_IOMMUV2_MASK) {
2115 if (!dev_data->passthrough)
2116 return -EINVAL;
2117
2118 if (dev_data->iommu_v2) {
2119 if (pdev_iommuv2_enable(pdev) != 0)
2120 return -EINVAL;
2121
2122 dev_data->ats.enabled = true;
2123 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2124 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2125 }
2126 } else if (amd_iommu_iotlb_sup &&
2127 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2128 dev_data->ats.enabled = true;
2129 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2130 }
2131
2132 skip_ats_check:
2133 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2134 ret = __attach_device(dev_data, domain);
2135 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2136
2137 /*
2138 * We might boot into a crash-kernel here. The crashed kernel
2139 * left the caches in the IOMMU dirty. So we have to flush
2140 * here to evict all dirty stuff.
2141 */
2142 domain_flush_tlb_pde(domain);
2143
2144 return ret;
2145 }
2146
2147 /*
2148 * Removes a device from a protection domain (unlocked)
2149 */
2150 static void __detach_device(struct iommu_dev_data *dev_data)
2151 {
2152 struct protection_domain *domain;
2153
2154 domain = dev_data->domain;
2155
2156 spin_lock(&domain->lock);
2157
2158 do_detach(dev_data);
2159
2160 spin_unlock(&domain->lock);
2161 }
2162
2163 /*
2164 * Removes a device from a protection domain (with devtable_lock held)
2165 */
2166 static void detach_device(struct device *dev)
2167 {
2168 struct protection_domain *domain;
2169 struct iommu_dev_data *dev_data;
2170 unsigned long flags;
2171
2172 dev_data = get_dev_data(dev);
2173 domain = dev_data->domain;
2174
2175 /*
2176 * First check if the device is still attached. It might already
2177 * be detached from its domain because the generic
2178 * iommu_detach_group code detached it and we try again here in
2179 * our alias handling.
2180 */
2181 if (WARN_ON(!dev_data->domain))
2182 return;
2183
2184 /* lock device table */
2185 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2186 __detach_device(dev_data);
2187 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2188
2189 if (!dev_is_pci(dev))
2190 return;
2191
2192 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2193 pdev_iommuv2_disable(to_pci_dev(dev));
2194 else if (dev_data->ats.enabled)
2195 pci_disable_ats(to_pci_dev(dev));
2196
2197 dev_data->ats.enabled = false;
2198 }
2199
2200 static int amd_iommu_add_device(struct device *dev)
2201 {
2202 struct iommu_dev_data *dev_data;
2203 struct iommu_domain *domain;
2204 struct amd_iommu *iommu;
2205 int ret, devid;
2206
2207 if (!check_device(dev) || get_dev_data(dev))
2208 return 0;
2209
2210 devid = get_device_id(dev);
2211 if (devid < 0)
2212 return devid;
2213
2214 iommu = amd_iommu_rlookup_table[devid];
2215
2216 ret = iommu_init_device(dev);
2217 if (ret) {
2218 if (ret != -ENOTSUPP)
2219 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2220
2221 iommu_ignore_device(dev);
2222 dev->dma_ops = NULL;
2223 goto out;
2224 }
2225 init_iommu_group(dev);
2226
2227 dev_data = get_dev_data(dev);
2228
2229 BUG_ON(!dev_data);
2230
2231 if (iommu_pass_through || dev_data->iommu_v2)
2232 iommu_request_dm_for_dev(dev);
2233
2234 /* Domains are initialized for this device - have a look what we ended up with */
2235 domain = iommu_get_domain_for_dev(dev);
2236 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2237 dev_data->passthrough = true;
2238 else
2239 dev->dma_ops = &amd_iommu_dma_ops;
2240
2241 out:
2242 iommu_completion_wait(iommu);
2243
2244 return 0;
2245 }
2246
2247 static void amd_iommu_remove_device(struct device *dev)
2248 {
2249 struct amd_iommu *iommu;
2250 int devid;
2251
2252 if (!check_device(dev))
2253 return;
2254
2255 devid = get_device_id(dev);
2256 if (devid < 0)
2257 return;
2258
2259 iommu = amd_iommu_rlookup_table[devid];
2260
2261 iommu_uninit_device(dev);
2262 iommu_completion_wait(iommu);
2263 }
2264
2265 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2266 {
2267 if (dev_is_pci(dev))
2268 return pci_device_group(dev);
2269
2270 return acpihid_device_group(dev);
2271 }
2272
2273 /*****************************************************************************
2274 *
2275 * The next functions belong to the dma_ops mapping/unmapping code.
2276 *
2277 *****************************************************************************/
2278
2279 /*
2280 * In the dma_ops path we only have the struct device. This function
2281 * finds the corresponding IOMMU, the protection domain and the
2282 * requestor id for a given device.
2283 * If the device is not yet associated with a domain this is also done
2284 * in this function.
2285 */
2286 static struct protection_domain *get_domain(struct device *dev)
2287 {
2288 struct protection_domain *domain;
2289 struct iommu_domain *io_domain;
2290
2291 if (!check_device(dev))
2292 return ERR_PTR(-EINVAL);
2293
2294 domain = get_dev_data(dev)->domain;
2295 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2296 get_dev_data(dev)->defer_attach = false;
2297 io_domain = iommu_get_domain_for_dev(dev);
2298 domain = to_pdomain(io_domain);
2299 attach_device(dev, domain);
2300 }
2301 if (domain == NULL)
2302 return ERR_PTR(-EBUSY);
2303
2304 if (!dma_ops_domain(domain))
2305 return ERR_PTR(-EBUSY);
2306
2307 return domain;
2308 }
2309
2310 static void update_device_table(struct protection_domain *domain)
2311 {
2312 struct iommu_dev_data *dev_data;
2313
2314 list_for_each_entry(dev_data, &domain->dev_list, list) {
2315 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2316 dev_data->iommu_v2);
2317
2318 if (dev_data->devid == dev_data->alias)
2319 continue;
2320
2321 /* There is an alias, update device table entry for it */
2322 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2323 dev_data->iommu_v2);
2324 }
2325 }
2326
2327 static void update_domain(struct protection_domain *domain)
2328 {
2329 if (!domain->updated)
2330 return;
2331
2332 update_device_table(domain);
2333
2334 domain_flush_devices(domain);
2335 domain_flush_tlb_pde(domain);
2336
2337 domain->updated = false;
2338 }
2339
2340 static int dir2prot(enum dma_data_direction direction)
2341 {
2342 if (direction == DMA_TO_DEVICE)
2343 return IOMMU_PROT_IR;
2344 else if (direction == DMA_FROM_DEVICE)
2345 return IOMMU_PROT_IW;
2346 else if (direction == DMA_BIDIRECTIONAL)
2347 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2348 else
2349 return 0;
2350 }
2351
2352 /*
2353 * This function contains common code for mapping of a physically
2354 * contiguous memory region into DMA address space. It is used by all
2355 * mapping functions provided with this IOMMU driver.
2356 * Must be called with the domain lock held.
2357 */
2358 static dma_addr_t __map_single(struct device *dev,
2359 struct dma_ops_domain *dma_dom,
2360 phys_addr_t paddr,
2361 size_t size,
2362 enum dma_data_direction direction,
2363 u64 dma_mask)
2364 {
2365 dma_addr_t offset = paddr & ~PAGE_MASK;
2366 dma_addr_t address, start, ret;
2367 unsigned int pages;
2368 int prot = 0;
2369 int i;
2370
2371 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2372 paddr &= PAGE_MASK;
2373
2374 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2375 if (!address)
2376 goto out;
2377
2378 prot = dir2prot(direction);
2379
2380 start = address;
2381 for (i = 0; i < pages; ++i) {
2382 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2383 PAGE_SIZE, prot, GFP_ATOMIC);
2384 if (ret)
2385 goto out_unmap;
2386
2387 paddr += PAGE_SIZE;
2388 start += PAGE_SIZE;
2389 }
2390 address += offset;
2391
2392 if (unlikely(amd_iommu_np_cache)) {
2393 domain_flush_pages(&dma_dom->domain, address, size);
2394 domain_flush_complete(&dma_dom->domain);
2395 }
2396
2397 out:
2398 return address;
2399
2400 out_unmap:
2401
2402 for (--i; i >= 0; --i) {
2403 start -= PAGE_SIZE;
2404 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2405 }
2406
2407 domain_flush_tlb(&dma_dom->domain);
2408 domain_flush_complete(&dma_dom->domain);
2409
2410 dma_ops_free_iova(dma_dom, address, pages);
2411
2412 return DMA_MAPPING_ERROR;
2413 }
2414
2415 /*
2416 * Does the reverse of the __map_single function. Must be called with
2417 * the domain lock held too
2418 */
2419 static void __unmap_single(struct dma_ops_domain *dma_dom,
2420 dma_addr_t dma_addr,
2421 size_t size,
2422 int dir)
2423 {
2424 dma_addr_t i, start;
2425 unsigned int pages;
2426
2427 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2428 dma_addr &= PAGE_MASK;
2429 start = dma_addr;
2430
2431 for (i = 0; i < pages; ++i) {
2432 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2433 start += PAGE_SIZE;
2434 }
2435
2436 if (amd_iommu_unmap_flush) {
2437 domain_flush_tlb(&dma_dom->domain);
2438 domain_flush_complete(&dma_dom->domain);
2439 dma_ops_free_iova(dma_dom, dma_addr, pages);
2440 } else {
2441 pages = __roundup_pow_of_two(pages);
2442 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2443 }
2444 }
2445
2446 /*
2447 * The exported map_single function for dma_ops.
2448 */
2449 static dma_addr_t map_page(struct device *dev, struct page *page,
2450 unsigned long offset, size_t size,
2451 enum dma_data_direction dir,
2452 unsigned long attrs)
2453 {
2454 phys_addr_t paddr = page_to_phys(page) + offset;
2455 struct protection_domain *domain;
2456 struct dma_ops_domain *dma_dom;
2457 u64 dma_mask;
2458
2459 domain = get_domain(dev);
2460 if (PTR_ERR(domain) == -EINVAL)
2461 return (dma_addr_t)paddr;
2462 else if (IS_ERR(domain))
2463 return DMA_MAPPING_ERROR;
2464
2465 dma_mask = *dev->dma_mask;
2466 dma_dom = to_dma_ops_domain(domain);
2467
2468 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2469 }
2470
2471 /*
2472 * The exported unmap_single function for dma_ops.
2473 */
2474 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2475 enum dma_data_direction dir, unsigned long attrs)
2476 {
2477 struct protection_domain *domain;
2478 struct dma_ops_domain *dma_dom;
2479
2480 domain = get_domain(dev);
2481 if (IS_ERR(domain))
2482 return;
2483
2484 dma_dom = to_dma_ops_domain(domain);
2485
2486 __unmap_single(dma_dom, dma_addr, size, dir);
2487 }
2488
2489 static int sg_num_pages(struct device *dev,
2490 struct scatterlist *sglist,
2491 int nelems)
2492 {
2493 unsigned long mask, boundary_size;
2494 struct scatterlist *s;
2495 int i, npages = 0;
2496
2497 mask = dma_get_seg_boundary(dev);
2498 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2499 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2500
2501 for_each_sg(sglist, s, nelems, i) {
2502 int p, n;
2503
2504 s->dma_address = npages << PAGE_SHIFT;
2505 p = npages % boundary_size;
2506 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2507 if (p + n > boundary_size)
2508 npages += boundary_size - p;
2509 npages += n;
2510 }
2511
2512 return npages;
2513 }
2514
2515 /*
2516 * The exported map_sg function for dma_ops (handles scatter-gather
2517 * lists).
2518 */
2519 static int map_sg(struct device *dev, struct scatterlist *sglist,
2520 int nelems, enum dma_data_direction direction,
2521 unsigned long attrs)
2522 {
2523 int mapped_pages = 0, npages = 0, prot = 0, i;
2524 struct protection_domain *domain;
2525 struct dma_ops_domain *dma_dom;
2526 struct scatterlist *s;
2527 unsigned long address;
2528 u64 dma_mask;
2529 int ret;
2530
2531 domain = get_domain(dev);
2532 if (IS_ERR(domain))
2533 return 0;
2534
2535 dma_dom = to_dma_ops_domain(domain);
2536 dma_mask = *dev->dma_mask;
2537
2538 npages = sg_num_pages(dev, sglist, nelems);
2539
2540 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2541 if (address == DMA_MAPPING_ERROR)
2542 goto out_err;
2543
2544 prot = dir2prot(direction);
2545
2546 /* Map all sg entries */
2547 for_each_sg(sglist, s, nelems, i) {
2548 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2549
2550 for (j = 0; j < pages; ++j) {
2551 unsigned long bus_addr, phys_addr;
2552
2553 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2554 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2555 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2556 if (ret)
2557 goto out_unmap;
2558
2559 mapped_pages += 1;
2560 }
2561 }
2562
2563 /* Everything is mapped - write the right values into s->dma_address */
2564 for_each_sg(sglist, s, nelems, i) {
2565 /*
2566 * Add in the remaining piece of the scatter-gather offset that
2567 * was masked out when we were determining the physical address
2568 * via (sg_phys(s) & PAGE_MASK) earlier.
2569 */
2570 s->dma_address += address + (s->offset & ~PAGE_MASK);
2571 s->dma_length = s->length;
2572 }
2573
2574 return nelems;
2575
2576 out_unmap:
2577 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2578 npages, ret);
2579
2580 for_each_sg(sglist, s, nelems, i) {
2581 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2582
2583 for (j = 0; j < pages; ++j) {
2584 unsigned long bus_addr;
2585
2586 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2587 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2588
2589 if (--mapped_pages == 0)
2590 goto out_free_iova;
2591 }
2592 }
2593
2594 out_free_iova:
2595 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2596
2597 out_err:
2598 return 0;
2599 }
2600
2601 /*
2602 * The exported map_sg function for dma_ops (handles scatter-gather
2603 * lists).
2604 */
2605 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2606 int nelems, enum dma_data_direction dir,
2607 unsigned long attrs)
2608 {
2609 struct protection_domain *domain;
2610 struct dma_ops_domain *dma_dom;
2611 unsigned long startaddr;
2612 int npages = 2;
2613
2614 domain = get_domain(dev);
2615 if (IS_ERR(domain))
2616 return;
2617
2618 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2619 dma_dom = to_dma_ops_domain(domain);
2620 npages = sg_num_pages(dev, sglist, nelems);
2621
2622 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2623 }
2624
2625 /*
2626 * The exported alloc_coherent function for dma_ops.
2627 */
2628 static void *alloc_coherent(struct device *dev, size_t size,
2629 dma_addr_t *dma_addr, gfp_t flag,
2630 unsigned long attrs)
2631 {
2632 u64 dma_mask = dev->coherent_dma_mask;
2633 struct protection_domain *domain;
2634 struct dma_ops_domain *dma_dom;
2635 struct page *page;
2636
2637 domain = get_domain(dev);
2638 if (PTR_ERR(domain) == -EINVAL) {
2639 page = alloc_pages(flag, get_order(size));
2640 *dma_addr = page_to_phys(page);
2641 return page_address(page);
2642 } else if (IS_ERR(domain))
2643 return NULL;
2644
2645 dma_dom = to_dma_ops_domain(domain);
2646 size = PAGE_ALIGN(size);
2647 dma_mask = dev->coherent_dma_mask;
2648 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2649 flag |= __GFP_ZERO;
2650
2651 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2652 if (!page) {
2653 if (!gfpflags_allow_blocking(flag))
2654 return NULL;
2655
2656 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2657 get_order(size), flag & __GFP_NOWARN);
2658 if (!page)
2659 return NULL;
2660 }
2661
2662 if (!dma_mask)
2663 dma_mask = *dev->dma_mask;
2664
2665 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2666 size, DMA_BIDIRECTIONAL, dma_mask);
2667
2668 if (*dma_addr == DMA_MAPPING_ERROR)
2669 goto out_free;
2670
2671 return page_address(page);
2672
2673 out_free:
2674
2675 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2676 __free_pages(page, get_order(size));
2677
2678 return NULL;
2679 }
2680
2681 /*
2682 * The exported free_coherent function for dma_ops.
2683 */
2684 static void free_coherent(struct device *dev, size_t size,
2685 void *virt_addr, dma_addr_t dma_addr,
2686 unsigned long attrs)
2687 {
2688 struct protection_domain *domain;
2689 struct dma_ops_domain *dma_dom;
2690 struct page *page;
2691
2692 page = virt_to_page(virt_addr);
2693 size = PAGE_ALIGN(size);
2694
2695 domain = get_domain(dev);
2696 if (IS_ERR(domain))
2697 goto free_mem;
2698
2699 dma_dom = to_dma_ops_domain(domain);
2700
2701 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2702
2703 free_mem:
2704 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2705 __free_pages(page, get_order(size));
2706 }
2707
2708 /*
2709 * This function is called by the DMA layer to find out if we can handle a
2710 * particular device. It is part of the dma_ops.
2711 */
2712 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2713 {
2714 if (!dma_direct_supported(dev, mask))
2715 return 0;
2716 return check_device(dev);
2717 }
2718
2719 static const struct dma_map_ops amd_iommu_dma_ops = {
2720 .alloc = alloc_coherent,
2721 .free = free_coherent,
2722 .map_page = map_page,
2723 .unmap_page = unmap_page,
2724 .map_sg = map_sg,
2725 .unmap_sg = unmap_sg,
2726 .dma_supported = amd_iommu_dma_supported,
2727 };
2728
2729 static int init_reserved_iova_ranges(void)
2730 {
2731 struct pci_dev *pdev = NULL;
2732 struct iova *val;
2733
2734 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2735
2736 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2737 &reserved_rbtree_key);
2738
2739 /* MSI memory range */
2740 val = reserve_iova(&reserved_iova_ranges,
2741 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2742 if (!val) {
2743 pr_err("Reserving MSI range failed\n");
2744 return -ENOMEM;
2745 }
2746
2747 /* HT memory range */
2748 val = reserve_iova(&reserved_iova_ranges,
2749 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2750 if (!val) {
2751 pr_err("Reserving HT range failed\n");
2752 return -ENOMEM;
2753 }
2754
2755 /*
2756 * Memory used for PCI resources
2757 * FIXME: Check whether we can reserve the PCI-hole completly
2758 */
2759 for_each_pci_dev(pdev) {
2760 int i;
2761
2762 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2763 struct resource *r = &pdev->resource[i];
2764
2765 if (!(r->flags & IORESOURCE_MEM))
2766 continue;
2767
2768 val = reserve_iova(&reserved_iova_ranges,
2769 IOVA_PFN(r->start),
2770 IOVA_PFN(r->end));
2771 if (!val) {
2772 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2773 return -ENOMEM;
2774 }
2775 }
2776 }
2777
2778 return 0;
2779 }
2780
2781 int __init amd_iommu_init_api(void)
2782 {
2783 int ret, err = 0;
2784
2785 ret = iova_cache_get();
2786 if (ret)
2787 return ret;
2788
2789 ret = init_reserved_iova_ranges();
2790 if (ret)
2791 return ret;
2792
2793 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2794 if (err)
2795 return err;
2796 #ifdef CONFIG_ARM_AMBA
2797 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2798 if (err)
2799 return err;
2800 #endif
2801 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2802 if (err)
2803 return err;
2804
2805 return 0;
2806 }
2807
2808 int __init amd_iommu_init_dma_ops(void)
2809 {
2810 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2811 iommu_detected = 1;
2812
2813 if (amd_iommu_unmap_flush)
2814 pr_info("IO/TLB flush on unmap enabled\n");
2815 else
2816 pr_info("Lazy IO/TLB flushing enabled\n");
2817
2818 return 0;
2819
2820 }
2821
2822 /*****************************************************************************
2823 *
2824 * The following functions belong to the exported interface of AMD IOMMU
2825 *
2826 * This interface allows access to lower level functions of the IOMMU
2827 * like protection domain handling and assignement of devices to domains
2828 * which is not possible with the dma_ops interface.
2829 *
2830 *****************************************************************************/
2831
2832 static void cleanup_domain(struct protection_domain *domain)
2833 {
2834 struct iommu_dev_data *entry;
2835 unsigned long flags;
2836
2837 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2838
2839 while (!list_empty(&domain->dev_list)) {
2840 entry = list_first_entry(&domain->dev_list,
2841 struct iommu_dev_data, list);
2842 BUG_ON(!entry->domain);
2843 __detach_device(entry);
2844 }
2845
2846 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2847 }
2848
2849 static void protection_domain_free(struct protection_domain *domain)
2850 {
2851 if (!domain)
2852 return;
2853
2854 if (domain->id)
2855 domain_id_free(domain->id);
2856
2857 kfree(domain);
2858 }
2859
2860 static int protection_domain_init(struct protection_domain *domain)
2861 {
2862 spin_lock_init(&domain->lock);
2863 mutex_init(&domain->api_lock);
2864 domain->id = domain_id_alloc();
2865 if (!domain->id)
2866 return -ENOMEM;
2867 INIT_LIST_HEAD(&domain->dev_list);
2868
2869 return 0;
2870 }
2871
2872 static struct protection_domain *protection_domain_alloc(void)
2873 {
2874 struct protection_domain *domain;
2875
2876 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2877 if (!domain)
2878 return NULL;
2879
2880 if (protection_domain_init(domain))
2881 goto out_err;
2882
2883 return domain;
2884
2885 out_err:
2886 kfree(domain);
2887
2888 return NULL;
2889 }
2890
2891 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2892 {
2893 struct protection_domain *pdomain;
2894 struct dma_ops_domain *dma_domain;
2895
2896 switch (type) {
2897 case IOMMU_DOMAIN_UNMANAGED:
2898 pdomain = protection_domain_alloc();
2899 if (!pdomain)
2900 return NULL;
2901
2902 pdomain->mode = PAGE_MODE_3_LEVEL;
2903 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2904 if (!pdomain->pt_root) {
2905 protection_domain_free(pdomain);
2906 return NULL;
2907 }
2908
2909 pdomain->domain.geometry.aperture_start = 0;
2910 pdomain->domain.geometry.aperture_end = ~0ULL;
2911 pdomain->domain.geometry.force_aperture = true;
2912
2913 break;
2914 case IOMMU_DOMAIN_DMA:
2915 dma_domain = dma_ops_domain_alloc();
2916 if (!dma_domain) {
2917 pr_err("Failed to allocate\n");
2918 return NULL;
2919 }
2920 pdomain = &dma_domain->domain;
2921 break;
2922 case IOMMU_DOMAIN_IDENTITY:
2923 pdomain = protection_domain_alloc();
2924 if (!pdomain)
2925 return NULL;
2926
2927 pdomain->mode = PAGE_MODE_NONE;
2928 break;
2929 default:
2930 return NULL;
2931 }
2932
2933 return &pdomain->domain;
2934 }
2935
2936 static void amd_iommu_domain_free(struct iommu_domain *dom)
2937 {
2938 struct protection_domain *domain;
2939 struct dma_ops_domain *dma_dom;
2940
2941 domain = to_pdomain(dom);
2942
2943 if (domain->dev_cnt > 0)
2944 cleanup_domain(domain);
2945
2946 BUG_ON(domain->dev_cnt != 0);
2947
2948 if (!dom)
2949 return;
2950
2951 switch (dom->type) {
2952 case IOMMU_DOMAIN_DMA:
2953 /* Now release the domain */
2954 dma_dom = to_dma_ops_domain(domain);
2955 dma_ops_domain_free(dma_dom);
2956 break;
2957 default:
2958 if (domain->mode != PAGE_MODE_NONE)
2959 free_pagetable(domain);
2960
2961 if (domain->flags & PD_IOMMUV2_MASK)
2962 free_gcr3_table(domain);
2963
2964 protection_domain_free(domain);
2965 break;
2966 }
2967 }
2968
2969 static void amd_iommu_detach_device(struct iommu_domain *dom,
2970 struct device *dev)
2971 {
2972 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2973 struct amd_iommu *iommu;
2974 int devid;
2975
2976 if (!check_device(dev))
2977 return;
2978
2979 devid = get_device_id(dev);
2980 if (devid < 0)
2981 return;
2982
2983 if (dev_data->domain != NULL)
2984 detach_device(dev);
2985
2986 iommu = amd_iommu_rlookup_table[devid];
2987 if (!iommu)
2988 return;
2989
2990 #ifdef CONFIG_IRQ_REMAP
2991 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2992 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2993 dev_data->use_vapic = 0;
2994 #endif
2995
2996 iommu_completion_wait(iommu);
2997 }
2998
2999 static int amd_iommu_attach_device(struct iommu_domain *dom,
3000 struct device *dev)
3001 {
3002 struct protection_domain *domain = to_pdomain(dom);
3003 struct iommu_dev_data *dev_data;
3004 struct amd_iommu *iommu;
3005 int ret;
3006
3007 if (!check_device(dev))
3008 return -EINVAL;
3009
3010 dev_data = dev->archdata.iommu;
3011
3012 iommu = amd_iommu_rlookup_table[dev_data->devid];
3013 if (!iommu)
3014 return -EINVAL;
3015
3016 if (dev_data->domain)
3017 detach_device(dev);
3018
3019 ret = attach_device(dev, domain);
3020
3021 #ifdef CONFIG_IRQ_REMAP
3022 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3023 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3024 dev_data->use_vapic = 1;
3025 else
3026 dev_data->use_vapic = 0;
3027 }
3028 #endif
3029
3030 iommu_completion_wait(iommu);
3031
3032 return ret;
3033 }
3034
3035 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3036 phys_addr_t paddr, size_t page_size, int iommu_prot)
3037 {
3038 struct protection_domain *domain = to_pdomain(dom);
3039 int prot = 0;
3040 int ret;
3041
3042 if (domain->mode == PAGE_MODE_NONE)
3043 return -EINVAL;
3044
3045 if (iommu_prot & IOMMU_READ)
3046 prot |= IOMMU_PROT_IR;
3047 if (iommu_prot & IOMMU_WRITE)
3048 prot |= IOMMU_PROT_IW;
3049
3050 mutex_lock(&domain->api_lock);
3051 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3052 mutex_unlock(&domain->api_lock);
3053
3054 return ret;
3055 }
3056
3057 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3058 size_t page_size)
3059 {
3060 struct protection_domain *domain = to_pdomain(dom);
3061 size_t unmap_size;
3062
3063 if (domain->mode == PAGE_MODE_NONE)
3064 return 0;
3065
3066 mutex_lock(&domain->api_lock);
3067 unmap_size = iommu_unmap_page(domain, iova, page_size);
3068 mutex_unlock(&domain->api_lock);
3069
3070 return unmap_size;
3071 }
3072
3073 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3074 dma_addr_t iova)
3075 {
3076 struct protection_domain *domain = to_pdomain(dom);
3077 unsigned long offset_mask, pte_pgsize;
3078 u64 *pte, __pte;
3079
3080 if (domain->mode == PAGE_MODE_NONE)
3081 return iova;
3082
3083 pte = fetch_pte(domain, iova, &pte_pgsize);
3084
3085 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3086 return 0;
3087
3088 offset_mask = pte_pgsize - 1;
3089 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3090
3091 return (__pte & ~offset_mask) | (iova & offset_mask);
3092 }
3093
3094 static bool amd_iommu_capable(enum iommu_cap cap)
3095 {
3096 switch (cap) {
3097 case IOMMU_CAP_CACHE_COHERENCY:
3098 return true;
3099 case IOMMU_CAP_INTR_REMAP:
3100 return (irq_remapping_enabled == 1);
3101 case IOMMU_CAP_NOEXEC:
3102 return false;
3103 default:
3104 break;
3105 }
3106
3107 return false;
3108 }
3109
3110 static void amd_iommu_get_resv_regions(struct device *dev,
3111 struct list_head *head)
3112 {
3113 struct iommu_resv_region *region;
3114 struct unity_map_entry *entry;
3115 int devid;
3116
3117 devid = get_device_id(dev);
3118 if (devid < 0)
3119 return;
3120
3121 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3122 int type, prot = 0;
3123 size_t length;
3124
3125 if (devid < entry->devid_start || devid > entry->devid_end)
3126 continue;
3127
3128 type = IOMMU_RESV_DIRECT;
3129 length = entry->address_end - entry->address_start;
3130 if (entry->prot & IOMMU_PROT_IR)
3131 prot |= IOMMU_READ;
3132 if (entry->prot & IOMMU_PROT_IW)
3133 prot |= IOMMU_WRITE;
3134 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3135 /* Exclusion range */
3136 type = IOMMU_RESV_RESERVED;
3137
3138 region = iommu_alloc_resv_region(entry->address_start,
3139 length, prot, type);
3140 if (!region) {
3141 dev_err(dev, "Out of memory allocating dm-regions\n");
3142 return;
3143 }
3144 list_add_tail(&region->list, head);
3145 }
3146
3147 region = iommu_alloc_resv_region(MSI_RANGE_START,
3148 MSI_RANGE_END - MSI_RANGE_START + 1,
3149 0, IOMMU_RESV_MSI);
3150 if (!region)
3151 return;
3152 list_add_tail(&region->list, head);
3153
3154 region = iommu_alloc_resv_region(HT_RANGE_START,
3155 HT_RANGE_END - HT_RANGE_START + 1,
3156 0, IOMMU_RESV_RESERVED);
3157 if (!region)
3158 return;
3159 list_add_tail(&region->list, head);
3160 }
3161
3162 static void amd_iommu_put_resv_regions(struct device *dev,
3163 struct list_head *head)
3164 {
3165 struct iommu_resv_region *entry, *next;
3166
3167 list_for_each_entry_safe(entry, next, head, list)
3168 kfree(entry);
3169 }
3170
3171 static void amd_iommu_apply_resv_region(struct device *dev,
3172 struct iommu_domain *domain,
3173 struct iommu_resv_region *region)
3174 {
3175 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3176 unsigned long start, end;
3177
3178 start = IOVA_PFN(region->start);
3179 end = IOVA_PFN(region->start + region->length - 1);
3180
3181 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3182 }
3183
3184 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3185 struct device *dev)
3186 {
3187 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3188 return dev_data->defer_attach;
3189 }
3190
3191 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3192 {
3193 struct protection_domain *dom = to_pdomain(domain);
3194
3195 domain_flush_tlb_pde(dom);
3196 domain_flush_complete(dom);
3197 }
3198
3199 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3200 unsigned long iova, size_t size)
3201 {
3202 }
3203
3204 const struct iommu_ops amd_iommu_ops = {
3205 .capable = amd_iommu_capable,
3206 .domain_alloc = amd_iommu_domain_alloc,
3207 .domain_free = amd_iommu_domain_free,
3208 .attach_dev = amd_iommu_attach_device,
3209 .detach_dev = amd_iommu_detach_device,
3210 .map = amd_iommu_map,
3211 .unmap = amd_iommu_unmap,
3212 .iova_to_phys = amd_iommu_iova_to_phys,
3213 .add_device = amd_iommu_add_device,
3214 .remove_device = amd_iommu_remove_device,
3215 .device_group = amd_iommu_device_group,
3216 .get_resv_regions = amd_iommu_get_resv_regions,
3217 .put_resv_regions = amd_iommu_put_resv_regions,
3218 .apply_resv_region = amd_iommu_apply_resv_region,
3219 .is_attach_deferred = amd_iommu_is_attach_deferred,
3220 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3221 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3222 .iotlb_range_add = amd_iommu_iotlb_range_add,
3223 .iotlb_sync = amd_iommu_flush_iotlb_all,
3224 };
3225
3226 /*****************************************************************************
3227 *
3228 * The next functions do a basic initialization of IOMMU for pass through
3229 * mode
3230 *
3231 * In passthrough mode the IOMMU is initialized and enabled but not used for
3232 * DMA-API translation.
3233 *
3234 *****************************************************************************/
3235
3236 /* IOMMUv2 specific functions */
3237 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3238 {
3239 return atomic_notifier_chain_register(&ppr_notifier, nb);
3240 }
3241 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3242
3243 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3244 {
3245 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3246 }
3247 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3248
3249 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3250 {
3251 struct protection_domain *domain = to_pdomain(dom);
3252 unsigned long flags;
3253
3254 spin_lock_irqsave(&domain->lock, flags);
3255
3256 /* Update data structure */
3257 domain->mode = PAGE_MODE_NONE;
3258 domain->updated = true;
3259
3260 /* Make changes visible to IOMMUs */
3261 update_domain(domain);
3262
3263 /* Page-table is not visible to IOMMU anymore, so free it */
3264 free_pagetable(domain);
3265
3266 spin_unlock_irqrestore(&domain->lock, flags);
3267 }
3268 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3269
3270 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3271 {
3272 struct protection_domain *domain = to_pdomain(dom);
3273 unsigned long flags;
3274 int levels, ret;
3275
3276 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3277 return -EINVAL;
3278
3279 /* Number of GCR3 table levels required */
3280 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3281 levels += 1;
3282
3283 if (levels > amd_iommu_max_glx_val)
3284 return -EINVAL;
3285
3286 spin_lock_irqsave(&domain->lock, flags);
3287
3288 /*
3289 * Save us all sanity checks whether devices already in the
3290 * domain support IOMMUv2. Just force that the domain has no
3291 * devices attached when it is switched into IOMMUv2 mode.
3292 */
3293 ret = -EBUSY;
3294 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3295 goto out;
3296
3297 ret = -ENOMEM;
3298 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3299 if (domain->gcr3_tbl == NULL)
3300 goto out;
3301
3302 domain->glx = levels;
3303 domain->flags |= PD_IOMMUV2_MASK;
3304 domain->updated = true;
3305
3306 update_domain(domain);
3307
3308 ret = 0;
3309
3310 out:
3311 spin_unlock_irqrestore(&domain->lock, flags);
3312
3313 return ret;
3314 }
3315 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3316
3317 static int __flush_pasid(struct protection_domain *domain, int pasid,
3318 u64 address, bool size)
3319 {
3320 struct iommu_dev_data *dev_data;
3321 struct iommu_cmd cmd;
3322 int i, ret;
3323
3324 if (!(domain->flags & PD_IOMMUV2_MASK))
3325 return -EINVAL;
3326
3327 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3328
3329 /*
3330 * IOMMU TLB needs to be flushed before Device TLB to
3331 * prevent device TLB refill from IOMMU TLB
3332 */
3333 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3334 if (domain->dev_iommu[i] == 0)
3335 continue;
3336
3337 ret = iommu_queue_command(amd_iommus[i], &cmd);
3338 if (ret != 0)
3339 goto out;
3340 }
3341
3342 /* Wait until IOMMU TLB flushes are complete */
3343 domain_flush_complete(domain);
3344
3345 /* Now flush device TLBs */
3346 list_for_each_entry(dev_data, &domain->dev_list, list) {
3347 struct amd_iommu *iommu;
3348 int qdep;
3349
3350 /*
3351 There might be non-IOMMUv2 capable devices in an IOMMUv2
3352 * domain.
3353 */
3354 if (!dev_data->ats.enabled)
3355 continue;
3356
3357 qdep = dev_data->ats.qdep;
3358 iommu = amd_iommu_rlookup_table[dev_data->devid];
3359
3360 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3361 qdep, address, size);
3362
3363 ret = iommu_queue_command(iommu, &cmd);
3364 if (ret != 0)
3365 goto out;
3366 }
3367
3368 /* Wait until all device TLBs are flushed */
3369 domain_flush_complete(domain);
3370
3371 ret = 0;
3372
3373 out:
3374
3375 return ret;
3376 }
3377
3378 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3379 u64 address)
3380 {
3381 return __flush_pasid(domain, pasid, address, false);
3382 }
3383
3384 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3385 u64 address)
3386 {
3387 struct protection_domain *domain = to_pdomain(dom);
3388 unsigned long flags;
3389 int ret;
3390
3391 spin_lock_irqsave(&domain->lock, flags);
3392 ret = __amd_iommu_flush_page(domain, pasid, address);
3393 spin_unlock_irqrestore(&domain->lock, flags);
3394
3395 return ret;
3396 }
3397 EXPORT_SYMBOL(amd_iommu_flush_page);
3398
3399 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3400 {
3401 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3402 true);
3403 }
3404
3405 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3406 {
3407 struct protection_domain *domain = to_pdomain(dom);
3408 unsigned long flags;
3409 int ret;
3410
3411 spin_lock_irqsave(&domain->lock, flags);
3412 ret = __amd_iommu_flush_tlb(domain, pasid);
3413 spin_unlock_irqrestore(&domain->lock, flags);
3414
3415 return ret;
3416 }
3417 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3418
3419 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3420 {
3421 int index;
3422 u64 *pte;
3423
3424 while (true) {
3425
3426 index = (pasid >> (9 * level)) & 0x1ff;
3427 pte = &root[index];
3428
3429 if (level == 0)
3430 break;
3431
3432 if (!(*pte & GCR3_VALID)) {
3433 if (!alloc)
3434 return NULL;
3435
3436 root = (void *)get_zeroed_page(GFP_ATOMIC);
3437 if (root == NULL)
3438 return NULL;
3439
3440 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3441 }
3442
3443 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3444
3445 level -= 1;
3446 }
3447
3448 return pte;
3449 }
3450
3451 static int __set_gcr3(struct protection_domain *domain, int pasid,
3452 unsigned long cr3)
3453 {
3454 u64 *pte;
3455
3456 if (domain->mode != PAGE_MODE_NONE)
3457 return -EINVAL;
3458
3459 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3460 if (pte == NULL)
3461 return -ENOMEM;
3462
3463 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3464
3465 return __amd_iommu_flush_tlb(domain, pasid);
3466 }
3467
3468 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3469 {
3470 u64 *pte;
3471
3472 if (domain->mode != PAGE_MODE_NONE)
3473 return -EINVAL;
3474
3475 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3476 if (pte == NULL)
3477 return 0;
3478
3479 *pte = 0;
3480
3481 return __amd_iommu_flush_tlb(domain, pasid);
3482 }
3483
3484 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3485 unsigned long cr3)
3486 {
3487 struct protection_domain *domain = to_pdomain(dom);
3488 unsigned long flags;
3489 int ret;
3490
3491 spin_lock_irqsave(&domain->lock, flags);
3492 ret = __set_gcr3(domain, pasid, cr3);
3493 spin_unlock_irqrestore(&domain->lock, flags);
3494
3495 return ret;
3496 }
3497 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3498
3499 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3500 {
3501 struct protection_domain *domain = to_pdomain(dom);
3502 unsigned long flags;
3503 int ret;
3504
3505 spin_lock_irqsave(&domain->lock, flags);
3506 ret = __clear_gcr3(domain, pasid);
3507 spin_unlock_irqrestore(&domain->lock, flags);
3508
3509 return ret;
3510 }
3511 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3512
3513 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3514 int status, int tag)
3515 {
3516 struct iommu_dev_data *dev_data;
3517 struct amd_iommu *iommu;
3518 struct iommu_cmd cmd;
3519
3520 dev_data = get_dev_data(&pdev->dev);
3521 iommu = amd_iommu_rlookup_table[dev_data->devid];
3522
3523 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3524 tag, dev_data->pri_tlp);
3525
3526 return iommu_queue_command(iommu, &cmd);
3527 }
3528 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3529
3530 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3531 {
3532 struct protection_domain *pdomain;
3533
3534 pdomain = get_domain(&pdev->dev);
3535 if (IS_ERR(pdomain))
3536 return NULL;
3537
3538 /* Only return IOMMUv2 domains */
3539 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3540 return NULL;
3541
3542 return &pdomain->domain;
3543 }
3544 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3545
3546 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3547 {
3548 struct iommu_dev_data *dev_data;
3549
3550 if (!amd_iommu_v2_supported())
3551 return;
3552
3553 dev_data = get_dev_data(&pdev->dev);
3554 dev_data->errata |= (1 << erratum);
3555 }
3556 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3557
3558 int amd_iommu_device_info(struct pci_dev *pdev,
3559 struct amd_iommu_device_info *info)
3560 {
3561 int max_pasids;
3562 int pos;
3563
3564 if (pdev == NULL || info == NULL)
3565 return -EINVAL;
3566
3567 if (!amd_iommu_v2_supported())
3568 return -EINVAL;
3569
3570 memset(info, 0, sizeof(*info));
3571
3572 if (!pci_ats_disabled()) {
3573 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3574 if (pos)
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3576 }
3577
3578 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3579 if (pos)
3580 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3581
3582 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3583 if (pos) {
3584 int features;
3585
3586 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3587 max_pasids = min(max_pasids, (1 << 20));
3588
3589 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3590 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3591
3592 features = pci_pasid_features(pdev);
3593 if (features & PCI_PASID_CAP_EXEC)
3594 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3595 if (features & PCI_PASID_CAP_PRIV)
3596 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3597 }
3598
3599 return 0;
3600 }
3601 EXPORT_SYMBOL(amd_iommu_device_info);
3602
3603 #ifdef CONFIG_IRQ_REMAP
3604
3605 /*****************************************************************************
3606 *
3607 * Interrupt Remapping Implementation
3608 *
3609 *****************************************************************************/
3610
3611 static struct irq_chip amd_ir_chip;
3612 static DEFINE_SPINLOCK(iommu_table_lock);
3613
3614 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3615 {
3616 u64 dte;
3617
3618 dte = amd_iommu_dev_table[devid].data[2];
3619 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3620 dte |= iommu_virt_to_phys(table->table);
3621 dte |= DTE_IRQ_REMAP_INTCTL;
3622 dte |= DTE_IRQ_TABLE_LEN;
3623 dte |= DTE_IRQ_REMAP_ENABLE;
3624
3625 amd_iommu_dev_table[devid].data[2] = dte;
3626 }
3627
3628 static struct irq_remap_table *get_irq_table(u16 devid)
3629 {
3630 struct irq_remap_table *table;
3631
3632 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3633 "%s: no iommu for devid %x\n", __func__, devid))
3634 return NULL;
3635
3636 table = irq_lookup_table[devid];
3637 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3638 return NULL;
3639
3640 return table;
3641 }
3642
3643 static struct irq_remap_table *__alloc_irq_table(void)
3644 {
3645 struct irq_remap_table *table;
3646
3647 table = kzalloc(sizeof(*table), GFP_KERNEL);
3648 if (!table)
3649 return NULL;
3650
3651 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3652 if (!table->table) {
3653 kfree(table);
3654 return NULL;
3655 }
3656 raw_spin_lock_init(&table->lock);
3657
3658 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3659 memset(table->table, 0,
3660 MAX_IRQS_PER_TABLE * sizeof(u32));
3661 else
3662 memset(table->table, 0,
3663 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3664 return table;
3665 }
3666
3667 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3668 struct irq_remap_table *table)
3669 {
3670 irq_lookup_table[devid] = table;
3671 set_dte_irq_entry(devid, table);
3672 iommu_flush_dte(iommu, devid);
3673 }
3674
3675 static struct irq_remap_table *alloc_irq_table(u16 devid)
3676 {
3677 struct irq_remap_table *table = NULL;
3678 struct irq_remap_table *new_table = NULL;
3679 struct amd_iommu *iommu;
3680 unsigned long flags;
3681 u16 alias;
3682
3683 spin_lock_irqsave(&iommu_table_lock, flags);
3684
3685 iommu = amd_iommu_rlookup_table[devid];
3686 if (!iommu)
3687 goto out_unlock;
3688
3689 table = irq_lookup_table[devid];
3690 if (table)
3691 goto out_unlock;
3692
3693 alias = amd_iommu_alias_table[devid];
3694 table = irq_lookup_table[alias];
3695 if (table) {
3696 set_remap_table_entry(iommu, devid, table);
3697 goto out_wait;
3698 }
3699 spin_unlock_irqrestore(&iommu_table_lock, flags);
3700
3701 /* Nothing there yet, allocate new irq remapping table */
3702 new_table = __alloc_irq_table();
3703 if (!new_table)
3704 return NULL;
3705
3706 spin_lock_irqsave(&iommu_table_lock, flags);
3707
3708 table = irq_lookup_table[devid];
3709 if (table)
3710 goto out_unlock;
3711
3712 table = irq_lookup_table[alias];
3713 if (table) {
3714 set_remap_table_entry(iommu, devid, table);
3715 goto out_wait;
3716 }
3717
3718 table = new_table;
3719 new_table = NULL;
3720
3721 set_remap_table_entry(iommu, devid, table);
3722 if (devid != alias)
3723 set_remap_table_entry(iommu, alias, table);
3724
3725 out_wait:
3726 iommu_completion_wait(iommu);
3727
3728 out_unlock:
3729 spin_unlock_irqrestore(&iommu_table_lock, flags);
3730
3731 if (new_table) {
3732 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3733 kfree(new_table);
3734 }
3735 return table;
3736 }
3737
3738 static int alloc_irq_index(u16 devid, int count, bool align)
3739 {
3740 struct irq_remap_table *table;
3741 int index, c, alignment = 1;
3742 unsigned long flags;
3743 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3744
3745 if (!iommu)
3746 return -ENODEV;
3747
3748 table = alloc_irq_table(devid);
3749 if (!table)
3750 return -ENODEV;
3751
3752 if (align)
3753 alignment = roundup_pow_of_two(count);
3754
3755 raw_spin_lock_irqsave(&table->lock, flags);
3756
3757 /* Scan table for free entries */
3758 for (index = ALIGN(table->min_index, alignment), c = 0;
3759 index < MAX_IRQS_PER_TABLE;) {
3760 if (!iommu->irte_ops->is_allocated(table, index)) {
3761 c += 1;
3762 } else {
3763 c = 0;
3764 index = ALIGN(index + 1, alignment);
3765 continue;
3766 }
3767
3768 if (c == count) {
3769 for (; c != 0; --c)
3770 iommu->irte_ops->set_allocated(table, index - c + 1);
3771
3772 index -= count - 1;
3773 goto out;
3774 }
3775
3776 index++;
3777 }
3778
3779 index = -ENOSPC;
3780
3781 out:
3782 raw_spin_unlock_irqrestore(&table->lock, flags);
3783
3784 return index;
3785 }
3786
3787 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3788 struct amd_ir_data *data)
3789 {
3790 struct irq_remap_table *table;
3791 struct amd_iommu *iommu;
3792 unsigned long flags;
3793 struct irte_ga *entry;
3794
3795 iommu = amd_iommu_rlookup_table[devid];
3796 if (iommu == NULL)
3797 return -EINVAL;
3798
3799 table = get_irq_table(devid);
3800 if (!table)
3801 return -ENOMEM;
3802
3803 raw_spin_lock_irqsave(&table->lock, flags);
3804
3805 entry = (struct irte_ga *)table->table;
3806 entry = &entry[index];
3807 entry->lo.fields_remap.valid = 0;
3808 entry->hi.val = irte->hi.val;
3809 entry->lo.val = irte->lo.val;
3810 entry->lo.fields_remap.valid = 1;
3811 if (data)
3812 data->ref = entry;
3813
3814 raw_spin_unlock_irqrestore(&table->lock, flags);
3815
3816 iommu_flush_irt(iommu, devid);
3817 iommu_completion_wait(iommu);
3818
3819 return 0;
3820 }
3821
3822 static int modify_irte(u16 devid, int index, union irte *irte)
3823 {
3824 struct irq_remap_table *table;
3825 struct amd_iommu *iommu;
3826 unsigned long flags;
3827
3828 iommu = amd_iommu_rlookup_table[devid];
3829 if (iommu == NULL)
3830 return -EINVAL;
3831
3832 table = get_irq_table(devid);
3833 if (!table)
3834 return -ENOMEM;
3835
3836 raw_spin_lock_irqsave(&table->lock, flags);
3837 table->table[index] = irte->val;
3838 raw_spin_unlock_irqrestore(&table->lock, flags);
3839
3840 iommu_flush_irt(iommu, devid);
3841 iommu_completion_wait(iommu);
3842
3843 return 0;
3844 }
3845
3846 static void free_irte(u16 devid, int index)
3847 {
3848 struct irq_remap_table *table;
3849 struct amd_iommu *iommu;
3850 unsigned long flags;
3851
3852 iommu = amd_iommu_rlookup_table[devid];
3853 if (iommu == NULL)
3854 return;
3855
3856 table = get_irq_table(devid);
3857 if (!table)
3858 return;
3859
3860 raw_spin_lock_irqsave(&table->lock, flags);
3861 iommu->irte_ops->clear_allocated(table, index);
3862 raw_spin_unlock_irqrestore(&table->lock, flags);
3863
3864 iommu_flush_irt(iommu, devid);
3865 iommu_completion_wait(iommu);
3866 }
3867
3868 static void irte_prepare(void *entry,
3869 u32 delivery_mode, u32 dest_mode,
3870 u8 vector, u32 dest_apicid, int devid)
3871 {
3872 union irte *irte = (union irte *) entry;
3873
3874 irte->val = 0;
3875 irte->fields.vector = vector;
3876 irte->fields.int_type = delivery_mode;
3877 irte->fields.destination = dest_apicid;
3878 irte->fields.dm = dest_mode;
3879 irte->fields.valid = 1;
3880 }
3881
3882 static void irte_ga_prepare(void *entry,
3883 u32 delivery_mode, u32 dest_mode,
3884 u8 vector, u32 dest_apicid, int devid)
3885 {
3886 struct irte_ga *irte = (struct irte_ga *) entry;
3887
3888 irte->lo.val = 0;
3889 irte->hi.val = 0;
3890 irte->lo.fields_remap.int_type = delivery_mode;
3891 irte->lo.fields_remap.dm = dest_mode;
3892 irte->hi.fields.vector = vector;
3893 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3894 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3895 irte->lo.fields_remap.valid = 1;
3896 }
3897
3898 static void irte_activate(void *entry, u16 devid, u16 index)
3899 {
3900 union irte *irte = (union irte *) entry;
3901
3902 irte->fields.valid = 1;
3903 modify_irte(devid, index, irte);
3904 }
3905
3906 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3907 {
3908 struct irte_ga *irte = (struct irte_ga *) entry;
3909
3910 irte->lo.fields_remap.valid = 1;
3911 modify_irte_ga(devid, index, irte, NULL);
3912 }
3913
3914 static void irte_deactivate(void *entry, u16 devid, u16 index)
3915 {
3916 union irte *irte = (union irte *) entry;
3917
3918 irte->fields.valid = 0;
3919 modify_irte(devid, index, irte);
3920 }
3921
3922 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3923 {
3924 struct irte_ga *irte = (struct irte_ga *) entry;
3925
3926 irte->lo.fields_remap.valid = 0;
3927 modify_irte_ga(devid, index, irte, NULL);
3928 }
3929
3930 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3931 u8 vector, u32 dest_apicid)
3932 {
3933 union irte *irte = (union irte *) entry;
3934
3935 irte->fields.vector = vector;
3936 irte->fields.destination = dest_apicid;
3937 modify_irte(devid, index, irte);
3938 }
3939
3940 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3941 u8 vector, u32 dest_apicid)
3942 {
3943 struct irte_ga *irte = (struct irte_ga *) entry;
3944
3945 if (!irte->lo.fields_remap.guest_mode) {
3946 irte->hi.fields.vector = vector;
3947 irte->lo.fields_remap.destination =
3948 APICID_TO_IRTE_DEST_LO(dest_apicid);
3949 irte->hi.fields.destination =
3950 APICID_TO_IRTE_DEST_HI(dest_apicid);
3951 modify_irte_ga(devid, index, irte, NULL);
3952 }
3953 }
3954
3955 #define IRTE_ALLOCATED (~1U)
3956 static void irte_set_allocated(struct irq_remap_table *table, int index)
3957 {
3958 table->table[index] = IRTE_ALLOCATED;
3959 }
3960
3961 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3962 {
3963 struct irte_ga *ptr = (struct irte_ga *)table->table;
3964 struct irte_ga *irte = &ptr[index];
3965
3966 memset(&irte->lo.val, 0, sizeof(u64));
3967 memset(&irte->hi.val, 0, sizeof(u64));
3968 irte->hi.fields.vector = 0xff;
3969 }
3970
3971 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3972 {
3973 union irte *ptr = (union irte *)table->table;
3974 union irte *irte = &ptr[index];
3975
3976 return irte->val != 0;
3977 }
3978
3979 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3980 {
3981 struct irte_ga *ptr = (struct irte_ga *)table->table;
3982 struct irte_ga *irte = &ptr[index];
3983
3984 return irte->hi.fields.vector != 0;
3985 }
3986
3987 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3988 {
3989 table->table[index] = 0;
3990 }
3991
3992 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3993 {
3994 struct irte_ga *ptr = (struct irte_ga *)table->table;
3995 struct irte_ga *irte = &ptr[index];
3996
3997 memset(&irte->lo.val, 0, sizeof(u64));
3998 memset(&irte->hi.val, 0, sizeof(u64));
3999 }
4000
4001 static int get_devid(struct irq_alloc_info *info)
4002 {
4003 int devid = -1;
4004
4005 switch (info->type) {
4006 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4007 devid = get_ioapic_devid(info->ioapic_id);
4008 break;
4009 case X86_IRQ_ALLOC_TYPE_HPET:
4010 devid = get_hpet_devid(info->hpet_id);
4011 break;
4012 case X86_IRQ_ALLOC_TYPE_MSI:
4013 case X86_IRQ_ALLOC_TYPE_MSIX:
4014 devid = get_device_id(&info->msi_dev->dev);
4015 break;
4016 default:
4017 BUG_ON(1);
4018 break;
4019 }
4020
4021 return devid;
4022 }
4023
4024 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4025 {
4026 struct amd_iommu *iommu;
4027 int devid;
4028
4029 if (!info)
4030 return NULL;
4031
4032 devid = get_devid(info);
4033 if (devid >= 0) {
4034 iommu = amd_iommu_rlookup_table[devid];
4035 if (iommu)
4036 return iommu->ir_domain;
4037 }
4038
4039 return NULL;
4040 }
4041
4042 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4043 {
4044 struct amd_iommu *iommu;
4045 int devid;
4046
4047 if (!info)
4048 return NULL;
4049
4050 switch (info->type) {
4051 case X86_IRQ_ALLOC_TYPE_MSI:
4052 case X86_IRQ_ALLOC_TYPE_MSIX:
4053 devid = get_device_id(&info->msi_dev->dev);
4054 if (devid < 0)
4055 return NULL;
4056
4057 iommu = amd_iommu_rlookup_table[devid];
4058 if (iommu)
4059 return iommu->msi_domain;
4060 break;
4061 default:
4062 break;
4063 }
4064
4065 return NULL;
4066 }
4067
4068 struct irq_remap_ops amd_iommu_irq_ops = {
4069 .prepare = amd_iommu_prepare,
4070 .enable = amd_iommu_enable,
4071 .disable = amd_iommu_disable,
4072 .reenable = amd_iommu_reenable,
4073 .enable_faulting = amd_iommu_enable_faulting,
4074 .get_ir_irq_domain = get_ir_irq_domain,
4075 .get_irq_domain = get_irq_domain,
4076 };
4077
4078 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4079 struct irq_cfg *irq_cfg,
4080 struct irq_alloc_info *info,
4081 int devid, int index, int sub_handle)
4082 {
4083 struct irq_2_irte *irte_info = &data->irq_2_irte;
4084 struct msi_msg *msg = &data->msi_entry;
4085 struct IO_APIC_route_entry *entry;
4086 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4087
4088 if (!iommu)
4089 return;
4090
4091 data->irq_2_irte.devid = devid;
4092 data->irq_2_irte.index = index + sub_handle;
4093 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4094 apic->irq_dest_mode, irq_cfg->vector,
4095 irq_cfg->dest_apicid, devid);
4096
4097 switch (info->type) {
4098 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4099 /* Setup IOAPIC entry */
4100 entry = info->ioapic_entry;
4101 info->ioapic_entry = NULL;
4102 memset(entry, 0, sizeof(*entry));
4103 entry->vector = index;
4104 entry->mask = 0;
4105 entry->trigger = info->ioapic_trigger;
4106 entry->polarity = info->ioapic_polarity;
4107 /* Mask level triggered irqs. */
4108 if (info->ioapic_trigger)
4109 entry->mask = 1;
4110 break;
4111
4112 case X86_IRQ_ALLOC_TYPE_HPET:
4113 case X86_IRQ_ALLOC_TYPE_MSI:
4114 case X86_IRQ_ALLOC_TYPE_MSIX:
4115 msg->address_hi = MSI_ADDR_BASE_HI;
4116 msg->address_lo = MSI_ADDR_BASE_LO;
4117 msg->data = irte_info->index;
4118 break;
4119
4120 default:
4121 BUG_ON(1);
4122 break;
4123 }
4124 }
4125
4126 struct amd_irte_ops irte_32_ops = {
4127 .prepare = irte_prepare,
4128 .activate = irte_activate,
4129 .deactivate = irte_deactivate,
4130 .set_affinity = irte_set_affinity,
4131 .set_allocated = irte_set_allocated,
4132 .is_allocated = irte_is_allocated,
4133 .clear_allocated = irte_clear_allocated,
4134 };
4135
4136 struct amd_irte_ops irte_128_ops = {
4137 .prepare = irte_ga_prepare,
4138 .activate = irte_ga_activate,
4139 .deactivate = irte_ga_deactivate,
4140 .set_affinity = irte_ga_set_affinity,
4141 .set_allocated = irte_ga_set_allocated,
4142 .is_allocated = irte_ga_is_allocated,
4143 .clear_allocated = irte_ga_clear_allocated,
4144 };
4145
4146 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4147 unsigned int nr_irqs, void *arg)
4148 {
4149 struct irq_alloc_info *info = arg;
4150 struct irq_data *irq_data;
4151 struct amd_ir_data *data = NULL;
4152 struct irq_cfg *cfg;
4153 int i, ret, devid;
4154 int index;
4155
4156 if (!info)
4157 return -EINVAL;
4158 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4159 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4160 return -EINVAL;
4161
4162 /*
4163 * With IRQ remapping enabled, don't need contiguous CPU vectors
4164 * to support multiple MSI interrupts.
4165 */
4166 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4167 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4168
4169 devid = get_devid(info);
4170 if (devid < 0)
4171 return -EINVAL;
4172
4173 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4174 if (ret < 0)
4175 return ret;
4176
4177 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4178 struct irq_remap_table *table;
4179 struct amd_iommu *iommu;
4180
4181 table = alloc_irq_table(devid);
4182 if (table) {
4183 if (!table->min_index) {
4184 /*
4185 * Keep the first 32 indexes free for IOAPIC
4186 * interrupts.
4187 */
4188 table->min_index = 32;
4189 iommu = amd_iommu_rlookup_table[devid];
4190 for (i = 0; i < 32; ++i)
4191 iommu->irte_ops->set_allocated(table, i);
4192 }
4193 WARN_ON(table->min_index != 32);
4194 index = info->ioapic_pin;
4195 } else {
4196 index = -ENOMEM;
4197 }
4198 } else {
4199 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4200
4201 index = alloc_irq_index(devid, nr_irqs, align);
4202 }
4203 if (index < 0) {
4204 pr_warn("Failed to allocate IRTE\n");
4205 ret = index;
4206 goto out_free_parent;
4207 }
4208
4209 for (i = 0; i < nr_irqs; i++) {
4210 irq_data = irq_domain_get_irq_data(domain, virq + i);
4211 cfg = irqd_cfg(irq_data);
4212 if (!irq_data || !cfg) {
4213 ret = -EINVAL;
4214 goto out_free_data;
4215 }
4216
4217 ret = -ENOMEM;
4218 data = kzalloc(sizeof(*data), GFP_KERNEL);
4219 if (!data)
4220 goto out_free_data;
4221
4222 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4223 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4224 else
4225 data->entry = kzalloc(sizeof(struct irte_ga),
4226 GFP_KERNEL);
4227 if (!data->entry) {
4228 kfree(data);
4229 goto out_free_data;
4230 }
4231
4232 irq_data->hwirq = (devid << 16) + i;
4233 irq_data->chip_data = data;
4234 irq_data->chip = &amd_ir_chip;
4235 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4236 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4237 }
4238
4239 return 0;
4240
4241 out_free_data:
4242 for (i--; i >= 0; i--) {
4243 irq_data = irq_domain_get_irq_data(domain, virq + i);
4244 if (irq_data)
4245 kfree(irq_data->chip_data);
4246 }
4247 for (i = 0; i < nr_irqs; i++)
4248 free_irte(devid, index + i);
4249 out_free_parent:
4250 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4251 return ret;
4252 }
4253
4254 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4255 unsigned int nr_irqs)
4256 {
4257 struct irq_2_irte *irte_info;
4258 struct irq_data *irq_data;
4259 struct amd_ir_data *data;
4260 int i;
4261
4262 for (i = 0; i < nr_irqs; i++) {
4263 irq_data = irq_domain_get_irq_data(domain, virq + i);
4264 if (irq_data && irq_data->chip_data) {
4265 data = irq_data->chip_data;
4266 irte_info = &data->irq_2_irte;
4267 free_irte(irte_info->devid, irte_info->index);
4268 kfree(data->entry);
4269 kfree(data);
4270 }
4271 }
4272 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4273 }
4274
4275 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4276 struct amd_ir_data *ir_data,
4277 struct irq_2_irte *irte_info,
4278 struct irq_cfg *cfg);
4279
4280 static int irq_remapping_activate(struct irq_domain *domain,
4281 struct irq_data *irq_data, bool reserve)
4282 {
4283 struct amd_ir_data *data = irq_data->chip_data;
4284 struct irq_2_irte *irte_info = &data->irq_2_irte;
4285 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4286 struct irq_cfg *cfg = irqd_cfg(irq_data);
4287
4288 if (!iommu)
4289 return 0;
4290
4291 iommu->irte_ops->activate(data->entry, irte_info->devid,
4292 irte_info->index);
4293 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4294 return 0;
4295 }
4296
4297 static void irq_remapping_deactivate(struct irq_domain *domain,
4298 struct irq_data *irq_data)
4299 {
4300 struct amd_ir_data *data = irq_data->chip_data;
4301 struct irq_2_irte *irte_info = &data->irq_2_irte;
4302 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4303
4304 if (iommu)
4305 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4306 irte_info->index);
4307 }
4308
4309 static const struct irq_domain_ops amd_ir_domain_ops = {
4310 .alloc = irq_remapping_alloc,
4311 .free = irq_remapping_free,
4312 .activate = irq_remapping_activate,
4313 .deactivate = irq_remapping_deactivate,
4314 };
4315
4316 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4317 {
4318 struct amd_iommu *iommu;
4319 struct amd_iommu_pi_data *pi_data = vcpu_info;
4320 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4321 struct amd_ir_data *ir_data = data->chip_data;
4322 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4323 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4324 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4325
4326 /* Note:
4327 * This device has never been set up for guest mode.
4328 * we should not modify the IRTE
4329 */
4330 if (!dev_data || !dev_data->use_vapic)
4331 return 0;
4332
4333 pi_data->ir_data = ir_data;
4334
4335 /* Note:
4336 * SVM tries to set up for VAPIC mode, but we are in
4337 * legacy mode. So, we force legacy mode instead.
4338 */
4339 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4340 pr_debug("%s: Fall back to using intr legacy remap\n",
4341 __func__);
4342 pi_data->is_guest_mode = false;
4343 }
4344
4345 iommu = amd_iommu_rlookup_table[irte_info->devid];
4346 if (iommu == NULL)
4347 return -EINVAL;
4348
4349 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4350 if (pi_data->is_guest_mode) {
4351 /* Setting */
4352 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4353 irte->hi.fields.vector = vcpu_pi_info->vector;
4354 irte->lo.fields_vapic.ga_log_intr = 1;
4355 irte->lo.fields_vapic.guest_mode = 1;
4356 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4357
4358 ir_data->cached_ga_tag = pi_data->ga_tag;
4359 } else {
4360 /* Un-Setting */
4361 struct irq_cfg *cfg = irqd_cfg(data);
4362
4363 irte->hi.val = 0;
4364 irte->lo.val = 0;
4365 irte->hi.fields.vector = cfg->vector;
4366 irte->lo.fields_remap.guest_mode = 0;
4367 irte->lo.fields_remap.destination =
4368 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4369 irte->hi.fields.destination =
4370 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4371 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4372 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4373
4374 /*
4375 * This communicates the ga_tag back to the caller
4376 * so that it can do all the necessary clean up.
4377 */
4378 ir_data->cached_ga_tag = 0;
4379 }
4380
4381 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4382 }
4383
4384
4385 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4386 struct amd_ir_data *ir_data,
4387 struct irq_2_irte *irte_info,
4388 struct irq_cfg *cfg)
4389 {
4390
4391 /*
4392 * Atomically updates the IRTE with the new destination, vector
4393 * and flushes the interrupt entry cache.
4394 */
4395 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4396 irte_info->index, cfg->vector,
4397 cfg->dest_apicid);
4398 }
4399
4400 static int amd_ir_set_affinity(struct irq_data *data,
4401 const struct cpumask *mask, bool force)
4402 {
4403 struct amd_ir_data *ir_data = data->chip_data;
4404 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4405 struct irq_cfg *cfg = irqd_cfg(data);
4406 struct irq_data *parent = data->parent_data;
4407 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4408 int ret;
4409
4410 if (!iommu)
4411 return -ENODEV;
4412
4413 ret = parent->chip->irq_set_affinity(parent, mask, force);
4414 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4415 return ret;
4416
4417 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4418 /*
4419 * After this point, all the interrupts will start arriving
4420 * at the new destination. So, time to cleanup the previous
4421 * vector allocation.
4422 */
4423 send_cleanup_vector(cfg);
4424
4425 return IRQ_SET_MASK_OK_DONE;
4426 }
4427
4428 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4429 {
4430 struct amd_ir_data *ir_data = irq_data->chip_data;
4431
4432 *msg = ir_data->msi_entry;
4433 }
4434
4435 static struct irq_chip amd_ir_chip = {
4436 .name = "AMD-IR",
4437 .irq_ack = apic_ack_irq,
4438 .irq_set_affinity = amd_ir_set_affinity,
4439 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4440 .irq_compose_msi_msg = ir_compose_msi_msg,
4441 };
4442
4443 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4444 {
4445 struct fwnode_handle *fn;
4446
4447 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4448 if (!fn)
4449 return -ENOMEM;
4450 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4451 irq_domain_free_fwnode(fn);
4452 if (!iommu->ir_domain)
4453 return -ENOMEM;
4454
4455 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4456 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4457 "AMD-IR-MSI",
4458 iommu->index);
4459 return 0;
4460 }
4461
4462 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4463 {
4464 unsigned long flags;
4465 struct amd_iommu *iommu;
4466 struct irq_remap_table *table;
4467 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4468 int devid = ir_data->irq_2_irte.devid;
4469 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4470 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4471
4472 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4473 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4474 return 0;
4475
4476 iommu = amd_iommu_rlookup_table[devid];
4477 if (!iommu)
4478 return -ENODEV;
4479
4480 table = get_irq_table(devid);
4481 if (!table)
4482 return -ENODEV;
4483
4484 raw_spin_lock_irqsave(&table->lock, flags);
4485
4486 if (ref->lo.fields_vapic.guest_mode) {
4487 if (cpu >= 0) {
4488 ref->lo.fields_vapic.destination =
4489 APICID_TO_IRTE_DEST_LO(cpu);
4490 ref->hi.fields.destination =
4491 APICID_TO_IRTE_DEST_HI(cpu);
4492 }
4493 ref->lo.fields_vapic.is_run = is_run;
4494 barrier();
4495 }
4496
4497 raw_spin_unlock_irqrestore(&table->lock, flags);
4498
4499 iommu_flush_irt(iommu, devid);
4500 iommu_completion_wait(iommu);
4501 return 0;
4502 }
4503 EXPORT_SYMBOL(amd_iommu_update_ga);
4504 #endif
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