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[thirdparty/linux.git] / drivers / iommu / amd_iommu.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/iommu.h>
26 #include <linux/delay.h>
27 #include <linux/amd-iommu.h>
28 #include <linux/notifier.h>
29 #include <linux/export.h>
30 #include <linux/irq.h>
31 #include <linux/msi.h>
32 #include <linux/dma-contiguous.h>
33 #include <linux/irqdomain.h>
34 #include <linux/percpu.h>
35 #include <linux/iova.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/io_apic.h>
38 #include <asm/apic.h>
39 #include <asm/hw_irq.h>
40 #include <asm/msidef.h>
41 #include <asm/proto.h>
42 #include <asm/iommu.h>
43 #include <asm/gart.h>
44 #include <asm/dma.h>
45
46 #include "amd_iommu_proto.h"
47 #include "amd_iommu_types.h"
48 #include "irq_remapping.h"
49
50 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
51
52 #define LOOP_TIMEOUT 100000
53
54 /* IO virtual address start page frame number */
55 #define IOVA_START_PFN (1)
56 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
57
58 /* Reserved IOVA ranges */
59 #define MSI_RANGE_START (0xfee00000)
60 #define MSI_RANGE_END (0xfeefffff)
61 #define HT_RANGE_START (0xfd00000000ULL)
62 #define HT_RANGE_END (0xffffffffffULL)
63
64 /*
65 * This bitmap is used to advertise the page sizes our hardware support
66 * to the IOMMU core, which will then use this information to split
67 * physically contiguous memory regions it is mapping into page sizes
68 * that we support.
69 *
70 * 512GB Pages are not supported due to a hardware bug
71 */
72 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
73
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
75
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
78
79 LIST_HEAD(ioapic_map);
80 LIST_HEAD(hpet_map);
81 LIST_HEAD(acpihid_map);
82
83 /*
84 * Domain for untranslated devices - only allocated
85 * if iommu=pt passed on kernel cmd line.
86 */
87 const struct iommu_ops amd_iommu_ops;
88
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
91
92 /*
93 * general struct to manage commands send to an IOMMU
94 */
95 struct iommu_cmd {
96 u32 data[4];
97 };
98
99 struct kmem_cache *amd_iommu_irq_cache;
100
101 static void update_domain(struct protection_domain *domain);
102 static int protection_domain_init(struct protection_domain *domain);
103 static void detach_device(struct device *dev);
104
105 /****************************************************************************
106 *
107 * Helper functions
108 *
109 ****************************************************************************/
110
111 static inline u16 get_pci_device_id(struct device *dev)
112 {
113 struct pci_dev *pdev = to_pci_dev(dev);
114
115 return pci_dev_id(pdev);
116 }
117
118 static inline int get_acpihid_device_id(struct device *dev,
119 struct acpihid_map_entry **entry)
120 {
121 struct acpi_device *adev = ACPI_COMPANION(dev);
122 struct acpihid_map_entry *p;
123
124 if (!adev)
125 return -ENODEV;
126
127 list_for_each_entry(p, &acpihid_map, list) {
128 if (acpi_dev_hid_uid_match(adev, p->hid, p->uid)) {
129 if (entry)
130 *entry = p;
131 return p->devid;
132 }
133 }
134 return -EINVAL;
135 }
136
137 static inline int get_device_id(struct device *dev)
138 {
139 int devid;
140
141 if (dev_is_pci(dev))
142 devid = get_pci_device_id(dev);
143 else
144 devid = get_acpihid_device_id(dev, NULL);
145
146 return devid;
147 }
148
149 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
150 {
151 return container_of(dom, struct protection_domain, domain);
152 }
153
154 static struct iommu_dev_data *alloc_dev_data(u16 devid)
155 {
156 struct iommu_dev_data *dev_data;
157
158 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
159 if (!dev_data)
160 return NULL;
161
162 spin_lock_init(&dev_data->lock);
163 dev_data->devid = devid;
164 ratelimit_default_init(&dev_data->rs);
165
166 llist_add(&dev_data->dev_data_list, &dev_data_list);
167 return dev_data;
168 }
169
170 static struct iommu_dev_data *search_dev_data(u16 devid)
171 {
172 struct iommu_dev_data *dev_data;
173 struct llist_node *node;
174
175 if (llist_empty(&dev_data_list))
176 return NULL;
177
178 node = dev_data_list.first;
179 llist_for_each_entry(dev_data, node, dev_data_list) {
180 if (dev_data->devid == devid)
181 return dev_data;
182 }
183
184 return NULL;
185 }
186
187 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
188 {
189 u16 devid = pci_dev_id(pdev);
190
191 if (devid == alias)
192 return 0;
193
194 amd_iommu_rlookup_table[alias] =
195 amd_iommu_rlookup_table[devid];
196 memcpy(amd_iommu_dev_table[alias].data,
197 amd_iommu_dev_table[devid].data,
198 sizeof(amd_iommu_dev_table[alias].data));
199
200 return 0;
201 }
202
203 static void clone_aliases(struct pci_dev *pdev)
204 {
205 if (!pdev)
206 return;
207
208 /*
209 * The IVRS alias stored in the alias table may not be
210 * part of the PCI DMA aliases if it's bus differs
211 * from the original device.
212 */
213 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
214
215 pci_for_each_dma_alias(pdev, clone_alias, NULL);
216 }
217
218 static struct pci_dev *setup_aliases(struct device *dev)
219 {
220 struct pci_dev *pdev = to_pci_dev(dev);
221 u16 ivrs_alias;
222
223 /* For ACPI HID devices, there are no aliases */
224 if (!dev_is_pci(dev))
225 return NULL;
226
227 /*
228 * Add the IVRS alias to the pci aliases if it is on the same
229 * bus. The IVRS table may know about a quirk that we don't.
230 */
231 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
232 if (ivrs_alias != pci_dev_id(pdev) &&
233 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
234 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
235
236 clone_aliases(pdev);
237
238 return pdev;
239 }
240
241 static struct iommu_dev_data *find_dev_data(u16 devid)
242 {
243 struct iommu_dev_data *dev_data;
244 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
245
246 dev_data = search_dev_data(devid);
247
248 if (dev_data == NULL) {
249 dev_data = alloc_dev_data(devid);
250 if (!dev_data)
251 return NULL;
252
253 if (translation_pre_enabled(iommu))
254 dev_data->defer_attach = true;
255 }
256
257 return dev_data;
258 }
259
260 struct iommu_dev_data *get_dev_data(struct device *dev)
261 {
262 return dev->archdata.iommu;
263 }
264 EXPORT_SYMBOL(get_dev_data);
265
266 /*
267 * Find or create an IOMMU group for a acpihid device.
268 */
269 static struct iommu_group *acpihid_device_group(struct device *dev)
270 {
271 struct acpihid_map_entry *p, *entry = NULL;
272 int devid;
273
274 devid = get_acpihid_device_id(dev, &entry);
275 if (devid < 0)
276 return ERR_PTR(devid);
277
278 list_for_each_entry(p, &acpihid_map, list) {
279 if ((devid == p->devid) && p->group)
280 entry->group = p->group;
281 }
282
283 if (!entry->group)
284 entry->group = generic_device_group(dev);
285 else
286 iommu_group_ref_get(entry->group);
287
288 return entry->group;
289 }
290
291 static bool pci_iommuv2_capable(struct pci_dev *pdev)
292 {
293 static const int caps[] = {
294 PCI_EXT_CAP_ID_ATS,
295 PCI_EXT_CAP_ID_PRI,
296 PCI_EXT_CAP_ID_PASID,
297 };
298 int i, pos;
299
300 if (pci_ats_disabled())
301 return false;
302
303 for (i = 0; i < 3; ++i) {
304 pos = pci_find_ext_capability(pdev, caps[i]);
305 if (pos == 0)
306 return false;
307 }
308
309 return true;
310 }
311
312 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
313 {
314 struct iommu_dev_data *dev_data;
315
316 dev_data = get_dev_data(&pdev->dev);
317
318 return dev_data->errata & (1 << erratum) ? true : false;
319 }
320
321 /*
322 * This function checks if the driver got a valid device from the caller to
323 * avoid dereferencing invalid pointers.
324 */
325 static bool check_device(struct device *dev)
326 {
327 int devid;
328
329 if (!dev || !dev->dma_mask)
330 return false;
331
332 devid = get_device_id(dev);
333 if (devid < 0)
334 return false;
335
336 /* Out of our scope? */
337 if (devid > amd_iommu_last_bdf)
338 return false;
339
340 if (amd_iommu_rlookup_table[devid] == NULL)
341 return false;
342
343 return true;
344 }
345
346 static void init_iommu_group(struct device *dev)
347 {
348 struct iommu_group *group;
349
350 group = iommu_group_get_for_dev(dev);
351 if (IS_ERR(group))
352 return;
353
354 iommu_group_put(group);
355 }
356
357 static int iommu_init_device(struct device *dev)
358 {
359 struct iommu_dev_data *dev_data;
360 struct amd_iommu *iommu;
361 int devid;
362
363 if (dev->archdata.iommu)
364 return 0;
365
366 devid = get_device_id(dev);
367 if (devid < 0)
368 return devid;
369
370 iommu = amd_iommu_rlookup_table[devid];
371
372 dev_data = find_dev_data(devid);
373 if (!dev_data)
374 return -ENOMEM;
375
376 dev_data->pdev = setup_aliases(dev);
377
378 /*
379 * By default we use passthrough mode for IOMMUv2 capable device.
380 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
381 * invalid address), we ignore the capability for the device so
382 * it'll be forced to go into translation mode.
383 */
384 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
385 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
386 struct amd_iommu *iommu;
387
388 iommu = amd_iommu_rlookup_table[dev_data->devid];
389 dev_data->iommu_v2 = iommu->is_iommu_v2;
390 }
391
392 dev->archdata.iommu = dev_data;
393
394 iommu_device_link(&iommu->iommu, dev);
395
396 return 0;
397 }
398
399 static void iommu_ignore_device(struct device *dev)
400 {
401 int devid;
402
403 devid = get_device_id(dev);
404 if (devid < 0)
405 return;
406
407 amd_iommu_rlookup_table[devid] = NULL;
408 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
409
410 setup_aliases(dev);
411 }
412
413 static void iommu_uninit_device(struct device *dev)
414 {
415 struct iommu_dev_data *dev_data;
416 struct amd_iommu *iommu;
417 int devid;
418
419 devid = get_device_id(dev);
420 if (devid < 0)
421 return;
422
423 iommu = amd_iommu_rlookup_table[devid];
424
425 dev_data = search_dev_data(devid);
426 if (!dev_data)
427 return;
428
429 if (dev_data->domain)
430 detach_device(dev);
431
432 iommu_device_unlink(&iommu->iommu, dev);
433
434 iommu_group_remove_device(dev);
435
436 /* Remove dma-ops */
437 dev->dma_ops = NULL;
438
439 /*
440 * We keep dev_data around for unplugged devices and reuse it when the
441 * device is re-plugged - not doing so would introduce a ton of races.
442 */
443 }
444
445 /*
446 * Helper function to get the first pte of a large mapping
447 */
448 static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
449 unsigned long *count)
450 {
451 unsigned long pte_mask, pg_size, cnt;
452 u64 *fpte;
453
454 pg_size = PTE_PAGE_SIZE(*pte);
455 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
456 pte_mask = ~((cnt << 3) - 1);
457 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
458
459 if (page_size)
460 *page_size = pg_size;
461
462 if (count)
463 *count = cnt;
464
465 return fpte;
466 }
467
468 /****************************************************************************
469 *
470 * Interrupt handling functions
471 *
472 ****************************************************************************/
473
474 static void dump_dte_entry(u16 devid)
475 {
476 int i;
477
478 for (i = 0; i < 4; ++i)
479 pr_err("DTE[%d]: %016llx\n", i,
480 amd_iommu_dev_table[devid].data[i]);
481 }
482
483 static void dump_command(unsigned long phys_addr)
484 {
485 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
486 int i;
487
488 for (i = 0; i < 4; ++i)
489 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
490 }
491
492 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
493 u64 address, int flags)
494 {
495 struct iommu_dev_data *dev_data = NULL;
496 struct pci_dev *pdev;
497
498 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
499 devid & 0xff);
500 if (pdev)
501 dev_data = get_dev_data(&pdev->dev);
502
503 if (dev_data && __ratelimit(&dev_data->rs)) {
504 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
505 domain_id, address, flags);
506 } else if (printk_ratelimit()) {
507 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
508 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
509 domain_id, address, flags);
510 }
511
512 if (pdev)
513 pci_dev_put(pdev);
514 }
515
516 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
517 {
518 struct device *dev = iommu->iommu.dev;
519 int type, devid, pasid, flags, tag;
520 volatile u32 *event = __evt;
521 int count = 0;
522 u64 address;
523
524 retry:
525 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
526 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
527 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
528 (event[1] & EVENT_DOMID_MASK_LO);
529 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
530 address = (u64)(((u64)event[3]) << 32) | event[2];
531
532 if (type == 0) {
533 /* Did we hit the erratum? */
534 if (++count == LOOP_TIMEOUT) {
535 pr_err("No event written to event log\n");
536 return;
537 }
538 udelay(1);
539 goto retry;
540 }
541
542 if (type == EVENT_TYPE_IO_FAULT) {
543 amd_iommu_report_page_fault(devid, pasid, address, flags);
544 return;
545 }
546
547 switch (type) {
548 case EVENT_TYPE_ILL_DEV:
549 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
550 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
551 pasid, address, flags);
552 dump_dte_entry(devid);
553 break;
554 case EVENT_TYPE_DEV_TAB_ERR:
555 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
556 "address=0x%llx flags=0x%04x]\n",
557 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
558 address, flags);
559 break;
560 case EVENT_TYPE_PAGE_TAB_ERR:
561 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
562 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
563 pasid, address, flags);
564 break;
565 case EVENT_TYPE_ILL_CMD:
566 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
567 dump_command(address);
568 break;
569 case EVENT_TYPE_CMD_HARD_ERR:
570 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
571 address, flags);
572 break;
573 case EVENT_TYPE_IOTLB_INV_TO:
574 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
575 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
576 address);
577 break;
578 case EVENT_TYPE_INV_DEV_REQ:
579 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
580 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
581 pasid, address, flags);
582 break;
583 case EVENT_TYPE_INV_PPR_REQ:
584 pasid = PPR_PASID(*((u64 *)__evt));
585 tag = event[1] & 0x03FF;
586 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
587 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
588 pasid, address, flags, tag);
589 break;
590 default:
591 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
592 event[0], event[1], event[2], event[3]);
593 }
594
595 memset(__evt, 0, 4 * sizeof(u32));
596 }
597
598 static void iommu_poll_events(struct amd_iommu *iommu)
599 {
600 u32 head, tail;
601
602 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
603 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
604
605 while (head != tail) {
606 iommu_print_event(iommu, iommu->evt_buf + head);
607 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
608 }
609
610 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
611 }
612
613 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
614 {
615 struct amd_iommu_fault fault;
616
617 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
618 pr_err_ratelimited("Unknown PPR request received\n");
619 return;
620 }
621
622 fault.address = raw[1];
623 fault.pasid = PPR_PASID(raw[0]);
624 fault.device_id = PPR_DEVID(raw[0]);
625 fault.tag = PPR_TAG(raw[0]);
626 fault.flags = PPR_FLAGS(raw[0]);
627
628 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
629 }
630
631 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
632 {
633 u32 head, tail;
634
635 if (iommu->ppr_log == NULL)
636 return;
637
638 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
639 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
640
641 while (head != tail) {
642 volatile u64 *raw;
643 u64 entry[2];
644 int i;
645
646 raw = (u64 *)(iommu->ppr_log + head);
647
648 /*
649 * Hardware bug: Interrupt may arrive before the entry is
650 * written to memory. If this happens we need to wait for the
651 * entry to arrive.
652 */
653 for (i = 0; i < LOOP_TIMEOUT; ++i) {
654 if (PPR_REQ_TYPE(raw[0]) != 0)
655 break;
656 udelay(1);
657 }
658
659 /* Avoid memcpy function-call overhead */
660 entry[0] = raw[0];
661 entry[1] = raw[1];
662
663 /*
664 * To detect the hardware bug we need to clear the entry
665 * back to zero.
666 */
667 raw[0] = raw[1] = 0UL;
668
669 /* Update head pointer of hardware ring-buffer */
670 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
671 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
672
673 /* Handle PPR entry */
674 iommu_handle_ppr_entry(iommu, entry);
675
676 /* Refresh ring-buffer information */
677 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
678 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
679 }
680 }
681
682 #ifdef CONFIG_IRQ_REMAP
683 static int (*iommu_ga_log_notifier)(u32);
684
685 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
686 {
687 iommu_ga_log_notifier = notifier;
688
689 return 0;
690 }
691 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
692
693 static void iommu_poll_ga_log(struct amd_iommu *iommu)
694 {
695 u32 head, tail, cnt = 0;
696
697 if (iommu->ga_log == NULL)
698 return;
699
700 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
701 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
702
703 while (head != tail) {
704 volatile u64 *raw;
705 u64 log_entry;
706
707 raw = (u64 *)(iommu->ga_log + head);
708 cnt++;
709
710 /* Avoid memcpy function-call overhead */
711 log_entry = *raw;
712
713 /* Update head pointer of hardware ring-buffer */
714 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
715 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
716
717 /* Handle GA entry */
718 switch (GA_REQ_TYPE(log_entry)) {
719 case GA_GUEST_NR:
720 if (!iommu_ga_log_notifier)
721 break;
722
723 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
724 __func__, GA_DEVID(log_entry),
725 GA_TAG(log_entry));
726
727 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
728 pr_err("GA log notifier failed.\n");
729 break;
730 default:
731 break;
732 }
733 }
734 }
735 #endif /* CONFIG_IRQ_REMAP */
736
737 #define AMD_IOMMU_INT_MASK \
738 (MMIO_STATUS_EVT_INT_MASK | \
739 MMIO_STATUS_PPR_INT_MASK | \
740 MMIO_STATUS_GALOG_INT_MASK)
741
742 irqreturn_t amd_iommu_int_thread(int irq, void *data)
743 {
744 struct amd_iommu *iommu = (struct amd_iommu *) data;
745 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
746
747 while (status & AMD_IOMMU_INT_MASK) {
748 /* Enable EVT and PPR and GA interrupts again */
749 writel(AMD_IOMMU_INT_MASK,
750 iommu->mmio_base + MMIO_STATUS_OFFSET);
751
752 if (status & MMIO_STATUS_EVT_INT_MASK) {
753 pr_devel("Processing IOMMU Event Log\n");
754 iommu_poll_events(iommu);
755 }
756
757 if (status & MMIO_STATUS_PPR_INT_MASK) {
758 pr_devel("Processing IOMMU PPR Log\n");
759 iommu_poll_ppr_log(iommu);
760 }
761
762 #ifdef CONFIG_IRQ_REMAP
763 if (status & MMIO_STATUS_GALOG_INT_MASK) {
764 pr_devel("Processing IOMMU GA Log\n");
765 iommu_poll_ga_log(iommu);
766 }
767 #endif
768
769 /*
770 * Hardware bug: ERBT1312
771 * When re-enabling interrupt (by writing 1
772 * to clear the bit), the hardware might also try to set
773 * the interrupt bit in the event status register.
774 * In this scenario, the bit will be set, and disable
775 * subsequent interrupts.
776 *
777 * Workaround: The IOMMU driver should read back the
778 * status register and check if the interrupt bits are cleared.
779 * If not, driver will need to go through the interrupt handler
780 * again and re-clear the bits
781 */
782 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
783 }
784 return IRQ_HANDLED;
785 }
786
787 irqreturn_t amd_iommu_int_handler(int irq, void *data)
788 {
789 return IRQ_WAKE_THREAD;
790 }
791
792 /****************************************************************************
793 *
794 * IOMMU command queuing functions
795 *
796 ****************************************************************************/
797
798 static int wait_on_sem(volatile u64 *sem)
799 {
800 int i = 0;
801
802 while (*sem == 0 && i < LOOP_TIMEOUT) {
803 udelay(1);
804 i += 1;
805 }
806
807 if (i == LOOP_TIMEOUT) {
808 pr_alert("Completion-Wait loop timed out\n");
809 return -EIO;
810 }
811
812 return 0;
813 }
814
815 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
816 struct iommu_cmd *cmd)
817 {
818 u8 *target;
819 u32 tail;
820
821 /* Copy command to buffer */
822 tail = iommu->cmd_buf_tail;
823 target = iommu->cmd_buf + tail;
824 memcpy(target, cmd, sizeof(*cmd));
825
826 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
827 iommu->cmd_buf_tail = tail;
828
829 /* Tell the IOMMU about it */
830 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
831 }
832
833 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
834 {
835 u64 paddr = iommu_virt_to_phys((void *)address);
836
837 WARN_ON(address & 0x7ULL);
838
839 memset(cmd, 0, sizeof(*cmd));
840 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
841 cmd->data[1] = upper_32_bits(paddr);
842 cmd->data[2] = 1;
843 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
844 }
845
846 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
847 {
848 memset(cmd, 0, sizeof(*cmd));
849 cmd->data[0] = devid;
850 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
851 }
852
853 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
854 size_t size, u16 domid, int pde)
855 {
856 u64 pages;
857 bool s;
858
859 pages = iommu_num_pages(address, size, PAGE_SIZE);
860 s = false;
861
862 if (pages > 1) {
863 /*
864 * If we have to flush more than one page, flush all
865 * TLB entries for this domain
866 */
867 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
868 s = true;
869 }
870
871 address &= PAGE_MASK;
872
873 memset(cmd, 0, sizeof(*cmd));
874 cmd->data[1] |= domid;
875 cmd->data[2] = lower_32_bits(address);
876 cmd->data[3] = upper_32_bits(address);
877 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
878 if (s) /* size bit - we flush more than one 4kb page */
879 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
880 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
881 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
882 }
883
884 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
885 u64 address, size_t size)
886 {
887 u64 pages;
888 bool s;
889
890 pages = iommu_num_pages(address, size, PAGE_SIZE);
891 s = false;
892
893 if (pages > 1) {
894 /*
895 * If we have to flush more than one page, flush all
896 * TLB entries for this domain
897 */
898 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
899 s = true;
900 }
901
902 address &= PAGE_MASK;
903
904 memset(cmd, 0, sizeof(*cmd));
905 cmd->data[0] = devid;
906 cmd->data[0] |= (qdep & 0xff) << 24;
907 cmd->data[1] = devid;
908 cmd->data[2] = lower_32_bits(address);
909 cmd->data[3] = upper_32_bits(address);
910 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
911 if (s)
912 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
913 }
914
915 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
916 u64 address, bool size)
917 {
918 memset(cmd, 0, sizeof(*cmd));
919
920 address &= ~(0xfffULL);
921
922 cmd->data[0] = pasid;
923 cmd->data[1] = domid;
924 cmd->data[2] = lower_32_bits(address);
925 cmd->data[3] = upper_32_bits(address);
926 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
927 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
928 if (size)
929 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
930 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
931 }
932
933 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
934 int qdep, u64 address, bool size)
935 {
936 memset(cmd, 0, sizeof(*cmd));
937
938 address &= ~(0xfffULL);
939
940 cmd->data[0] = devid;
941 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
942 cmd->data[0] |= (qdep & 0xff) << 24;
943 cmd->data[1] = devid;
944 cmd->data[1] |= (pasid & 0xff) << 16;
945 cmd->data[2] = lower_32_bits(address);
946 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
947 cmd->data[3] = upper_32_bits(address);
948 if (size)
949 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
950 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
951 }
952
953 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
954 int status, int tag, bool gn)
955 {
956 memset(cmd, 0, sizeof(*cmd));
957
958 cmd->data[0] = devid;
959 if (gn) {
960 cmd->data[1] = pasid;
961 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
962 }
963 cmd->data[3] = tag & 0x1ff;
964 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
965
966 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
967 }
968
969 static void build_inv_all(struct iommu_cmd *cmd)
970 {
971 memset(cmd, 0, sizeof(*cmd));
972 CMD_SET_TYPE(cmd, CMD_INV_ALL);
973 }
974
975 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
976 {
977 memset(cmd, 0, sizeof(*cmd));
978 cmd->data[0] = devid;
979 CMD_SET_TYPE(cmd, CMD_INV_IRT);
980 }
981
982 /*
983 * Writes the command to the IOMMUs command buffer and informs the
984 * hardware about the new command.
985 */
986 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
987 struct iommu_cmd *cmd,
988 bool sync)
989 {
990 unsigned int count = 0;
991 u32 left, next_tail;
992
993 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
994 again:
995 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
996
997 if (left <= 0x20) {
998 /* Skip udelay() the first time around */
999 if (count++) {
1000 if (count == LOOP_TIMEOUT) {
1001 pr_err("Command buffer timeout\n");
1002 return -EIO;
1003 }
1004
1005 udelay(1);
1006 }
1007
1008 /* Update head and recheck remaining space */
1009 iommu->cmd_buf_head = readl(iommu->mmio_base +
1010 MMIO_CMD_HEAD_OFFSET);
1011
1012 goto again;
1013 }
1014
1015 copy_cmd_to_buffer(iommu, cmd);
1016
1017 /* Do we need to make sure all commands are processed? */
1018 iommu->need_sync = sync;
1019
1020 return 0;
1021 }
1022
1023 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1024 struct iommu_cmd *cmd,
1025 bool sync)
1026 {
1027 unsigned long flags;
1028 int ret;
1029
1030 raw_spin_lock_irqsave(&iommu->lock, flags);
1031 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1032 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1033
1034 return ret;
1035 }
1036
1037 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1038 {
1039 return iommu_queue_command_sync(iommu, cmd, true);
1040 }
1041
1042 /*
1043 * This function queues a completion wait command into the command
1044 * buffer of an IOMMU
1045 */
1046 static int iommu_completion_wait(struct amd_iommu *iommu)
1047 {
1048 struct iommu_cmd cmd;
1049 unsigned long flags;
1050 int ret;
1051
1052 if (!iommu->need_sync)
1053 return 0;
1054
1055
1056 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1057
1058 raw_spin_lock_irqsave(&iommu->lock, flags);
1059
1060 iommu->cmd_sem = 0;
1061
1062 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1063 if (ret)
1064 goto out_unlock;
1065
1066 ret = wait_on_sem(&iommu->cmd_sem);
1067
1068 out_unlock:
1069 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1070
1071 return ret;
1072 }
1073
1074 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1075 {
1076 struct iommu_cmd cmd;
1077
1078 build_inv_dte(&cmd, devid);
1079
1080 return iommu_queue_command(iommu, &cmd);
1081 }
1082
1083 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1084 {
1085 u32 devid;
1086
1087 for (devid = 0; devid <= 0xffff; ++devid)
1088 iommu_flush_dte(iommu, devid);
1089
1090 iommu_completion_wait(iommu);
1091 }
1092
1093 /*
1094 * This function uses heavy locking and may disable irqs for some time. But
1095 * this is no issue because it is only called during resume.
1096 */
1097 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1098 {
1099 u32 dom_id;
1100
1101 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1102 struct iommu_cmd cmd;
1103 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1104 dom_id, 1);
1105 iommu_queue_command(iommu, &cmd);
1106 }
1107
1108 iommu_completion_wait(iommu);
1109 }
1110
1111 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1112 {
1113 struct iommu_cmd cmd;
1114
1115 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1116 dom_id, 1);
1117 iommu_queue_command(iommu, &cmd);
1118
1119 iommu_completion_wait(iommu);
1120 }
1121
1122 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1123 {
1124 struct iommu_cmd cmd;
1125
1126 build_inv_all(&cmd);
1127
1128 iommu_queue_command(iommu, &cmd);
1129 iommu_completion_wait(iommu);
1130 }
1131
1132 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1133 {
1134 struct iommu_cmd cmd;
1135
1136 build_inv_irt(&cmd, devid);
1137
1138 iommu_queue_command(iommu, &cmd);
1139 }
1140
1141 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1142 {
1143 u32 devid;
1144
1145 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1146 iommu_flush_irt(iommu, devid);
1147
1148 iommu_completion_wait(iommu);
1149 }
1150
1151 void iommu_flush_all_caches(struct amd_iommu *iommu)
1152 {
1153 if (iommu_feature(iommu, FEATURE_IA)) {
1154 amd_iommu_flush_all(iommu);
1155 } else {
1156 amd_iommu_flush_dte_all(iommu);
1157 amd_iommu_flush_irt_all(iommu);
1158 amd_iommu_flush_tlb_all(iommu);
1159 }
1160 }
1161
1162 /*
1163 * Command send function for flushing on-device TLB
1164 */
1165 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1166 u64 address, size_t size)
1167 {
1168 struct amd_iommu *iommu;
1169 struct iommu_cmd cmd;
1170 int qdep;
1171
1172 qdep = dev_data->ats.qdep;
1173 iommu = amd_iommu_rlookup_table[dev_data->devid];
1174
1175 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1176
1177 return iommu_queue_command(iommu, &cmd);
1178 }
1179
1180 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1181 {
1182 struct amd_iommu *iommu = data;
1183
1184 return iommu_flush_dte(iommu, alias);
1185 }
1186
1187 /*
1188 * Command send function for invalidating a device table entry
1189 */
1190 static int device_flush_dte(struct iommu_dev_data *dev_data)
1191 {
1192 struct amd_iommu *iommu;
1193 u16 alias;
1194 int ret;
1195
1196 iommu = amd_iommu_rlookup_table[dev_data->devid];
1197
1198 if (dev_data->pdev)
1199 ret = pci_for_each_dma_alias(dev_data->pdev,
1200 device_flush_dte_alias, iommu);
1201 else
1202 ret = iommu_flush_dte(iommu, dev_data->devid);
1203 if (ret)
1204 return ret;
1205
1206 alias = amd_iommu_alias_table[dev_data->devid];
1207 if (alias != dev_data->devid) {
1208 ret = iommu_flush_dte(iommu, alias);
1209 if (ret)
1210 return ret;
1211 }
1212
1213 if (dev_data->ats.enabled)
1214 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1215
1216 return ret;
1217 }
1218
1219 /*
1220 * TLB invalidation function which is called from the mapping functions.
1221 * It invalidates a single PTE if the range to flush is within a single
1222 * page. Otherwise it flushes the whole TLB of the IOMMU.
1223 */
1224 static void __domain_flush_pages(struct protection_domain *domain,
1225 u64 address, size_t size, int pde)
1226 {
1227 struct iommu_dev_data *dev_data;
1228 struct iommu_cmd cmd;
1229 int ret = 0, i;
1230
1231 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1232
1233 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1234 if (!domain->dev_iommu[i])
1235 continue;
1236
1237 /*
1238 * Devices of this domain are behind this IOMMU
1239 * We need a TLB flush
1240 */
1241 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1242 }
1243
1244 list_for_each_entry(dev_data, &domain->dev_list, list) {
1245
1246 if (!dev_data->ats.enabled)
1247 continue;
1248
1249 ret |= device_flush_iotlb(dev_data, address, size);
1250 }
1251
1252 WARN_ON(ret);
1253 }
1254
1255 static void domain_flush_pages(struct protection_domain *domain,
1256 u64 address, size_t size)
1257 {
1258 __domain_flush_pages(domain, address, size, 0);
1259 }
1260
1261 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1262 static void domain_flush_tlb_pde(struct protection_domain *domain)
1263 {
1264 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1265 }
1266
1267 static void domain_flush_complete(struct protection_domain *domain)
1268 {
1269 int i;
1270
1271 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1272 if (domain && !domain->dev_iommu[i])
1273 continue;
1274
1275 /*
1276 * Devices of this domain are behind this IOMMU
1277 * We need to wait for completion of all commands.
1278 */
1279 iommu_completion_wait(amd_iommus[i]);
1280 }
1281 }
1282
1283 /* Flush the not present cache if it exists */
1284 static void domain_flush_np_cache(struct protection_domain *domain,
1285 dma_addr_t iova, size_t size)
1286 {
1287 if (unlikely(amd_iommu_np_cache)) {
1288 unsigned long flags;
1289
1290 spin_lock_irqsave(&domain->lock, flags);
1291 domain_flush_pages(domain, iova, size);
1292 domain_flush_complete(domain);
1293 spin_unlock_irqrestore(&domain->lock, flags);
1294 }
1295 }
1296
1297
1298 /*
1299 * This function flushes the DTEs for all devices in domain
1300 */
1301 static void domain_flush_devices(struct protection_domain *domain)
1302 {
1303 struct iommu_dev_data *dev_data;
1304
1305 list_for_each_entry(dev_data, &domain->dev_list, list)
1306 device_flush_dte(dev_data);
1307 }
1308
1309 /****************************************************************************
1310 *
1311 * The functions below are used the create the page table mappings for
1312 * unity mapped regions.
1313 *
1314 ****************************************************************************/
1315
1316 static void free_page_list(struct page *freelist)
1317 {
1318 while (freelist != NULL) {
1319 unsigned long p = (unsigned long)page_address(freelist);
1320 freelist = freelist->freelist;
1321 free_page(p);
1322 }
1323 }
1324
1325 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1326 {
1327 struct page *p = virt_to_page((void *)pt);
1328
1329 p->freelist = freelist;
1330
1331 return p;
1332 }
1333
1334 #define DEFINE_FREE_PT_FN(LVL, FN) \
1335 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1336 { \
1337 unsigned long p; \
1338 u64 *pt; \
1339 int i; \
1340 \
1341 pt = (u64 *)__pt; \
1342 \
1343 for (i = 0; i < 512; ++i) { \
1344 /* PTE present? */ \
1345 if (!IOMMU_PTE_PRESENT(pt[i])) \
1346 continue; \
1347 \
1348 /* Large PTE? */ \
1349 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1350 PM_PTE_LEVEL(pt[i]) == 7) \
1351 continue; \
1352 \
1353 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1354 freelist = FN(p, freelist); \
1355 } \
1356 \
1357 return free_pt_page((unsigned long)pt, freelist); \
1358 }
1359
1360 DEFINE_FREE_PT_FN(l2, free_pt_page)
1361 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1362 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1363 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1364 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1365
1366 static struct page *free_sub_pt(unsigned long root, int mode,
1367 struct page *freelist)
1368 {
1369 switch (mode) {
1370 case PAGE_MODE_NONE:
1371 case PAGE_MODE_7_LEVEL:
1372 break;
1373 case PAGE_MODE_1_LEVEL:
1374 freelist = free_pt_page(root, freelist);
1375 break;
1376 case PAGE_MODE_2_LEVEL:
1377 freelist = free_pt_l2(root, freelist);
1378 break;
1379 case PAGE_MODE_3_LEVEL:
1380 freelist = free_pt_l3(root, freelist);
1381 break;
1382 case PAGE_MODE_4_LEVEL:
1383 freelist = free_pt_l4(root, freelist);
1384 break;
1385 case PAGE_MODE_5_LEVEL:
1386 freelist = free_pt_l5(root, freelist);
1387 break;
1388 case PAGE_MODE_6_LEVEL:
1389 freelist = free_pt_l6(root, freelist);
1390 break;
1391 default:
1392 BUG();
1393 }
1394
1395 return freelist;
1396 }
1397
1398 static void free_pagetable(struct protection_domain *domain)
1399 {
1400 unsigned long root = (unsigned long)domain->pt_root;
1401 struct page *freelist = NULL;
1402
1403 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1404 domain->mode > PAGE_MODE_6_LEVEL);
1405
1406 freelist = free_sub_pt(root, domain->mode, freelist);
1407
1408 free_page_list(freelist);
1409 }
1410
1411 /*
1412 * This function is used to add another level to an IO page table. Adding
1413 * another level increases the size of the address space by 9 bits to a size up
1414 * to 64 bits.
1415 */
1416 static bool increase_address_space(struct protection_domain *domain,
1417 unsigned long address,
1418 gfp_t gfp)
1419 {
1420 unsigned long flags;
1421 bool ret = false;
1422 u64 *pte;
1423
1424 spin_lock_irqsave(&domain->lock, flags);
1425
1426 if (address <= PM_LEVEL_SIZE(domain->mode) ||
1427 WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1428 goto out;
1429
1430 pte = (void *)get_zeroed_page(gfp);
1431 if (!pte)
1432 goto out;
1433
1434 *pte = PM_LEVEL_PDE(domain->mode,
1435 iommu_virt_to_phys(domain->pt_root));
1436 domain->pt_root = pte;
1437 domain->mode += 1;
1438
1439 ret = true;
1440
1441 out:
1442 spin_unlock_irqrestore(&domain->lock, flags);
1443
1444 return ret;
1445 }
1446
1447 static u64 *alloc_pte(struct protection_domain *domain,
1448 unsigned long address,
1449 unsigned long page_size,
1450 u64 **pte_page,
1451 gfp_t gfp,
1452 bool *updated)
1453 {
1454 int level, end_lvl;
1455 u64 *pte, *page;
1456
1457 BUG_ON(!is_power_of_2(page_size));
1458
1459 while (address > PM_LEVEL_SIZE(domain->mode))
1460 *updated = increase_address_space(domain, address, gfp) || *updated;
1461
1462 level = domain->mode - 1;
1463 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1464 address = PAGE_SIZE_ALIGN(address, page_size);
1465 end_lvl = PAGE_SIZE_LEVEL(page_size);
1466
1467 while (level > end_lvl) {
1468 u64 __pte, __npte;
1469 int pte_level;
1470
1471 __pte = *pte;
1472 pte_level = PM_PTE_LEVEL(__pte);
1473
1474 /*
1475 * If we replace a series of large PTEs, we need
1476 * to tear down all of them.
1477 */
1478 if (IOMMU_PTE_PRESENT(__pte) &&
1479 pte_level == PAGE_MODE_7_LEVEL) {
1480 unsigned long count, i;
1481 u64 *lpte;
1482
1483 lpte = first_pte_l7(pte, NULL, &count);
1484
1485 /*
1486 * Unmap the replicated PTEs that still match the
1487 * original large mapping
1488 */
1489 for (i = 0; i < count; ++i)
1490 cmpxchg64(&lpte[i], __pte, 0ULL);
1491
1492 *updated = true;
1493 continue;
1494 }
1495
1496 if (!IOMMU_PTE_PRESENT(__pte) ||
1497 pte_level == PAGE_MODE_NONE) {
1498 page = (u64 *)get_zeroed_page(gfp);
1499
1500 if (!page)
1501 return NULL;
1502
1503 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1504
1505 /* pte could have been changed somewhere. */
1506 if (cmpxchg64(pte, __pte, __npte) != __pte)
1507 free_page((unsigned long)page);
1508 else if (IOMMU_PTE_PRESENT(__pte))
1509 *updated = true;
1510
1511 continue;
1512 }
1513
1514 /* No level skipping support yet */
1515 if (pte_level != level)
1516 return NULL;
1517
1518 level -= 1;
1519
1520 pte = IOMMU_PTE_PAGE(__pte);
1521
1522 if (pte_page && level == end_lvl)
1523 *pte_page = pte;
1524
1525 pte = &pte[PM_LEVEL_INDEX(level, address)];
1526 }
1527
1528 return pte;
1529 }
1530
1531 /*
1532 * This function checks if there is a PTE for a given dma address. If
1533 * there is one, it returns the pointer to it.
1534 */
1535 static u64 *fetch_pte(struct protection_domain *domain,
1536 unsigned long address,
1537 unsigned long *page_size)
1538 {
1539 int level;
1540 u64 *pte;
1541
1542 *page_size = 0;
1543
1544 if (address > PM_LEVEL_SIZE(domain->mode))
1545 return NULL;
1546
1547 level = domain->mode - 1;
1548 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1549 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1550
1551 while (level > 0) {
1552
1553 /* Not Present */
1554 if (!IOMMU_PTE_PRESENT(*pte))
1555 return NULL;
1556
1557 /* Large PTE */
1558 if (PM_PTE_LEVEL(*pte) == 7 ||
1559 PM_PTE_LEVEL(*pte) == 0)
1560 break;
1561
1562 /* No level skipping support yet */
1563 if (PM_PTE_LEVEL(*pte) != level)
1564 return NULL;
1565
1566 level -= 1;
1567
1568 /* Walk to the next level */
1569 pte = IOMMU_PTE_PAGE(*pte);
1570 pte = &pte[PM_LEVEL_INDEX(level, address)];
1571 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1572 }
1573
1574 /*
1575 * If we have a series of large PTEs, make
1576 * sure to return a pointer to the first one.
1577 */
1578 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1579 pte = first_pte_l7(pte, page_size, NULL);
1580
1581 return pte;
1582 }
1583
1584 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1585 {
1586 unsigned long pt;
1587 int mode;
1588
1589 while (cmpxchg64(pte, pteval, 0) != pteval) {
1590 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1591 pteval = *pte;
1592 }
1593
1594 if (!IOMMU_PTE_PRESENT(pteval))
1595 return freelist;
1596
1597 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1598 mode = IOMMU_PTE_MODE(pteval);
1599
1600 return free_sub_pt(pt, mode, freelist);
1601 }
1602
1603 /*
1604 * Generic mapping functions. It maps a physical address into a DMA
1605 * address space. It allocates the page table pages if necessary.
1606 * In the future it can be extended to a generic mapping function
1607 * supporting all features of AMD IOMMU page tables like level skipping
1608 * and full 64 bit address spaces.
1609 */
1610 static int iommu_map_page(struct protection_domain *dom,
1611 unsigned long bus_addr,
1612 unsigned long phys_addr,
1613 unsigned long page_size,
1614 int prot,
1615 gfp_t gfp)
1616 {
1617 struct page *freelist = NULL;
1618 bool updated = false;
1619 u64 __pte, *pte;
1620 int ret, i, count;
1621
1622 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1623 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1624
1625 ret = -EINVAL;
1626 if (!(prot & IOMMU_PROT_MASK))
1627 goto out;
1628
1629 count = PAGE_SIZE_PTE_COUNT(page_size);
1630 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1631
1632 ret = -ENOMEM;
1633 if (!pte)
1634 goto out;
1635
1636 for (i = 0; i < count; ++i)
1637 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1638
1639 if (freelist != NULL)
1640 updated = true;
1641
1642 if (count > 1) {
1643 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1644 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1645 } else
1646 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1647
1648 if (prot & IOMMU_PROT_IR)
1649 __pte |= IOMMU_PTE_IR;
1650 if (prot & IOMMU_PROT_IW)
1651 __pte |= IOMMU_PTE_IW;
1652
1653 for (i = 0; i < count; ++i)
1654 pte[i] = __pte;
1655
1656 ret = 0;
1657
1658 out:
1659 if (updated) {
1660 unsigned long flags;
1661
1662 spin_lock_irqsave(&dom->lock, flags);
1663 update_domain(dom);
1664 spin_unlock_irqrestore(&dom->lock, flags);
1665 }
1666
1667 /* Everything flushed out, free pages now */
1668 free_page_list(freelist);
1669
1670 return ret;
1671 }
1672
1673 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1674 unsigned long bus_addr,
1675 unsigned long page_size)
1676 {
1677 unsigned long long unmapped;
1678 unsigned long unmap_size;
1679 u64 *pte;
1680
1681 BUG_ON(!is_power_of_2(page_size));
1682
1683 unmapped = 0;
1684
1685 while (unmapped < page_size) {
1686
1687 pte = fetch_pte(dom, bus_addr, &unmap_size);
1688
1689 if (pte) {
1690 int i, count;
1691
1692 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1693 for (i = 0; i < count; i++)
1694 pte[i] = 0ULL;
1695 }
1696
1697 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1698 unmapped += unmap_size;
1699 }
1700
1701 BUG_ON(unmapped && !is_power_of_2(unmapped));
1702
1703 return unmapped;
1704 }
1705
1706 /****************************************************************************
1707 *
1708 * The next functions belong to the domain allocation. A domain is
1709 * allocated for every IOMMU as the default domain. If device isolation
1710 * is enabled, every device get its own domain. The most important thing
1711 * about domains is the page table mapping the DMA address space they
1712 * contain.
1713 *
1714 ****************************************************************************/
1715
1716 static u16 domain_id_alloc(void)
1717 {
1718 int id;
1719
1720 spin_lock(&pd_bitmap_lock);
1721 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1722 BUG_ON(id == 0);
1723 if (id > 0 && id < MAX_DOMAIN_ID)
1724 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1725 else
1726 id = 0;
1727 spin_unlock(&pd_bitmap_lock);
1728
1729 return id;
1730 }
1731
1732 static void domain_id_free(int id)
1733 {
1734 spin_lock(&pd_bitmap_lock);
1735 if (id > 0 && id < MAX_DOMAIN_ID)
1736 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1737 spin_unlock(&pd_bitmap_lock);
1738 }
1739
1740 static void free_gcr3_tbl_level1(u64 *tbl)
1741 {
1742 u64 *ptr;
1743 int i;
1744
1745 for (i = 0; i < 512; ++i) {
1746 if (!(tbl[i] & GCR3_VALID))
1747 continue;
1748
1749 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1750
1751 free_page((unsigned long)ptr);
1752 }
1753 }
1754
1755 static void free_gcr3_tbl_level2(u64 *tbl)
1756 {
1757 u64 *ptr;
1758 int i;
1759
1760 for (i = 0; i < 512; ++i) {
1761 if (!(tbl[i] & GCR3_VALID))
1762 continue;
1763
1764 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1765
1766 free_gcr3_tbl_level1(ptr);
1767 }
1768 }
1769
1770 static void free_gcr3_table(struct protection_domain *domain)
1771 {
1772 if (domain->glx == 2)
1773 free_gcr3_tbl_level2(domain->gcr3_tbl);
1774 else if (domain->glx == 1)
1775 free_gcr3_tbl_level1(domain->gcr3_tbl);
1776 else
1777 BUG_ON(domain->glx != 0);
1778
1779 free_page((unsigned long)domain->gcr3_tbl);
1780 }
1781
1782 /*
1783 * Free a domain, only used if something went wrong in the
1784 * allocation path and we need to free an already allocated page table
1785 */
1786 static void dma_ops_domain_free(struct protection_domain *domain)
1787 {
1788 if (!domain)
1789 return;
1790
1791 iommu_put_dma_cookie(&domain->domain);
1792
1793 free_pagetable(domain);
1794
1795 if (domain->id)
1796 domain_id_free(domain->id);
1797
1798 kfree(domain);
1799 }
1800
1801 /*
1802 * Allocates a new protection domain usable for the dma_ops functions.
1803 * It also initializes the page table and the address allocator data
1804 * structures required for the dma_ops interface
1805 */
1806 static struct protection_domain *dma_ops_domain_alloc(void)
1807 {
1808 struct protection_domain *domain;
1809
1810 domain = kzalloc(sizeof(struct protection_domain), GFP_KERNEL);
1811 if (!domain)
1812 return NULL;
1813
1814 if (protection_domain_init(domain))
1815 goto free_domain;
1816
1817 domain->mode = PAGE_MODE_3_LEVEL;
1818 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1819 domain->flags = PD_DMA_OPS_MASK;
1820 if (!domain->pt_root)
1821 goto free_domain;
1822
1823 if (iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
1824 goto free_domain;
1825
1826 return domain;
1827
1828 free_domain:
1829 dma_ops_domain_free(domain);
1830
1831 return NULL;
1832 }
1833
1834 /*
1835 * little helper function to check whether a given protection domain is a
1836 * dma_ops domain
1837 */
1838 static bool dma_ops_domain(struct protection_domain *domain)
1839 {
1840 return domain->flags & PD_DMA_OPS_MASK;
1841 }
1842
1843 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1844 bool ats, bool ppr)
1845 {
1846 u64 pte_root = 0;
1847 u64 flags = 0;
1848 u32 old_domid;
1849
1850 if (domain->mode != PAGE_MODE_NONE)
1851 pte_root = iommu_virt_to_phys(domain->pt_root);
1852
1853 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1854 << DEV_ENTRY_MODE_SHIFT;
1855 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1856
1857 flags = amd_iommu_dev_table[devid].data[1];
1858
1859 if (ats)
1860 flags |= DTE_FLAG_IOTLB;
1861
1862 if (ppr) {
1863 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1864
1865 if (iommu_feature(iommu, FEATURE_EPHSUP))
1866 pte_root |= 1ULL << DEV_ENTRY_PPR;
1867 }
1868
1869 if (domain->flags & PD_IOMMUV2_MASK) {
1870 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1871 u64 glx = domain->glx;
1872 u64 tmp;
1873
1874 pte_root |= DTE_FLAG_GV;
1875 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1876
1877 /* First mask out possible old values for GCR3 table */
1878 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1879 flags &= ~tmp;
1880
1881 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1882 flags &= ~tmp;
1883
1884 /* Encode GCR3 table into DTE */
1885 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1886 pte_root |= tmp;
1887
1888 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1889 flags |= tmp;
1890
1891 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1892 flags |= tmp;
1893 }
1894
1895 flags &= ~DEV_DOMID_MASK;
1896 flags |= domain->id;
1897
1898 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1899 amd_iommu_dev_table[devid].data[1] = flags;
1900 amd_iommu_dev_table[devid].data[0] = pte_root;
1901
1902 /*
1903 * A kdump kernel might be replacing a domain ID that was copied from
1904 * the previous kernel--if so, it needs to flush the translation cache
1905 * entries for the old domain ID that is being overwritten
1906 */
1907 if (old_domid) {
1908 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1909
1910 amd_iommu_flush_tlb_domid(iommu, old_domid);
1911 }
1912 }
1913
1914 static void clear_dte_entry(u16 devid)
1915 {
1916 /* remove entry from the device table seen by the hardware */
1917 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1918 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1919
1920 amd_iommu_apply_erratum_63(devid);
1921 }
1922
1923 static void do_attach(struct iommu_dev_data *dev_data,
1924 struct protection_domain *domain)
1925 {
1926 struct amd_iommu *iommu;
1927 bool ats;
1928
1929 iommu = amd_iommu_rlookup_table[dev_data->devid];
1930 ats = dev_data->ats.enabled;
1931
1932 /* Update data structures */
1933 dev_data->domain = domain;
1934 list_add(&dev_data->list, &domain->dev_list);
1935
1936 /* Do reference counting */
1937 domain->dev_iommu[iommu->index] += 1;
1938 domain->dev_cnt += 1;
1939
1940 /* Update device table */
1941 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1942 clone_aliases(dev_data->pdev);
1943
1944 device_flush_dte(dev_data);
1945 }
1946
1947 static void do_detach(struct iommu_dev_data *dev_data)
1948 {
1949 struct protection_domain *domain = dev_data->domain;
1950 struct amd_iommu *iommu;
1951
1952 iommu = amd_iommu_rlookup_table[dev_data->devid];
1953
1954 /* Update data structures */
1955 dev_data->domain = NULL;
1956 list_del(&dev_data->list);
1957 clear_dte_entry(dev_data->devid);
1958 clone_aliases(dev_data->pdev);
1959
1960 /* Flush the DTE entry */
1961 device_flush_dte(dev_data);
1962
1963 /* Flush IOTLB */
1964 domain_flush_tlb_pde(domain);
1965
1966 /* Wait for the flushes to finish */
1967 domain_flush_complete(domain);
1968
1969 /* decrease reference counters - needs to happen after the flushes */
1970 domain->dev_iommu[iommu->index] -= 1;
1971 domain->dev_cnt -= 1;
1972 }
1973
1974 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1975 {
1976 pci_disable_ats(pdev);
1977 pci_disable_pri(pdev);
1978 pci_disable_pasid(pdev);
1979 }
1980
1981 /* FIXME: Change generic reset-function to do the same */
1982 static int pri_reset_while_enabled(struct pci_dev *pdev)
1983 {
1984 u16 control;
1985 int pos;
1986
1987 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1988 if (!pos)
1989 return -EINVAL;
1990
1991 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1992 control |= PCI_PRI_CTRL_RESET;
1993 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1994
1995 return 0;
1996 }
1997
1998 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1999 {
2000 bool reset_enable;
2001 int reqs, ret;
2002
2003 /* FIXME: Hardcode number of outstanding requests for now */
2004 reqs = 32;
2005 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2006 reqs = 1;
2007 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2008
2009 /* Only allow access to user-accessible pages */
2010 ret = pci_enable_pasid(pdev, 0);
2011 if (ret)
2012 goto out_err;
2013
2014 /* First reset the PRI state of the device */
2015 ret = pci_reset_pri(pdev);
2016 if (ret)
2017 goto out_err;
2018
2019 /* Enable PRI */
2020 ret = pci_enable_pri(pdev, reqs);
2021 if (ret)
2022 goto out_err;
2023
2024 if (reset_enable) {
2025 ret = pri_reset_while_enabled(pdev);
2026 if (ret)
2027 goto out_err;
2028 }
2029
2030 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2031 if (ret)
2032 goto out_err;
2033
2034 return 0;
2035
2036 out_err:
2037 pci_disable_pri(pdev);
2038 pci_disable_pasid(pdev);
2039
2040 return ret;
2041 }
2042
2043 /*
2044 * If a device is not yet associated with a domain, this function makes the
2045 * device visible in the domain
2046 */
2047 static int attach_device(struct device *dev,
2048 struct protection_domain *domain)
2049 {
2050 struct pci_dev *pdev;
2051 struct iommu_dev_data *dev_data;
2052 unsigned long flags;
2053 int ret;
2054
2055 spin_lock_irqsave(&domain->lock, flags);
2056
2057 dev_data = get_dev_data(dev);
2058
2059 spin_lock(&dev_data->lock);
2060
2061 ret = -EBUSY;
2062 if (dev_data->domain != NULL)
2063 goto out;
2064
2065 if (!dev_is_pci(dev))
2066 goto skip_ats_check;
2067
2068 pdev = to_pci_dev(dev);
2069 if (domain->flags & PD_IOMMUV2_MASK) {
2070 ret = -EINVAL;
2071 if (!dev_data->passthrough)
2072 goto out;
2073
2074 if (dev_data->iommu_v2) {
2075 if (pdev_iommuv2_enable(pdev) != 0)
2076 goto out;
2077
2078 dev_data->ats.enabled = true;
2079 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2080 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2081 }
2082 } else if (amd_iommu_iotlb_sup &&
2083 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2084 dev_data->ats.enabled = true;
2085 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2086 }
2087
2088 skip_ats_check:
2089 ret = 0;
2090
2091 do_attach(dev_data, domain);
2092
2093 /*
2094 * We might boot into a crash-kernel here. The crashed kernel
2095 * left the caches in the IOMMU dirty. So we have to flush
2096 * here to evict all dirty stuff.
2097 */
2098 domain_flush_tlb_pde(domain);
2099
2100 domain_flush_complete(domain);
2101
2102 out:
2103 spin_unlock(&dev_data->lock);
2104
2105 spin_unlock_irqrestore(&domain->lock, flags);
2106
2107 return ret;
2108 }
2109
2110 /*
2111 * Removes a device from a protection domain (with devtable_lock held)
2112 */
2113 static void detach_device(struct device *dev)
2114 {
2115 struct protection_domain *domain;
2116 struct iommu_dev_data *dev_data;
2117 unsigned long flags;
2118
2119 dev_data = get_dev_data(dev);
2120 domain = dev_data->domain;
2121
2122 spin_lock_irqsave(&domain->lock, flags);
2123
2124 spin_lock(&dev_data->lock);
2125
2126 /*
2127 * First check if the device is still attached. It might already
2128 * be detached from its domain because the generic
2129 * iommu_detach_group code detached it and we try again here in
2130 * our alias handling.
2131 */
2132 if (WARN_ON(!dev_data->domain))
2133 goto out;
2134
2135 do_detach(dev_data);
2136
2137 if (!dev_is_pci(dev))
2138 goto out;
2139
2140 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2141 pdev_iommuv2_disable(to_pci_dev(dev));
2142 else if (dev_data->ats.enabled)
2143 pci_disable_ats(to_pci_dev(dev));
2144
2145 dev_data->ats.enabled = false;
2146
2147 out:
2148 spin_unlock(&dev_data->lock);
2149
2150 spin_unlock_irqrestore(&domain->lock, flags);
2151 }
2152
2153 static int amd_iommu_add_device(struct device *dev)
2154 {
2155 struct iommu_dev_data *dev_data;
2156 struct iommu_domain *domain;
2157 struct amd_iommu *iommu;
2158 int ret, devid;
2159
2160 if (!check_device(dev) || get_dev_data(dev))
2161 return 0;
2162
2163 devid = get_device_id(dev);
2164 if (devid < 0)
2165 return devid;
2166
2167 iommu = amd_iommu_rlookup_table[devid];
2168
2169 ret = iommu_init_device(dev);
2170 if (ret) {
2171 if (ret != -ENOTSUPP)
2172 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2173
2174 iommu_ignore_device(dev);
2175 dev->dma_ops = NULL;
2176 goto out;
2177 }
2178 init_iommu_group(dev);
2179
2180 dev_data = get_dev_data(dev);
2181
2182 BUG_ON(!dev_data);
2183
2184 if (dev_data->iommu_v2)
2185 iommu_request_dm_for_dev(dev);
2186
2187 /* Domains are initialized for this device - have a look what we ended up with */
2188 domain = iommu_get_domain_for_dev(dev);
2189 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2190 dev_data->passthrough = true;
2191 else if (domain->type == IOMMU_DOMAIN_DMA)
2192 iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
2193
2194 out:
2195 iommu_completion_wait(iommu);
2196
2197 return 0;
2198 }
2199
2200 static void amd_iommu_remove_device(struct device *dev)
2201 {
2202 struct amd_iommu *iommu;
2203 int devid;
2204
2205 if (!check_device(dev))
2206 return;
2207
2208 devid = get_device_id(dev);
2209 if (devid < 0)
2210 return;
2211
2212 iommu = amd_iommu_rlookup_table[devid];
2213
2214 iommu_uninit_device(dev);
2215 iommu_completion_wait(iommu);
2216 }
2217
2218 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2219 {
2220 if (dev_is_pci(dev))
2221 return pci_device_group(dev);
2222
2223 return acpihid_device_group(dev);
2224 }
2225
2226 static int amd_iommu_domain_get_attr(struct iommu_domain *domain,
2227 enum iommu_attr attr, void *data)
2228 {
2229 switch (domain->type) {
2230 case IOMMU_DOMAIN_UNMANAGED:
2231 return -ENODEV;
2232 case IOMMU_DOMAIN_DMA:
2233 switch (attr) {
2234 case DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE:
2235 *(int *)data = !amd_iommu_unmap_flush;
2236 return 0;
2237 default:
2238 return -ENODEV;
2239 }
2240 break;
2241 default:
2242 return -EINVAL;
2243 }
2244 }
2245
2246 /*****************************************************************************
2247 *
2248 * The next functions belong to the dma_ops mapping/unmapping code.
2249 *
2250 *****************************************************************************/
2251
2252 static void update_device_table(struct protection_domain *domain)
2253 {
2254 struct iommu_dev_data *dev_data;
2255
2256 list_for_each_entry(dev_data, &domain->dev_list, list) {
2257 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2258 dev_data->iommu_v2);
2259 clone_aliases(dev_data->pdev);
2260 }
2261 }
2262
2263 static void update_domain(struct protection_domain *domain)
2264 {
2265 update_device_table(domain);
2266
2267 domain_flush_devices(domain);
2268 domain_flush_tlb_pde(domain);
2269 }
2270
2271 int __init amd_iommu_init_api(void)
2272 {
2273 int ret, err = 0;
2274
2275 ret = iova_cache_get();
2276 if (ret)
2277 return ret;
2278
2279 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2280 if (err)
2281 return err;
2282 #ifdef CONFIG_ARM_AMBA
2283 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2284 if (err)
2285 return err;
2286 #endif
2287 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2288 if (err)
2289 return err;
2290
2291 return 0;
2292 }
2293
2294 int __init amd_iommu_init_dma_ops(void)
2295 {
2296 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2297
2298 if (amd_iommu_unmap_flush)
2299 pr_info("IO/TLB flush on unmap enabled\n");
2300 else
2301 pr_info("Lazy IO/TLB flushing enabled\n");
2302
2303 return 0;
2304
2305 }
2306
2307 /*****************************************************************************
2308 *
2309 * The following functions belong to the exported interface of AMD IOMMU
2310 *
2311 * This interface allows access to lower level functions of the IOMMU
2312 * like protection domain handling and assignement of devices to domains
2313 * which is not possible with the dma_ops interface.
2314 *
2315 *****************************************************************************/
2316
2317 static void cleanup_domain(struct protection_domain *domain)
2318 {
2319 struct iommu_dev_data *entry;
2320 unsigned long flags;
2321
2322 spin_lock_irqsave(&domain->lock, flags);
2323
2324 while (!list_empty(&domain->dev_list)) {
2325 entry = list_first_entry(&domain->dev_list,
2326 struct iommu_dev_data, list);
2327 BUG_ON(!entry->domain);
2328 do_detach(entry);
2329 }
2330
2331 spin_unlock_irqrestore(&domain->lock, flags);
2332 }
2333
2334 static void protection_domain_free(struct protection_domain *domain)
2335 {
2336 if (!domain)
2337 return;
2338
2339 if (domain->id)
2340 domain_id_free(domain->id);
2341
2342 kfree(domain);
2343 }
2344
2345 static int protection_domain_init(struct protection_domain *domain)
2346 {
2347 spin_lock_init(&domain->lock);
2348 domain->id = domain_id_alloc();
2349 if (!domain->id)
2350 return -ENOMEM;
2351 INIT_LIST_HEAD(&domain->dev_list);
2352
2353 return 0;
2354 }
2355
2356 static struct protection_domain *protection_domain_alloc(void)
2357 {
2358 struct protection_domain *domain;
2359
2360 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2361 if (!domain)
2362 return NULL;
2363
2364 if (protection_domain_init(domain))
2365 goto out_err;
2366
2367 return domain;
2368
2369 out_err:
2370 kfree(domain);
2371
2372 return NULL;
2373 }
2374
2375 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2376 {
2377 struct protection_domain *pdomain;
2378
2379 switch (type) {
2380 case IOMMU_DOMAIN_UNMANAGED:
2381 pdomain = protection_domain_alloc();
2382 if (!pdomain)
2383 return NULL;
2384
2385 pdomain->mode = PAGE_MODE_3_LEVEL;
2386 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2387 if (!pdomain->pt_root) {
2388 protection_domain_free(pdomain);
2389 return NULL;
2390 }
2391
2392 pdomain->domain.geometry.aperture_start = 0;
2393 pdomain->domain.geometry.aperture_end = ~0ULL;
2394 pdomain->domain.geometry.force_aperture = true;
2395
2396 break;
2397 case IOMMU_DOMAIN_DMA:
2398 pdomain = dma_ops_domain_alloc();
2399 if (!pdomain) {
2400 pr_err("Failed to allocate\n");
2401 return NULL;
2402 }
2403 break;
2404 case IOMMU_DOMAIN_IDENTITY:
2405 pdomain = protection_domain_alloc();
2406 if (!pdomain)
2407 return NULL;
2408
2409 pdomain->mode = PAGE_MODE_NONE;
2410 break;
2411 default:
2412 return NULL;
2413 }
2414
2415 return &pdomain->domain;
2416 }
2417
2418 static void amd_iommu_domain_free(struct iommu_domain *dom)
2419 {
2420 struct protection_domain *domain;
2421
2422 domain = to_pdomain(dom);
2423
2424 if (domain->dev_cnt > 0)
2425 cleanup_domain(domain);
2426
2427 BUG_ON(domain->dev_cnt != 0);
2428
2429 if (!dom)
2430 return;
2431
2432 switch (dom->type) {
2433 case IOMMU_DOMAIN_DMA:
2434 /* Now release the domain */
2435 dma_ops_domain_free(domain);
2436 break;
2437 default:
2438 if (domain->mode != PAGE_MODE_NONE)
2439 free_pagetable(domain);
2440
2441 if (domain->flags & PD_IOMMUV2_MASK)
2442 free_gcr3_table(domain);
2443
2444 protection_domain_free(domain);
2445 break;
2446 }
2447 }
2448
2449 static void amd_iommu_detach_device(struct iommu_domain *dom,
2450 struct device *dev)
2451 {
2452 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2453 struct amd_iommu *iommu;
2454 int devid;
2455
2456 if (!check_device(dev))
2457 return;
2458
2459 devid = get_device_id(dev);
2460 if (devid < 0)
2461 return;
2462
2463 if (dev_data->domain != NULL)
2464 detach_device(dev);
2465
2466 iommu = amd_iommu_rlookup_table[devid];
2467 if (!iommu)
2468 return;
2469
2470 #ifdef CONFIG_IRQ_REMAP
2471 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2472 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2473 dev_data->use_vapic = 0;
2474 #endif
2475
2476 iommu_completion_wait(iommu);
2477 }
2478
2479 static int amd_iommu_attach_device(struct iommu_domain *dom,
2480 struct device *dev)
2481 {
2482 struct protection_domain *domain = to_pdomain(dom);
2483 struct iommu_dev_data *dev_data;
2484 struct amd_iommu *iommu;
2485 int ret;
2486
2487 if (!check_device(dev))
2488 return -EINVAL;
2489
2490 dev_data = dev->archdata.iommu;
2491 dev_data->defer_attach = false;
2492
2493 iommu = amd_iommu_rlookup_table[dev_data->devid];
2494 if (!iommu)
2495 return -EINVAL;
2496
2497 if (dev_data->domain)
2498 detach_device(dev);
2499
2500 ret = attach_device(dev, domain);
2501
2502 #ifdef CONFIG_IRQ_REMAP
2503 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2504 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2505 dev_data->use_vapic = 1;
2506 else
2507 dev_data->use_vapic = 0;
2508 }
2509 #endif
2510
2511 iommu_completion_wait(iommu);
2512
2513 return ret;
2514 }
2515
2516 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2517 phys_addr_t paddr, size_t page_size, int iommu_prot,
2518 gfp_t gfp)
2519 {
2520 struct protection_domain *domain = to_pdomain(dom);
2521 int prot = 0;
2522 int ret;
2523
2524 if (domain->mode == PAGE_MODE_NONE)
2525 return -EINVAL;
2526
2527 if (iommu_prot & IOMMU_READ)
2528 prot |= IOMMU_PROT_IR;
2529 if (iommu_prot & IOMMU_WRITE)
2530 prot |= IOMMU_PROT_IW;
2531
2532 ret = iommu_map_page(domain, iova, paddr, page_size, prot, gfp);
2533
2534 domain_flush_np_cache(domain, iova, page_size);
2535
2536 return ret;
2537 }
2538
2539 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2540 size_t page_size,
2541 struct iommu_iotlb_gather *gather)
2542 {
2543 struct protection_domain *domain = to_pdomain(dom);
2544
2545 if (domain->mode == PAGE_MODE_NONE)
2546 return 0;
2547
2548 return iommu_unmap_page(domain, iova, page_size);
2549 }
2550
2551 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2552 dma_addr_t iova)
2553 {
2554 struct protection_domain *domain = to_pdomain(dom);
2555 unsigned long offset_mask, pte_pgsize;
2556 u64 *pte, __pte;
2557
2558 if (domain->mode == PAGE_MODE_NONE)
2559 return iova;
2560
2561 pte = fetch_pte(domain, iova, &pte_pgsize);
2562
2563 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2564 return 0;
2565
2566 offset_mask = pte_pgsize - 1;
2567 __pte = __sme_clr(*pte & PM_ADDR_MASK);
2568
2569 return (__pte & ~offset_mask) | (iova & offset_mask);
2570 }
2571
2572 static bool amd_iommu_capable(enum iommu_cap cap)
2573 {
2574 switch (cap) {
2575 case IOMMU_CAP_CACHE_COHERENCY:
2576 return true;
2577 case IOMMU_CAP_INTR_REMAP:
2578 return (irq_remapping_enabled == 1);
2579 case IOMMU_CAP_NOEXEC:
2580 return false;
2581 default:
2582 break;
2583 }
2584
2585 return false;
2586 }
2587
2588 static void amd_iommu_get_resv_regions(struct device *dev,
2589 struct list_head *head)
2590 {
2591 struct iommu_resv_region *region;
2592 struct unity_map_entry *entry;
2593 int devid;
2594
2595 devid = get_device_id(dev);
2596 if (devid < 0)
2597 return;
2598
2599 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2600 int type, prot = 0;
2601 size_t length;
2602
2603 if (devid < entry->devid_start || devid > entry->devid_end)
2604 continue;
2605
2606 type = IOMMU_RESV_DIRECT;
2607 length = entry->address_end - entry->address_start;
2608 if (entry->prot & IOMMU_PROT_IR)
2609 prot |= IOMMU_READ;
2610 if (entry->prot & IOMMU_PROT_IW)
2611 prot |= IOMMU_WRITE;
2612 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2613 /* Exclusion range */
2614 type = IOMMU_RESV_RESERVED;
2615
2616 region = iommu_alloc_resv_region(entry->address_start,
2617 length, prot, type);
2618 if (!region) {
2619 dev_err(dev, "Out of memory allocating dm-regions\n");
2620 return;
2621 }
2622 list_add_tail(&region->list, head);
2623 }
2624
2625 region = iommu_alloc_resv_region(MSI_RANGE_START,
2626 MSI_RANGE_END - MSI_RANGE_START + 1,
2627 0, IOMMU_RESV_MSI);
2628 if (!region)
2629 return;
2630 list_add_tail(&region->list, head);
2631
2632 region = iommu_alloc_resv_region(HT_RANGE_START,
2633 HT_RANGE_END - HT_RANGE_START + 1,
2634 0, IOMMU_RESV_RESERVED);
2635 if (!region)
2636 return;
2637 list_add_tail(&region->list, head);
2638 }
2639
2640 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2641 struct device *dev)
2642 {
2643 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2644 return dev_data->defer_attach;
2645 }
2646
2647 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2648 {
2649 struct protection_domain *dom = to_pdomain(domain);
2650 unsigned long flags;
2651
2652 spin_lock_irqsave(&dom->lock, flags);
2653 domain_flush_tlb_pde(dom);
2654 domain_flush_complete(dom);
2655 spin_unlock_irqrestore(&dom->lock, flags);
2656 }
2657
2658 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2659 struct iommu_iotlb_gather *gather)
2660 {
2661 amd_iommu_flush_iotlb_all(domain);
2662 }
2663
2664 const struct iommu_ops amd_iommu_ops = {
2665 .capable = amd_iommu_capable,
2666 .domain_alloc = amd_iommu_domain_alloc,
2667 .domain_free = amd_iommu_domain_free,
2668 .attach_dev = amd_iommu_attach_device,
2669 .detach_dev = amd_iommu_detach_device,
2670 .map = amd_iommu_map,
2671 .unmap = amd_iommu_unmap,
2672 .iova_to_phys = amd_iommu_iova_to_phys,
2673 .add_device = amd_iommu_add_device,
2674 .remove_device = amd_iommu_remove_device,
2675 .device_group = amd_iommu_device_group,
2676 .domain_get_attr = amd_iommu_domain_get_attr,
2677 .get_resv_regions = amd_iommu_get_resv_regions,
2678 .put_resv_regions = generic_iommu_put_resv_regions,
2679 .is_attach_deferred = amd_iommu_is_attach_deferred,
2680 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2681 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2682 .iotlb_sync = amd_iommu_iotlb_sync,
2683 };
2684
2685 /*****************************************************************************
2686 *
2687 * The next functions do a basic initialization of IOMMU for pass through
2688 * mode
2689 *
2690 * In passthrough mode the IOMMU is initialized and enabled but not used for
2691 * DMA-API translation.
2692 *
2693 *****************************************************************************/
2694
2695 /* IOMMUv2 specific functions */
2696 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2697 {
2698 return atomic_notifier_chain_register(&ppr_notifier, nb);
2699 }
2700 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2701
2702 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2703 {
2704 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2705 }
2706 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2707
2708 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2709 {
2710 struct protection_domain *domain = to_pdomain(dom);
2711 unsigned long flags;
2712
2713 spin_lock_irqsave(&domain->lock, flags);
2714
2715 /* Update data structure */
2716 domain->mode = PAGE_MODE_NONE;
2717
2718 /* Make changes visible to IOMMUs */
2719 update_domain(domain);
2720
2721 /* Page-table is not visible to IOMMU anymore, so free it */
2722 free_pagetable(domain);
2723
2724 spin_unlock_irqrestore(&domain->lock, flags);
2725 }
2726 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2727
2728 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2729 {
2730 struct protection_domain *domain = to_pdomain(dom);
2731 unsigned long flags;
2732 int levels, ret;
2733
2734 if (pasids <= 0 || pasids > (PASID_MASK + 1))
2735 return -EINVAL;
2736
2737 /* Number of GCR3 table levels required */
2738 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2739 levels += 1;
2740
2741 if (levels > amd_iommu_max_glx_val)
2742 return -EINVAL;
2743
2744 spin_lock_irqsave(&domain->lock, flags);
2745
2746 /*
2747 * Save us all sanity checks whether devices already in the
2748 * domain support IOMMUv2. Just force that the domain has no
2749 * devices attached when it is switched into IOMMUv2 mode.
2750 */
2751 ret = -EBUSY;
2752 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2753 goto out;
2754
2755 ret = -ENOMEM;
2756 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2757 if (domain->gcr3_tbl == NULL)
2758 goto out;
2759
2760 domain->glx = levels;
2761 domain->flags |= PD_IOMMUV2_MASK;
2762
2763 update_domain(domain);
2764
2765 ret = 0;
2766
2767 out:
2768 spin_unlock_irqrestore(&domain->lock, flags);
2769
2770 return ret;
2771 }
2772 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2773
2774 static int __flush_pasid(struct protection_domain *domain, int pasid,
2775 u64 address, bool size)
2776 {
2777 struct iommu_dev_data *dev_data;
2778 struct iommu_cmd cmd;
2779 int i, ret;
2780
2781 if (!(domain->flags & PD_IOMMUV2_MASK))
2782 return -EINVAL;
2783
2784 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2785
2786 /*
2787 * IOMMU TLB needs to be flushed before Device TLB to
2788 * prevent device TLB refill from IOMMU TLB
2789 */
2790 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2791 if (domain->dev_iommu[i] == 0)
2792 continue;
2793
2794 ret = iommu_queue_command(amd_iommus[i], &cmd);
2795 if (ret != 0)
2796 goto out;
2797 }
2798
2799 /* Wait until IOMMU TLB flushes are complete */
2800 domain_flush_complete(domain);
2801
2802 /* Now flush device TLBs */
2803 list_for_each_entry(dev_data, &domain->dev_list, list) {
2804 struct amd_iommu *iommu;
2805 int qdep;
2806
2807 /*
2808 There might be non-IOMMUv2 capable devices in an IOMMUv2
2809 * domain.
2810 */
2811 if (!dev_data->ats.enabled)
2812 continue;
2813
2814 qdep = dev_data->ats.qdep;
2815 iommu = amd_iommu_rlookup_table[dev_data->devid];
2816
2817 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2818 qdep, address, size);
2819
2820 ret = iommu_queue_command(iommu, &cmd);
2821 if (ret != 0)
2822 goto out;
2823 }
2824
2825 /* Wait until all device TLBs are flushed */
2826 domain_flush_complete(domain);
2827
2828 ret = 0;
2829
2830 out:
2831
2832 return ret;
2833 }
2834
2835 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
2836 u64 address)
2837 {
2838 return __flush_pasid(domain, pasid, address, false);
2839 }
2840
2841 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
2842 u64 address)
2843 {
2844 struct protection_domain *domain = to_pdomain(dom);
2845 unsigned long flags;
2846 int ret;
2847
2848 spin_lock_irqsave(&domain->lock, flags);
2849 ret = __amd_iommu_flush_page(domain, pasid, address);
2850 spin_unlock_irqrestore(&domain->lock, flags);
2851
2852 return ret;
2853 }
2854 EXPORT_SYMBOL(amd_iommu_flush_page);
2855
2856 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
2857 {
2858 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2859 true);
2860 }
2861
2862 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
2863 {
2864 struct protection_domain *domain = to_pdomain(dom);
2865 unsigned long flags;
2866 int ret;
2867
2868 spin_lock_irqsave(&domain->lock, flags);
2869 ret = __amd_iommu_flush_tlb(domain, pasid);
2870 spin_unlock_irqrestore(&domain->lock, flags);
2871
2872 return ret;
2873 }
2874 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2875
2876 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
2877 {
2878 int index;
2879 u64 *pte;
2880
2881 while (true) {
2882
2883 index = (pasid >> (9 * level)) & 0x1ff;
2884 pte = &root[index];
2885
2886 if (level == 0)
2887 break;
2888
2889 if (!(*pte & GCR3_VALID)) {
2890 if (!alloc)
2891 return NULL;
2892
2893 root = (void *)get_zeroed_page(GFP_ATOMIC);
2894 if (root == NULL)
2895 return NULL;
2896
2897 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2898 }
2899
2900 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2901
2902 level -= 1;
2903 }
2904
2905 return pte;
2906 }
2907
2908 static int __set_gcr3(struct protection_domain *domain, int pasid,
2909 unsigned long cr3)
2910 {
2911 u64 *pte;
2912
2913 if (domain->mode != PAGE_MODE_NONE)
2914 return -EINVAL;
2915
2916 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2917 if (pte == NULL)
2918 return -ENOMEM;
2919
2920 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2921
2922 return __amd_iommu_flush_tlb(domain, pasid);
2923 }
2924
2925 static int __clear_gcr3(struct protection_domain *domain, int pasid)
2926 {
2927 u64 *pte;
2928
2929 if (domain->mode != PAGE_MODE_NONE)
2930 return -EINVAL;
2931
2932 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2933 if (pte == NULL)
2934 return 0;
2935
2936 *pte = 0;
2937
2938 return __amd_iommu_flush_tlb(domain, pasid);
2939 }
2940
2941 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
2942 unsigned long cr3)
2943 {
2944 struct protection_domain *domain = to_pdomain(dom);
2945 unsigned long flags;
2946 int ret;
2947
2948 spin_lock_irqsave(&domain->lock, flags);
2949 ret = __set_gcr3(domain, pasid, cr3);
2950 spin_unlock_irqrestore(&domain->lock, flags);
2951
2952 return ret;
2953 }
2954 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2955
2956 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
2957 {
2958 struct protection_domain *domain = to_pdomain(dom);
2959 unsigned long flags;
2960 int ret;
2961
2962 spin_lock_irqsave(&domain->lock, flags);
2963 ret = __clear_gcr3(domain, pasid);
2964 spin_unlock_irqrestore(&domain->lock, flags);
2965
2966 return ret;
2967 }
2968 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2969
2970 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
2971 int status, int tag)
2972 {
2973 struct iommu_dev_data *dev_data;
2974 struct amd_iommu *iommu;
2975 struct iommu_cmd cmd;
2976
2977 dev_data = get_dev_data(&pdev->dev);
2978 iommu = amd_iommu_rlookup_table[dev_data->devid];
2979
2980 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2981 tag, dev_data->pri_tlp);
2982
2983 return iommu_queue_command(iommu, &cmd);
2984 }
2985 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2986
2987 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
2988 {
2989 struct protection_domain *pdomain;
2990 struct iommu_domain *io_domain;
2991 struct device *dev = &pdev->dev;
2992
2993 if (!check_device(dev))
2994 return NULL;
2995
2996 pdomain = get_dev_data(dev)->domain;
2997 if (pdomain == NULL && get_dev_data(dev)->defer_attach) {
2998 get_dev_data(dev)->defer_attach = false;
2999 io_domain = iommu_get_domain_for_dev(dev);
3000 pdomain = to_pdomain(io_domain);
3001 attach_device(dev, pdomain);
3002 }
3003 if (pdomain == NULL)
3004 return NULL;
3005
3006 if (!dma_ops_domain(pdomain))
3007 return NULL;
3008
3009 /* Only return IOMMUv2 domains */
3010 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3011 return NULL;
3012
3013 return &pdomain->domain;
3014 }
3015 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3016
3017 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3018 {
3019 struct iommu_dev_data *dev_data;
3020
3021 if (!amd_iommu_v2_supported())
3022 return;
3023
3024 dev_data = get_dev_data(&pdev->dev);
3025 dev_data->errata |= (1 << erratum);
3026 }
3027 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3028
3029 int amd_iommu_device_info(struct pci_dev *pdev,
3030 struct amd_iommu_device_info *info)
3031 {
3032 int max_pasids;
3033 int pos;
3034
3035 if (pdev == NULL || info == NULL)
3036 return -EINVAL;
3037
3038 if (!amd_iommu_v2_supported())
3039 return -EINVAL;
3040
3041 memset(info, 0, sizeof(*info));
3042
3043 if (!pci_ats_disabled()) {
3044 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3045 if (pos)
3046 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3047 }
3048
3049 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3050 if (pos)
3051 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3052
3053 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3054 if (pos) {
3055 int features;
3056
3057 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3058 max_pasids = min(max_pasids, (1 << 20));
3059
3060 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3061 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3062
3063 features = pci_pasid_features(pdev);
3064 if (features & PCI_PASID_CAP_EXEC)
3065 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3066 if (features & PCI_PASID_CAP_PRIV)
3067 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3068 }
3069
3070 return 0;
3071 }
3072 EXPORT_SYMBOL(amd_iommu_device_info);
3073
3074 #ifdef CONFIG_IRQ_REMAP
3075
3076 /*****************************************************************************
3077 *
3078 * Interrupt Remapping Implementation
3079 *
3080 *****************************************************************************/
3081
3082 static struct irq_chip amd_ir_chip;
3083 static DEFINE_SPINLOCK(iommu_table_lock);
3084
3085 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3086 {
3087 u64 dte;
3088
3089 dte = amd_iommu_dev_table[devid].data[2];
3090 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3091 dte |= iommu_virt_to_phys(table->table);
3092 dte |= DTE_IRQ_REMAP_INTCTL;
3093 dte |= DTE_IRQ_TABLE_LEN;
3094 dte |= DTE_IRQ_REMAP_ENABLE;
3095
3096 amd_iommu_dev_table[devid].data[2] = dte;
3097 }
3098
3099 static struct irq_remap_table *get_irq_table(u16 devid)
3100 {
3101 struct irq_remap_table *table;
3102
3103 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3104 "%s: no iommu for devid %x\n", __func__, devid))
3105 return NULL;
3106
3107 table = irq_lookup_table[devid];
3108 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3109 return NULL;
3110
3111 return table;
3112 }
3113
3114 static struct irq_remap_table *__alloc_irq_table(void)
3115 {
3116 struct irq_remap_table *table;
3117
3118 table = kzalloc(sizeof(*table), GFP_KERNEL);
3119 if (!table)
3120 return NULL;
3121
3122 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3123 if (!table->table) {
3124 kfree(table);
3125 return NULL;
3126 }
3127 raw_spin_lock_init(&table->lock);
3128
3129 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3130 memset(table->table, 0,
3131 MAX_IRQS_PER_TABLE * sizeof(u32));
3132 else
3133 memset(table->table, 0,
3134 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3135 return table;
3136 }
3137
3138 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3139 struct irq_remap_table *table)
3140 {
3141 irq_lookup_table[devid] = table;
3142 set_dte_irq_entry(devid, table);
3143 iommu_flush_dte(iommu, devid);
3144 }
3145
3146 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
3147 void *data)
3148 {
3149 struct irq_remap_table *table = data;
3150
3151 irq_lookup_table[alias] = table;
3152 set_dte_irq_entry(alias, table);
3153
3154 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
3155
3156 return 0;
3157 }
3158
3159 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
3160 {
3161 struct irq_remap_table *table = NULL;
3162 struct irq_remap_table *new_table = NULL;
3163 struct amd_iommu *iommu;
3164 unsigned long flags;
3165 u16 alias;
3166
3167 spin_lock_irqsave(&iommu_table_lock, flags);
3168
3169 iommu = amd_iommu_rlookup_table[devid];
3170 if (!iommu)
3171 goto out_unlock;
3172
3173 table = irq_lookup_table[devid];
3174 if (table)
3175 goto out_unlock;
3176
3177 alias = amd_iommu_alias_table[devid];
3178 table = irq_lookup_table[alias];
3179 if (table) {
3180 set_remap_table_entry(iommu, devid, table);
3181 goto out_wait;
3182 }
3183 spin_unlock_irqrestore(&iommu_table_lock, flags);
3184
3185 /* Nothing there yet, allocate new irq remapping table */
3186 new_table = __alloc_irq_table();
3187 if (!new_table)
3188 return NULL;
3189
3190 spin_lock_irqsave(&iommu_table_lock, flags);
3191
3192 table = irq_lookup_table[devid];
3193 if (table)
3194 goto out_unlock;
3195
3196 table = irq_lookup_table[alias];
3197 if (table) {
3198 set_remap_table_entry(iommu, devid, table);
3199 goto out_wait;
3200 }
3201
3202 table = new_table;
3203 new_table = NULL;
3204
3205 if (pdev)
3206 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
3207 table);
3208 else
3209 set_remap_table_entry(iommu, devid, table);
3210
3211 if (devid != alias)
3212 set_remap_table_entry(iommu, alias, table);
3213
3214 out_wait:
3215 iommu_completion_wait(iommu);
3216
3217 out_unlock:
3218 spin_unlock_irqrestore(&iommu_table_lock, flags);
3219
3220 if (new_table) {
3221 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3222 kfree(new_table);
3223 }
3224 return table;
3225 }
3226
3227 static int alloc_irq_index(u16 devid, int count, bool align,
3228 struct pci_dev *pdev)
3229 {
3230 struct irq_remap_table *table;
3231 int index, c, alignment = 1;
3232 unsigned long flags;
3233 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3234
3235 if (!iommu)
3236 return -ENODEV;
3237
3238 table = alloc_irq_table(devid, pdev);
3239 if (!table)
3240 return -ENODEV;
3241
3242 if (align)
3243 alignment = roundup_pow_of_two(count);
3244
3245 raw_spin_lock_irqsave(&table->lock, flags);
3246
3247 /* Scan table for free entries */
3248 for (index = ALIGN(table->min_index, alignment), c = 0;
3249 index < MAX_IRQS_PER_TABLE;) {
3250 if (!iommu->irte_ops->is_allocated(table, index)) {
3251 c += 1;
3252 } else {
3253 c = 0;
3254 index = ALIGN(index + 1, alignment);
3255 continue;
3256 }
3257
3258 if (c == count) {
3259 for (; c != 0; --c)
3260 iommu->irte_ops->set_allocated(table, index - c + 1);
3261
3262 index -= count - 1;
3263 goto out;
3264 }
3265
3266 index++;
3267 }
3268
3269 index = -ENOSPC;
3270
3271 out:
3272 raw_spin_unlock_irqrestore(&table->lock, flags);
3273
3274 return index;
3275 }
3276
3277 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3278 struct amd_ir_data *data)
3279 {
3280 struct irq_remap_table *table;
3281 struct amd_iommu *iommu;
3282 unsigned long flags;
3283 struct irte_ga *entry;
3284
3285 iommu = amd_iommu_rlookup_table[devid];
3286 if (iommu == NULL)
3287 return -EINVAL;
3288
3289 table = get_irq_table(devid);
3290 if (!table)
3291 return -ENOMEM;
3292
3293 raw_spin_lock_irqsave(&table->lock, flags);
3294
3295 entry = (struct irte_ga *)table->table;
3296 entry = &entry[index];
3297 entry->lo.fields_remap.valid = 0;
3298 entry->hi.val = irte->hi.val;
3299 entry->lo.val = irte->lo.val;
3300 entry->lo.fields_remap.valid = 1;
3301 if (data)
3302 data->ref = entry;
3303
3304 raw_spin_unlock_irqrestore(&table->lock, flags);
3305
3306 iommu_flush_irt(iommu, devid);
3307 iommu_completion_wait(iommu);
3308
3309 return 0;
3310 }
3311
3312 static int modify_irte(u16 devid, int index, union irte *irte)
3313 {
3314 struct irq_remap_table *table;
3315 struct amd_iommu *iommu;
3316 unsigned long flags;
3317
3318 iommu = amd_iommu_rlookup_table[devid];
3319 if (iommu == NULL)
3320 return -EINVAL;
3321
3322 table = get_irq_table(devid);
3323 if (!table)
3324 return -ENOMEM;
3325
3326 raw_spin_lock_irqsave(&table->lock, flags);
3327 table->table[index] = irte->val;
3328 raw_spin_unlock_irqrestore(&table->lock, flags);
3329
3330 iommu_flush_irt(iommu, devid);
3331 iommu_completion_wait(iommu);
3332
3333 return 0;
3334 }
3335
3336 static void free_irte(u16 devid, int index)
3337 {
3338 struct irq_remap_table *table;
3339 struct amd_iommu *iommu;
3340 unsigned long flags;
3341
3342 iommu = amd_iommu_rlookup_table[devid];
3343 if (iommu == NULL)
3344 return;
3345
3346 table = get_irq_table(devid);
3347 if (!table)
3348 return;
3349
3350 raw_spin_lock_irqsave(&table->lock, flags);
3351 iommu->irte_ops->clear_allocated(table, index);
3352 raw_spin_unlock_irqrestore(&table->lock, flags);
3353
3354 iommu_flush_irt(iommu, devid);
3355 iommu_completion_wait(iommu);
3356 }
3357
3358 static void irte_prepare(void *entry,
3359 u32 delivery_mode, u32 dest_mode,
3360 u8 vector, u32 dest_apicid, int devid)
3361 {
3362 union irte *irte = (union irte *) entry;
3363
3364 irte->val = 0;
3365 irte->fields.vector = vector;
3366 irte->fields.int_type = delivery_mode;
3367 irte->fields.destination = dest_apicid;
3368 irte->fields.dm = dest_mode;
3369 irte->fields.valid = 1;
3370 }
3371
3372 static void irte_ga_prepare(void *entry,
3373 u32 delivery_mode, u32 dest_mode,
3374 u8 vector, u32 dest_apicid, int devid)
3375 {
3376 struct irte_ga *irte = (struct irte_ga *) entry;
3377
3378 irte->lo.val = 0;
3379 irte->hi.val = 0;
3380 irte->lo.fields_remap.int_type = delivery_mode;
3381 irte->lo.fields_remap.dm = dest_mode;
3382 irte->hi.fields.vector = vector;
3383 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3384 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3385 irte->lo.fields_remap.valid = 1;
3386 }
3387
3388 static void irte_activate(void *entry, u16 devid, u16 index)
3389 {
3390 union irte *irte = (union irte *) entry;
3391
3392 irte->fields.valid = 1;
3393 modify_irte(devid, index, irte);
3394 }
3395
3396 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3397 {
3398 struct irte_ga *irte = (struct irte_ga *) entry;
3399
3400 irte->lo.fields_remap.valid = 1;
3401 modify_irte_ga(devid, index, irte, NULL);
3402 }
3403
3404 static void irte_deactivate(void *entry, u16 devid, u16 index)
3405 {
3406 union irte *irte = (union irte *) entry;
3407
3408 irte->fields.valid = 0;
3409 modify_irte(devid, index, irte);
3410 }
3411
3412 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3413 {
3414 struct irte_ga *irte = (struct irte_ga *) entry;
3415
3416 irte->lo.fields_remap.valid = 0;
3417 modify_irte_ga(devid, index, irte, NULL);
3418 }
3419
3420 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3421 u8 vector, u32 dest_apicid)
3422 {
3423 union irte *irte = (union irte *) entry;
3424
3425 irte->fields.vector = vector;
3426 irte->fields.destination = dest_apicid;
3427 modify_irte(devid, index, irte);
3428 }
3429
3430 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3431 u8 vector, u32 dest_apicid)
3432 {
3433 struct irte_ga *irte = (struct irte_ga *) entry;
3434
3435 if (!irte->lo.fields_remap.guest_mode) {
3436 irte->hi.fields.vector = vector;
3437 irte->lo.fields_remap.destination =
3438 APICID_TO_IRTE_DEST_LO(dest_apicid);
3439 irte->hi.fields.destination =
3440 APICID_TO_IRTE_DEST_HI(dest_apicid);
3441 modify_irte_ga(devid, index, irte, NULL);
3442 }
3443 }
3444
3445 #define IRTE_ALLOCATED (~1U)
3446 static void irte_set_allocated(struct irq_remap_table *table, int index)
3447 {
3448 table->table[index] = IRTE_ALLOCATED;
3449 }
3450
3451 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3452 {
3453 struct irte_ga *ptr = (struct irte_ga *)table->table;
3454 struct irte_ga *irte = &ptr[index];
3455
3456 memset(&irte->lo.val, 0, sizeof(u64));
3457 memset(&irte->hi.val, 0, sizeof(u64));
3458 irte->hi.fields.vector = 0xff;
3459 }
3460
3461 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3462 {
3463 union irte *ptr = (union irte *)table->table;
3464 union irte *irte = &ptr[index];
3465
3466 return irte->val != 0;
3467 }
3468
3469 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3470 {
3471 struct irte_ga *ptr = (struct irte_ga *)table->table;
3472 struct irte_ga *irte = &ptr[index];
3473
3474 return irte->hi.fields.vector != 0;
3475 }
3476
3477 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3478 {
3479 table->table[index] = 0;
3480 }
3481
3482 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3483 {
3484 struct irte_ga *ptr = (struct irte_ga *)table->table;
3485 struct irte_ga *irte = &ptr[index];
3486
3487 memset(&irte->lo.val, 0, sizeof(u64));
3488 memset(&irte->hi.val, 0, sizeof(u64));
3489 }
3490
3491 static int get_devid(struct irq_alloc_info *info)
3492 {
3493 int devid = -1;
3494
3495 switch (info->type) {
3496 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3497 devid = get_ioapic_devid(info->ioapic_id);
3498 break;
3499 case X86_IRQ_ALLOC_TYPE_HPET:
3500 devid = get_hpet_devid(info->hpet_id);
3501 break;
3502 case X86_IRQ_ALLOC_TYPE_MSI:
3503 case X86_IRQ_ALLOC_TYPE_MSIX:
3504 devid = get_device_id(&info->msi_dev->dev);
3505 break;
3506 default:
3507 BUG_ON(1);
3508 break;
3509 }
3510
3511 return devid;
3512 }
3513
3514 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3515 {
3516 struct amd_iommu *iommu;
3517 int devid;
3518
3519 if (!info)
3520 return NULL;
3521
3522 devid = get_devid(info);
3523 if (devid >= 0) {
3524 iommu = amd_iommu_rlookup_table[devid];
3525 if (iommu)
3526 return iommu->ir_domain;
3527 }
3528
3529 return NULL;
3530 }
3531
3532 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3533 {
3534 struct amd_iommu *iommu;
3535 int devid;
3536
3537 if (!info)
3538 return NULL;
3539
3540 switch (info->type) {
3541 case X86_IRQ_ALLOC_TYPE_MSI:
3542 case X86_IRQ_ALLOC_TYPE_MSIX:
3543 devid = get_device_id(&info->msi_dev->dev);
3544 if (devid < 0)
3545 return NULL;
3546
3547 iommu = amd_iommu_rlookup_table[devid];
3548 if (iommu)
3549 return iommu->msi_domain;
3550 break;
3551 default:
3552 break;
3553 }
3554
3555 return NULL;
3556 }
3557
3558 struct irq_remap_ops amd_iommu_irq_ops = {
3559 .prepare = amd_iommu_prepare,
3560 .enable = amd_iommu_enable,
3561 .disable = amd_iommu_disable,
3562 .reenable = amd_iommu_reenable,
3563 .enable_faulting = amd_iommu_enable_faulting,
3564 .get_ir_irq_domain = get_ir_irq_domain,
3565 .get_irq_domain = get_irq_domain,
3566 };
3567
3568 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3569 struct irq_cfg *irq_cfg,
3570 struct irq_alloc_info *info,
3571 int devid, int index, int sub_handle)
3572 {
3573 struct irq_2_irte *irte_info = &data->irq_2_irte;
3574 struct msi_msg *msg = &data->msi_entry;
3575 struct IO_APIC_route_entry *entry;
3576 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3577
3578 if (!iommu)
3579 return;
3580
3581 data->irq_2_irte.devid = devid;
3582 data->irq_2_irte.index = index + sub_handle;
3583 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
3584 apic->irq_dest_mode, irq_cfg->vector,
3585 irq_cfg->dest_apicid, devid);
3586
3587 switch (info->type) {
3588 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3589 /* Setup IOAPIC entry */
3590 entry = info->ioapic_entry;
3591 info->ioapic_entry = NULL;
3592 memset(entry, 0, sizeof(*entry));
3593 entry->vector = index;
3594 entry->mask = 0;
3595 entry->trigger = info->ioapic_trigger;
3596 entry->polarity = info->ioapic_polarity;
3597 /* Mask level triggered irqs. */
3598 if (info->ioapic_trigger)
3599 entry->mask = 1;
3600 break;
3601
3602 case X86_IRQ_ALLOC_TYPE_HPET:
3603 case X86_IRQ_ALLOC_TYPE_MSI:
3604 case X86_IRQ_ALLOC_TYPE_MSIX:
3605 msg->address_hi = MSI_ADDR_BASE_HI;
3606 msg->address_lo = MSI_ADDR_BASE_LO;
3607 msg->data = irte_info->index;
3608 break;
3609
3610 default:
3611 BUG_ON(1);
3612 break;
3613 }
3614 }
3615
3616 struct amd_irte_ops irte_32_ops = {
3617 .prepare = irte_prepare,
3618 .activate = irte_activate,
3619 .deactivate = irte_deactivate,
3620 .set_affinity = irte_set_affinity,
3621 .set_allocated = irte_set_allocated,
3622 .is_allocated = irte_is_allocated,
3623 .clear_allocated = irte_clear_allocated,
3624 };
3625
3626 struct amd_irte_ops irte_128_ops = {
3627 .prepare = irte_ga_prepare,
3628 .activate = irte_ga_activate,
3629 .deactivate = irte_ga_deactivate,
3630 .set_affinity = irte_ga_set_affinity,
3631 .set_allocated = irte_ga_set_allocated,
3632 .is_allocated = irte_ga_is_allocated,
3633 .clear_allocated = irte_ga_clear_allocated,
3634 };
3635
3636 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3637 unsigned int nr_irqs, void *arg)
3638 {
3639 struct irq_alloc_info *info = arg;
3640 struct irq_data *irq_data;
3641 struct amd_ir_data *data = NULL;
3642 struct irq_cfg *cfg;
3643 int i, ret, devid;
3644 int index;
3645
3646 if (!info)
3647 return -EINVAL;
3648 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3649 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3650 return -EINVAL;
3651
3652 /*
3653 * With IRQ remapping enabled, don't need contiguous CPU vectors
3654 * to support multiple MSI interrupts.
3655 */
3656 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3657 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3658
3659 devid = get_devid(info);
3660 if (devid < 0)
3661 return -EINVAL;
3662
3663 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3664 if (ret < 0)
3665 return ret;
3666
3667 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3668 struct irq_remap_table *table;
3669 struct amd_iommu *iommu;
3670
3671 table = alloc_irq_table(devid, NULL);
3672 if (table) {
3673 if (!table->min_index) {
3674 /*
3675 * Keep the first 32 indexes free for IOAPIC
3676 * interrupts.
3677 */
3678 table->min_index = 32;
3679 iommu = amd_iommu_rlookup_table[devid];
3680 for (i = 0; i < 32; ++i)
3681 iommu->irte_ops->set_allocated(table, i);
3682 }
3683 WARN_ON(table->min_index != 32);
3684 index = info->ioapic_pin;
3685 } else {
3686 index = -ENOMEM;
3687 }
3688 } else if (info->type == X86_IRQ_ALLOC_TYPE_MSI ||
3689 info->type == X86_IRQ_ALLOC_TYPE_MSIX) {
3690 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
3691
3692 index = alloc_irq_index(devid, nr_irqs, align, info->msi_dev);
3693 } else {
3694 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3695 }
3696
3697 if (index < 0) {
3698 pr_warn("Failed to allocate IRTE\n");
3699 ret = index;
3700 goto out_free_parent;
3701 }
3702
3703 for (i = 0; i < nr_irqs; i++) {
3704 irq_data = irq_domain_get_irq_data(domain, virq + i);
3705 cfg = irqd_cfg(irq_data);
3706 if (!irq_data || !cfg) {
3707 ret = -EINVAL;
3708 goto out_free_data;
3709 }
3710
3711 ret = -ENOMEM;
3712 data = kzalloc(sizeof(*data), GFP_KERNEL);
3713 if (!data)
3714 goto out_free_data;
3715
3716 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3717 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3718 else
3719 data->entry = kzalloc(sizeof(struct irte_ga),
3720 GFP_KERNEL);
3721 if (!data->entry) {
3722 kfree(data);
3723 goto out_free_data;
3724 }
3725
3726 irq_data->hwirq = (devid << 16) + i;
3727 irq_data->chip_data = data;
3728 irq_data->chip = &amd_ir_chip;
3729 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3730 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3731 }
3732
3733 return 0;
3734
3735 out_free_data:
3736 for (i--; i >= 0; i--) {
3737 irq_data = irq_domain_get_irq_data(domain, virq + i);
3738 if (irq_data)
3739 kfree(irq_data->chip_data);
3740 }
3741 for (i = 0; i < nr_irqs; i++)
3742 free_irte(devid, index + i);
3743 out_free_parent:
3744 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3745 return ret;
3746 }
3747
3748 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3749 unsigned int nr_irqs)
3750 {
3751 struct irq_2_irte *irte_info;
3752 struct irq_data *irq_data;
3753 struct amd_ir_data *data;
3754 int i;
3755
3756 for (i = 0; i < nr_irqs; i++) {
3757 irq_data = irq_domain_get_irq_data(domain, virq + i);
3758 if (irq_data && irq_data->chip_data) {
3759 data = irq_data->chip_data;
3760 irte_info = &data->irq_2_irte;
3761 free_irte(irte_info->devid, irte_info->index);
3762 kfree(data->entry);
3763 kfree(data);
3764 }
3765 }
3766 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3767 }
3768
3769 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3770 struct amd_ir_data *ir_data,
3771 struct irq_2_irte *irte_info,
3772 struct irq_cfg *cfg);
3773
3774 static int irq_remapping_activate(struct irq_domain *domain,
3775 struct irq_data *irq_data, bool reserve)
3776 {
3777 struct amd_ir_data *data = irq_data->chip_data;
3778 struct irq_2_irte *irte_info = &data->irq_2_irte;
3779 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3780 struct irq_cfg *cfg = irqd_cfg(irq_data);
3781
3782 if (!iommu)
3783 return 0;
3784
3785 iommu->irte_ops->activate(data->entry, irte_info->devid,
3786 irte_info->index);
3787 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3788 return 0;
3789 }
3790
3791 static void irq_remapping_deactivate(struct irq_domain *domain,
3792 struct irq_data *irq_data)
3793 {
3794 struct amd_ir_data *data = irq_data->chip_data;
3795 struct irq_2_irte *irte_info = &data->irq_2_irte;
3796 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3797
3798 if (iommu)
3799 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3800 irte_info->index);
3801 }
3802
3803 static const struct irq_domain_ops amd_ir_domain_ops = {
3804 .alloc = irq_remapping_alloc,
3805 .free = irq_remapping_free,
3806 .activate = irq_remapping_activate,
3807 .deactivate = irq_remapping_deactivate,
3808 };
3809
3810 int amd_iommu_activate_guest_mode(void *data)
3811 {
3812 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3813 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3814
3815 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3816 !entry || entry->lo.fields_vapic.guest_mode)
3817 return 0;
3818
3819 entry->lo.val = 0;
3820 entry->hi.val = 0;
3821
3822 entry->lo.fields_vapic.guest_mode = 1;
3823 entry->lo.fields_vapic.ga_log_intr = 1;
3824 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3825 entry->hi.fields.vector = ir_data->ga_vector;
3826 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3827
3828 return modify_irte_ga(ir_data->irq_2_irte.devid,
3829 ir_data->irq_2_irte.index, entry, ir_data);
3830 }
3831 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3832
3833 int amd_iommu_deactivate_guest_mode(void *data)
3834 {
3835 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3836 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3837 struct irq_cfg *cfg = ir_data->cfg;
3838
3839 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3840 !entry || !entry->lo.fields_vapic.guest_mode)
3841 return 0;
3842
3843 entry->lo.val = 0;
3844 entry->hi.val = 0;
3845
3846 entry->lo.fields_remap.dm = apic->irq_dest_mode;
3847 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
3848 entry->hi.fields.vector = cfg->vector;
3849 entry->lo.fields_remap.destination =
3850 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3851 entry->hi.fields.destination =
3852 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3853
3854 return modify_irte_ga(ir_data->irq_2_irte.devid,
3855 ir_data->irq_2_irte.index, entry, ir_data);
3856 }
3857 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3858
3859 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3860 {
3861 int ret;
3862 struct amd_iommu *iommu;
3863 struct amd_iommu_pi_data *pi_data = vcpu_info;
3864 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3865 struct amd_ir_data *ir_data = data->chip_data;
3866 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3867 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3868
3869 /* Note:
3870 * This device has never been set up for guest mode.
3871 * we should not modify the IRTE
3872 */
3873 if (!dev_data || !dev_data->use_vapic)
3874 return 0;
3875
3876 ir_data->cfg = irqd_cfg(data);
3877 pi_data->ir_data = ir_data;
3878
3879 /* Note:
3880 * SVM tries to set up for VAPIC mode, but we are in
3881 * legacy mode. So, we force legacy mode instead.
3882 */
3883 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3884 pr_debug("%s: Fall back to using intr legacy remap\n",
3885 __func__);
3886 pi_data->is_guest_mode = false;
3887 }
3888
3889 iommu = amd_iommu_rlookup_table[irte_info->devid];
3890 if (iommu == NULL)
3891 return -EINVAL;
3892
3893 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3894 if (pi_data->is_guest_mode) {
3895 ir_data->ga_root_ptr = (pi_data->base >> 12);
3896 ir_data->ga_vector = vcpu_pi_info->vector;
3897 ir_data->ga_tag = pi_data->ga_tag;
3898 ret = amd_iommu_activate_guest_mode(ir_data);
3899 if (!ret)
3900 ir_data->cached_ga_tag = pi_data->ga_tag;
3901 } else {
3902 ret = amd_iommu_deactivate_guest_mode(ir_data);
3903
3904 /*
3905 * This communicates the ga_tag back to the caller
3906 * so that it can do all the necessary clean up.
3907 */
3908 if (!ret)
3909 ir_data->cached_ga_tag = 0;
3910 }
3911
3912 return ret;
3913 }
3914
3915
3916 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3917 struct amd_ir_data *ir_data,
3918 struct irq_2_irte *irte_info,
3919 struct irq_cfg *cfg)
3920 {
3921
3922 /*
3923 * Atomically updates the IRTE with the new destination, vector
3924 * and flushes the interrupt entry cache.
3925 */
3926 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
3927 irte_info->index, cfg->vector,
3928 cfg->dest_apicid);
3929 }
3930
3931 static int amd_ir_set_affinity(struct irq_data *data,
3932 const struct cpumask *mask, bool force)
3933 {
3934 struct amd_ir_data *ir_data = data->chip_data;
3935 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3936 struct irq_cfg *cfg = irqd_cfg(data);
3937 struct irq_data *parent = data->parent_data;
3938 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3939 int ret;
3940
3941 if (!iommu)
3942 return -ENODEV;
3943
3944 ret = parent->chip->irq_set_affinity(parent, mask, force);
3945 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3946 return ret;
3947
3948 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3949 /*
3950 * After this point, all the interrupts will start arriving
3951 * at the new destination. So, time to cleanup the previous
3952 * vector allocation.
3953 */
3954 send_cleanup_vector(cfg);
3955
3956 return IRQ_SET_MASK_OK_DONE;
3957 }
3958
3959 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3960 {
3961 struct amd_ir_data *ir_data = irq_data->chip_data;
3962
3963 *msg = ir_data->msi_entry;
3964 }
3965
3966 static struct irq_chip amd_ir_chip = {
3967 .name = "AMD-IR",
3968 .irq_ack = apic_ack_irq,
3969 .irq_set_affinity = amd_ir_set_affinity,
3970 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
3971 .irq_compose_msi_msg = ir_compose_msi_msg,
3972 };
3973
3974 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3975 {
3976 struct fwnode_handle *fn;
3977
3978 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3979 if (!fn)
3980 return -ENOMEM;
3981 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3982 irq_domain_free_fwnode(fn);
3983 if (!iommu->ir_domain)
3984 return -ENOMEM;
3985
3986 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3987 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3988 "AMD-IR-MSI",
3989 iommu->index);
3990 return 0;
3991 }
3992
3993 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3994 {
3995 unsigned long flags;
3996 struct amd_iommu *iommu;
3997 struct irq_remap_table *table;
3998 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3999 int devid = ir_data->irq_2_irte.devid;
4000 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4001 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4002
4003 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4004 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4005 return 0;
4006
4007 iommu = amd_iommu_rlookup_table[devid];
4008 if (!iommu)
4009 return -ENODEV;
4010
4011 table = get_irq_table(devid);
4012 if (!table)
4013 return -ENODEV;
4014
4015 raw_spin_lock_irqsave(&table->lock, flags);
4016
4017 if (ref->lo.fields_vapic.guest_mode) {
4018 if (cpu >= 0) {
4019 ref->lo.fields_vapic.destination =
4020 APICID_TO_IRTE_DEST_LO(cpu);
4021 ref->hi.fields.destination =
4022 APICID_TO_IRTE_DEST_HI(cpu);
4023 }
4024 ref->lo.fields_vapic.is_run = is_run;
4025 barrier();
4026 }
4027
4028 raw_spin_unlock_irqrestore(&table->lock, flags);
4029
4030 iommu_flush_irt(iommu, devid);
4031 iommu_completion_wait(iommu);
4032 return 0;
4033 }
4034 EXPORT_SYMBOL(amd_iommu_update_ga);
4035 #endif
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