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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/pci.h>
12 #include <linux/acpi.h>
13 #include <linux/list.h>
14 #include <linux/bitmap.h>
15 #include <linux/slab.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/interrupt.h>
18 #include <linux/msi.h>
19 #include <linux/amd-iommu.h>
20 #include <linux/export.h>
21 #include <linux/iommu.h>
22 #include <linux/kmemleak.h>
23 #include <linux/mem_encrypt.h>
24 #include <asm/pci-direct.h>
25 #include <asm/iommu.h>
26 #include <asm/apic.h>
27 #include <asm/msidef.h>
28 #include <asm/gart.h>
29 #include <asm/x86_init.h>
30 #include <asm/iommu_table.h>
31 #include <asm/io_apic.h>
32 #include <asm/irq_remapping.h>
33
34 #include <linux/crash_dump.h>
35 #include "amd_iommu.h"
36 #include "amd_iommu_proto.h"
37 #include "amd_iommu_types.h"
38 #include "irq_remapping.h"
39
40 /*
41 * definitions for the ACPI scanning code
42 */
43 #define IVRS_HEADER_LENGTH 48
44
45 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
46 #define ACPI_IVMD_TYPE_ALL 0x20
47 #define ACPI_IVMD_TYPE 0x21
48 #define ACPI_IVMD_TYPE_RANGE 0x22
49
50 #define IVHD_DEV_ALL 0x01
51 #define IVHD_DEV_SELECT 0x02
52 #define IVHD_DEV_SELECT_RANGE_START 0x03
53 #define IVHD_DEV_RANGE_END 0x04
54 #define IVHD_DEV_ALIAS 0x42
55 #define IVHD_DEV_ALIAS_RANGE 0x43
56 #define IVHD_DEV_EXT_SELECT 0x46
57 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
58 #define IVHD_DEV_SPECIAL 0x48
59 #define IVHD_DEV_ACPI_HID 0xf0
60
61 #define UID_NOT_PRESENT 0
62 #define UID_IS_INTEGER 1
63 #define UID_IS_CHARACTER 2
64
65 #define IVHD_SPECIAL_IOAPIC 1
66 #define IVHD_SPECIAL_HPET 2
67
68 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
69 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
70 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
71 #define IVHD_FLAG_ISOC_EN_MASK 0x08
72
73 #define IVMD_FLAG_EXCL_RANGE 0x08
74 #define IVMD_FLAG_IW 0x04
75 #define IVMD_FLAG_IR 0x02
76 #define IVMD_FLAG_UNITY_MAP 0x01
77
78 #define ACPI_DEVFLAG_INITPASS 0x01
79 #define ACPI_DEVFLAG_EXTINT 0x02
80 #define ACPI_DEVFLAG_NMI 0x04
81 #define ACPI_DEVFLAG_SYSMGT1 0x10
82 #define ACPI_DEVFLAG_SYSMGT2 0x20
83 #define ACPI_DEVFLAG_LINT0 0x40
84 #define ACPI_DEVFLAG_LINT1 0x80
85 #define ACPI_DEVFLAG_ATSDIS 0x10000000
86
87 #define LOOP_TIMEOUT 100000
88 /*
89 * ACPI table definitions
90 *
91 * These data structures are laid over the table to parse the important values
92 * out of it.
93 */
94
95 extern const struct iommu_ops amd_iommu_ops;
96
97 /*
98 * structure describing one IOMMU in the ACPI table. Typically followed by one
99 * or more ivhd_entrys.
100 */
101 struct ivhd_header {
102 u8 type;
103 u8 flags;
104 u16 length;
105 u16 devid;
106 u16 cap_ptr;
107 u64 mmio_phys;
108 u16 pci_seg;
109 u16 info;
110 u32 efr_attr;
111
112 /* Following only valid on IVHD type 11h and 40h */
113 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
114 u64 res;
115 } __attribute__((packed));
116
117 /*
118 * A device entry describing which devices a specific IOMMU translates and
119 * which requestor ids they use.
120 */
121 struct ivhd_entry {
122 u8 type;
123 u16 devid;
124 u8 flags;
125 u32 ext;
126 u32 hidh;
127 u64 cid;
128 u8 uidf;
129 u8 uidl;
130 u8 uid;
131 } __attribute__((packed));
132
133 /*
134 * An AMD IOMMU memory definition structure. It defines things like exclusion
135 * ranges for devices and regions that should be unity mapped.
136 */
137 struct ivmd_header {
138 u8 type;
139 u8 flags;
140 u16 length;
141 u16 devid;
142 u16 aux;
143 u64 resv;
144 u64 range_start;
145 u64 range_length;
146 } __attribute__((packed));
147
148 bool amd_iommu_dump;
149 bool amd_iommu_irq_remap __read_mostly;
150
151 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
152 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
153
154 static bool amd_iommu_detected;
155 static bool __initdata amd_iommu_disabled;
156 static int amd_iommu_target_ivhd_type;
157
158 u16 amd_iommu_last_bdf; /* largest PCI device id we have
159 to handle */
160 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
161 we find in ACPI */
162 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
163
164 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
165 system */
166
167 /* Array to assign indices to IOMMUs*/
168 struct amd_iommu *amd_iommus[MAX_IOMMUS];
169
170 /* Number of IOMMUs present in the system */
171 static int amd_iommus_present;
172
173 /* IOMMUs have a non-present cache? */
174 bool amd_iommu_np_cache __read_mostly;
175 bool amd_iommu_iotlb_sup __read_mostly = true;
176
177 u32 amd_iommu_max_pasid __read_mostly = ~0;
178
179 bool amd_iommu_v2_present __read_mostly;
180 static bool amd_iommu_pc_present __read_mostly;
181
182 bool amd_iommu_force_isolation __read_mostly;
183
184 /*
185 * Pointer to the device table which is shared by all AMD IOMMUs
186 * it is indexed by the PCI device id or the HT unit id and contains
187 * information about the domain the device belongs to as well as the
188 * page table root pointer.
189 */
190 struct dev_table_entry *amd_iommu_dev_table;
191 /*
192 * Pointer to a device table which the content of old device table
193 * will be copied to. It's only be used in kdump kernel.
194 */
195 static struct dev_table_entry *old_dev_tbl_cpy;
196
197 /*
198 * The alias table is a driver specific data structure which contains the
199 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
200 * More than one device can share the same requestor id.
201 */
202 u16 *amd_iommu_alias_table;
203
204 /*
205 * The rlookup table is used to find the IOMMU which is responsible
206 * for a specific device. It is also indexed by the PCI device id.
207 */
208 struct amd_iommu **amd_iommu_rlookup_table;
209 EXPORT_SYMBOL(amd_iommu_rlookup_table);
210
211 /*
212 * This table is used to find the irq remapping table for a given device id
213 * quickly.
214 */
215 struct irq_remap_table **irq_lookup_table;
216
217 /*
218 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
219 * to know which ones are already in use.
220 */
221 unsigned long *amd_iommu_pd_alloc_bitmap;
222
223 static u32 dev_table_size; /* size of the device table */
224 static u32 alias_table_size; /* size of the alias table */
225 static u32 rlookup_table_size; /* size if the rlookup table */
226
227 enum iommu_init_state {
228 IOMMU_START_STATE,
229 IOMMU_IVRS_DETECTED,
230 IOMMU_ACPI_FINISHED,
231 IOMMU_ENABLED,
232 IOMMU_PCI_INIT,
233 IOMMU_INTERRUPTS_EN,
234 IOMMU_DMA_OPS,
235 IOMMU_INITIALIZED,
236 IOMMU_NOT_FOUND,
237 IOMMU_INIT_ERROR,
238 IOMMU_CMDLINE_DISABLED,
239 };
240
241 /* Early ioapic and hpet maps from kernel command line */
242 #define EARLY_MAP_SIZE 4
243 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
244 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
245 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
246
247 static int __initdata early_ioapic_map_size;
248 static int __initdata early_hpet_map_size;
249 static int __initdata early_acpihid_map_size;
250
251 static bool __initdata cmdline_maps;
252
253 static enum iommu_init_state init_state = IOMMU_START_STATE;
254
255 static int amd_iommu_enable_interrupts(void);
256 static int __init iommu_go_to_state(enum iommu_init_state state);
257 static void init_device_table_dma(void);
258
259 static bool amd_iommu_pre_enabled = true;
260
261 bool translation_pre_enabled(struct amd_iommu *iommu)
262 {
263 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
264 }
265 EXPORT_SYMBOL(translation_pre_enabled);
266
267 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
268 {
269 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
270 }
271
272 static void init_translation_status(struct amd_iommu *iommu)
273 {
274 u64 ctrl;
275
276 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
277 if (ctrl & (1<<CONTROL_IOMMU_EN))
278 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
279 }
280
281 static inline void update_last_devid(u16 devid)
282 {
283 if (devid > amd_iommu_last_bdf)
284 amd_iommu_last_bdf = devid;
285 }
286
287 static inline unsigned long tbl_size(int entry_size)
288 {
289 unsigned shift = PAGE_SHIFT +
290 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
291
292 return 1UL << shift;
293 }
294
295 int amd_iommu_get_num_iommus(void)
296 {
297 return amd_iommus_present;
298 }
299
300 /* Access to l1 and l2 indexed register spaces */
301
302 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
303 {
304 u32 val;
305
306 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
307 pci_read_config_dword(iommu->dev, 0xfc, &val);
308 return val;
309 }
310
311 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
312 {
313 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
314 pci_write_config_dword(iommu->dev, 0xfc, val);
315 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
316 }
317
318 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
319 {
320 u32 val;
321
322 pci_write_config_dword(iommu->dev, 0xf0, address);
323 pci_read_config_dword(iommu->dev, 0xf4, &val);
324 return val;
325 }
326
327 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
328 {
329 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
330 pci_write_config_dword(iommu->dev, 0xf4, val);
331 }
332
333 /****************************************************************************
334 *
335 * AMD IOMMU MMIO register space handling functions
336 *
337 * These functions are used to program the IOMMU device registers in
338 * MMIO space required for that driver.
339 *
340 ****************************************************************************/
341
342 /*
343 * This function set the exclusion range in the IOMMU. DMA accesses to the
344 * exclusion range are passed through untranslated
345 */
346 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
347 {
348 u64 start = iommu->exclusion_start & PAGE_MASK;
349 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
350 u64 entry;
351
352 if (!iommu->exclusion_start)
353 return;
354
355 entry = start | MMIO_EXCL_ENABLE_MASK;
356 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
357 &entry, sizeof(entry));
358
359 entry = limit;
360 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
361 &entry, sizeof(entry));
362 }
363
364 /* Programs the physical address of the device table into the IOMMU hardware */
365 static void iommu_set_device_table(struct amd_iommu *iommu)
366 {
367 u64 entry;
368
369 BUG_ON(iommu->mmio_base == NULL);
370
371 entry = iommu_virt_to_phys(amd_iommu_dev_table);
372 entry |= (dev_table_size >> 12) - 1;
373 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
374 &entry, sizeof(entry));
375 }
376
377 /* Generic functions to enable/disable certain features of the IOMMU. */
378 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
379 {
380 u64 ctrl;
381
382 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
383 ctrl |= (1ULL << bit);
384 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
385 }
386
387 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
388 {
389 u64 ctrl;
390
391 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
392 ctrl &= ~(1ULL << bit);
393 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
394 }
395
396 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
397 {
398 u64 ctrl;
399
400 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
401 ctrl &= ~CTRL_INV_TO_MASK;
402 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
403 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
404 }
405
406 /* Function to enable the hardware */
407 static void iommu_enable(struct amd_iommu *iommu)
408 {
409 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
410 }
411
412 static void iommu_disable(struct amd_iommu *iommu)
413 {
414 if (!iommu->mmio_base)
415 return;
416
417 /* Disable command buffer */
418 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
419
420 /* Disable event logging and event interrupts */
421 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
422 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
423
424 /* Disable IOMMU GA_LOG */
425 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
426 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
427
428 /* Disable IOMMU hardware itself */
429 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
430 }
431
432 /*
433 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
434 * the system has one.
435 */
436 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
437 {
438 if (!request_mem_region(address, end, "amd_iommu")) {
439 pr_err("Can not reserve memory region %llx-%llx for mmio\n",
440 address, end);
441 pr_err("This is a BIOS bug. Please contact your hardware vendor\n");
442 return NULL;
443 }
444
445 return (u8 __iomem *)ioremap(address, end);
446 }
447
448 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
449 {
450 if (iommu->mmio_base)
451 iounmap(iommu->mmio_base);
452 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
453 }
454
455 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
456 {
457 u32 size = 0;
458
459 switch (h->type) {
460 case 0x10:
461 size = 24;
462 break;
463 case 0x11:
464 case 0x40:
465 size = 40;
466 break;
467 }
468 return size;
469 }
470
471 /****************************************************************************
472 *
473 * The functions below belong to the first pass of AMD IOMMU ACPI table
474 * parsing. In this pass we try to find out the highest device id this
475 * code has to handle. Upon this information the size of the shared data
476 * structures is determined later.
477 *
478 ****************************************************************************/
479
480 /*
481 * This function calculates the length of a given IVHD entry
482 */
483 static inline int ivhd_entry_length(u8 *ivhd)
484 {
485 u32 type = ((struct ivhd_entry *)ivhd)->type;
486
487 if (type < 0x80) {
488 return 0x04 << (*ivhd >> 6);
489 } else if (type == IVHD_DEV_ACPI_HID) {
490 /* For ACPI_HID, offset 21 is uid len */
491 return *((u8 *)ivhd + 21) + 22;
492 }
493 return 0;
494 }
495
496 /*
497 * After reading the highest device id from the IOMMU PCI capability header
498 * this function looks if there is a higher device id defined in the ACPI table
499 */
500 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
501 {
502 u8 *p = (void *)h, *end = (void *)h;
503 struct ivhd_entry *dev;
504
505 u32 ivhd_size = get_ivhd_header_size(h);
506
507 if (!ivhd_size) {
508 pr_err("Unsupported IVHD type %#x\n", h->type);
509 return -EINVAL;
510 }
511
512 p += ivhd_size;
513 end += h->length;
514
515 while (p < end) {
516 dev = (struct ivhd_entry *)p;
517 switch (dev->type) {
518 case IVHD_DEV_ALL:
519 /* Use maximum BDF value for DEV_ALL */
520 update_last_devid(0xffff);
521 break;
522 case IVHD_DEV_SELECT:
523 case IVHD_DEV_RANGE_END:
524 case IVHD_DEV_ALIAS:
525 case IVHD_DEV_EXT_SELECT:
526 /* all the above subfield types refer to device ids */
527 update_last_devid(dev->devid);
528 break;
529 default:
530 break;
531 }
532 p += ivhd_entry_length(p);
533 }
534
535 WARN_ON(p != end);
536
537 return 0;
538 }
539
540 static int __init check_ivrs_checksum(struct acpi_table_header *table)
541 {
542 int i;
543 u8 checksum = 0, *p = (u8 *)table;
544
545 for (i = 0; i < table->length; ++i)
546 checksum += p[i];
547 if (checksum != 0) {
548 /* ACPI table corrupt */
549 pr_err(FW_BUG "IVRS invalid checksum\n");
550 return -ENODEV;
551 }
552
553 return 0;
554 }
555
556 /*
557 * Iterate over all IVHD entries in the ACPI table and find the highest device
558 * id which we need to handle. This is the first of three functions which parse
559 * the ACPI table. So we check the checksum here.
560 */
561 static int __init find_last_devid_acpi(struct acpi_table_header *table)
562 {
563 u8 *p = (u8 *)table, *end = (u8 *)table;
564 struct ivhd_header *h;
565
566 p += IVRS_HEADER_LENGTH;
567
568 end += table->length;
569 while (p < end) {
570 h = (struct ivhd_header *)p;
571 if (h->type == amd_iommu_target_ivhd_type) {
572 int ret = find_last_devid_from_ivhd(h);
573
574 if (ret)
575 return ret;
576 }
577 p += h->length;
578 }
579 WARN_ON(p != end);
580
581 return 0;
582 }
583
584 /****************************************************************************
585 *
586 * The following functions belong to the code path which parses the ACPI table
587 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
588 * data structures, initialize the device/alias/rlookup table and also
589 * basically initialize the hardware.
590 *
591 ****************************************************************************/
592
593 /*
594 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
595 * write commands to that buffer later and the IOMMU will execute them
596 * asynchronously
597 */
598 static int __init alloc_command_buffer(struct amd_iommu *iommu)
599 {
600 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
601 get_order(CMD_BUFFER_SIZE));
602
603 return iommu->cmd_buf ? 0 : -ENOMEM;
604 }
605
606 /*
607 * This function resets the command buffer if the IOMMU stopped fetching
608 * commands from it.
609 */
610 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
611 {
612 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
613
614 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
615 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
616 iommu->cmd_buf_head = 0;
617 iommu->cmd_buf_tail = 0;
618
619 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
620 }
621
622 /*
623 * This function writes the command buffer address to the hardware and
624 * enables it.
625 */
626 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
627 {
628 u64 entry;
629
630 BUG_ON(iommu->cmd_buf == NULL);
631
632 entry = iommu_virt_to_phys(iommu->cmd_buf);
633 entry |= MMIO_CMD_SIZE_512;
634
635 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
636 &entry, sizeof(entry));
637
638 amd_iommu_reset_cmd_buffer(iommu);
639 }
640
641 /*
642 * This function disables the command buffer
643 */
644 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
645 {
646 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
647 }
648
649 static void __init free_command_buffer(struct amd_iommu *iommu)
650 {
651 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
652 }
653
654 /* allocates the memory where the IOMMU will log its events to */
655 static int __init alloc_event_buffer(struct amd_iommu *iommu)
656 {
657 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
658 get_order(EVT_BUFFER_SIZE));
659
660 return iommu->evt_buf ? 0 : -ENOMEM;
661 }
662
663 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
664 {
665 u64 entry;
666
667 BUG_ON(iommu->evt_buf == NULL);
668
669 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
670
671 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
672 &entry, sizeof(entry));
673
674 /* set head and tail to zero manually */
675 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
676 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
677
678 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
679 }
680
681 /*
682 * This function disables the event log buffer
683 */
684 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
685 {
686 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
687 }
688
689 static void __init free_event_buffer(struct amd_iommu *iommu)
690 {
691 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
692 }
693
694 /* allocates the memory where the IOMMU will log its events to */
695 static int __init alloc_ppr_log(struct amd_iommu *iommu)
696 {
697 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
698 get_order(PPR_LOG_SIZE));
699
700 return iommu->ppr_log ? 0 : -ENOMEM;
701 }
702
703 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
704 {
705 u64 entry;
706
707 if (iommu->ppr_log == NULL)
708 return;
709
710 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
711
712 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
713 &entry, sizeof(entry));
714
715 /* set head and tail to zero manually */
716 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
717 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
718
719 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN);
720 iommu_feature_enable(iommu, CONTROL_PPR_EN);
721 }
722
723 static void __init free_ppr_log(struct amd_iommu *iommu)
724 {
725 if (iommu->ppr_log == NULL)
726 return;
727
728 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
729 }
730
731 static void free_ga_log(struct amd_iommu *iommu)
732 {
733 #ifdef CONFIG_IRQ_REMAP
734 if (iommu->ga_log)
735 free_pages((unsigned long)iommu->ga_log,
736 get_order(GA_LOG_SIZE));
737 if (iommu->ga_log_tail)
738 free_pages((unsigned long)iommu->ga_log_tail,
739 get_order(8));
740 #endif
741 }
742
743 static int iommu_ga_log_enable(struct amd_iommu *iommu)
744 {
745 #ifdef CONFIG_IRQ_REMAP
746 u32 status, i;
747
748 if (!iommu->ga_log)
749 return -EINVAL;
750
751 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
752
753 /* Check if already running */
754 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
755 return 0;
756
757 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
758 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
759
760 for (i = 0; i < LOOP_TIMEOUT; ++i) {
761 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
762 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
763 break;
764 }
765
766 if (i >= LOOP_TIMEOUT)
767 return -EINVAL;
768 #endif /* CONFIG_IRQ_REMAP */
769 return 0;
770 }
771
772 #ifdef CONFIG_IRQ_REMAP
773 static int iommu_init_ga_log(struct amd_iommu *iommu)
774 {
775 u64 entry;
776
777 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
778 return 0;
779
780 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
781 get_order(GA_LOG_SIZE));
782 if (!iommu->ga_log)
783 goto err_out;
784
785 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
786 get_order(8));
787 if (!iommu->ga_log_tail)
788 goto err_out;
789
790 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
791 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
792 &entry, sizeof(entry));
793 entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
794 (BIT_ULL(52)-1)) & ~7ULL;
795 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
796 &entry, sizeof(entry));
797 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
798 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
799
800 return 0;
801 err_out:
802 free_ga_log(iommu);
803 return -EINVAL;
804 }
805 #endif /* CONFIG_IRQ_REMAP */
806
807 static int iommu_init_ga(struct amd_iommu *iommu)
808 {
809 int ret = 0;
810
811 #ifdef CONFIG_IRQ_REMAP
812 /* Note: We have already checked GASup from IVRS table.
813 * Now, we need to make sure that GAMSup is set.
814 */
815 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
816 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
817 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
818
819 ret = iommu_init_ga_log(iommu);
820 #endif /* CONFIG_IRQ_REMAP */
821
822 return ret;
823 }
824
825 static void iommu_enable_xt(struct amd_iommu *iommu)
826 {
827 #ifdef CONFIG_IRQ_REMAP
828 /*
829 * XT mode (32-bit APIC destination ID) requires
830 * GA mode (128-bit IRTE support) as a prerequisite.
831 */
832 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
833 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
834 iommu_feature_enable(iommu, CONTROL_XT_EN);
835 #endif /* CONFIG_IRQ_REMAP */
836 }
837
838 static void iommu_enable_gt(struct amd_iommu *iommu)
839 {
840 if (!iommu_feature(iommu, FEATURE_GT))
841 return;
842
843 iommu_feature_enable(iommu, CONTROL_GT_EN);
844 }
845
846 /* sets a specific bit in the device table entry. */
847 static void set_dev_entry_bit(u16 devid, u8 bit)
848 {
849 int i = (bit >> 6) & 0x03;
850 int _bit = bit & 0x3f;
851
852 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
853 }
854
855 static int get_dev_entry_bit(u16 devid, u8 bit)
856 {
857 int i = (bit >> 6) & 0x03;
858 int _bit = bit & 0x3f;
859
860 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
861 }
862
863
864 static bool copy_device_table(void)
865 {
866 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
867 struct dev_table_entry *old_devtb = NULL;
868 u32 lo, hi, devid, old_devtb_size;
869 phys_addr_t old_devtb_phys;
870 struct amd_iommu *iommu;
871 u16 dom_id, dte_v, irq_v;
872 gfp_t gfp_flag;
873 u64 tmp;
874
875 if (!amd_iommu_pre_enabled)
876 return false;
877
878 pr_warn("Translation is already enabled - trying to copy translation structures\n");
879 for_each_iommu(iommu) {
880 /* All IOMMUs should use the same device table with the same size */
881 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
882 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
883 entry = (((u64) hi) << 32) + lo;
884 if (last_entry && last_entry != entry) {
885 pr_err("IOMMU:%d should use the same dev table as others!\n",
886 iommu->index);
887 return false;
888 }
889 last_entry = entry;
890
891 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
892 if (old_devtb_size != dev_table_size) {
893 pr_err("The device table size of IOMMU:%d is not expected!\n",
894 iommu->index);
895 return false;
896 }
897 }
898
899 /*
900 * When SME is enabled in the first kernel, the entry includes the
901 * memory encryption mask(sme_me_mask), we must remove the memory
902 * encryption mask to obtain the true physical address in kdump kernel.
903 */
904 old_devtb_phys = __sme_clr(entry) & PAGE_MASK;
905
906 if (old_devtb_phys >= 0x100000000ULL) {
907 pr_err("The address of old device table is above 4G, not trustworthy!\n");
908 return false;
909 }
910 old_devtb = (sme_active() && is_kdump_kernel())
911 ? (__force void *)ioremap_encrypted(old_devtb_phys,
912 dev_table_size)
913 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
914
915 if (!old_devtb)
916 return false;
917
918 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
919 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
920 get_order(dev_table_size));
921 if (old_dev_tbl_cpy == NULL) {
922 pr_err("Failed to allocate memory for copying old device table!\n");
923 return false;
924 }
925
926 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
927 old_dev_tbl_cpy[devid] = old_devtb[devid];
928 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
929 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
930
931 if (dte_v && dom_id) {
932 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
933 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
934 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
935 /* If gcr3 table existed, mask it out */
936 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
937 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
938 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
939 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
940 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
941 tmp |= DTE_FLAG_GV;
942 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
943 }
944 }
945
946 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
947 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
948 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
949 if (irq_v && (int_ctl || int_tab_len)) {
950 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
951 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
952 pr_err("Wrong old irq remapping flag: %#x\n", devid);
953 return false;
954 }
955
956 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
957 }
958 }
959 memunmap(old_devtb);
960
961 return true;
962 }
963
964 void amd_iommu_apply_erratum_63(u16 devid)
965 {
966 int sysmgt;
967
968 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
969 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
970
971 if (sysmgt == 0x01)
972 set_dev_entry_bit(devid, DEV_ENTRY_IW);
973 }
974
975 /* Writes the specific IOMMU for a device into the rlookup table */
976 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
977 {
978 amd_iommu_rlookup_table[devid] = iommu;
979 }
980
981 /*
982 * This function takes the device specific flags read from the ACPI
983 * table and sets up the device table entry with that information
984 */
985 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
986 u16 devid, u32 flags, u32 ext_flags)
987 {
988 if (flags & ACPI_DEVFLAG_INITPASS)
989 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
990 if (flags & ACPI_DEVFLAG_EXTINT)
991 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
992 if (flags & ACPI_DEVFLAG_NMI)
993 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
994 if (flags & ACPI_DEVFLAG_SYSMGT1)
995 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
996 if (flags & ACPI_DEVFLAG_SYSMGT2)
997 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
998 if (flags & ACPI_DEVFLAG_LINT0)
999 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
1000 if (flags & ACPI_DEVFLAG_LINT1)
1001 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
1002
1003 amd_iommu_apply_erratum_63(devid);
1004
1005 set_iommu_for_device(iommu, devid);
1006 }
1007
1008 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
1009 {
1010 struct devid_map *entry;
1011 struct list_head *list;
1012
1013 if (type == IVHD_SPECIAL_IOAPIC)
1014 list = &ioapic_map;
1015 else if (type == IVHD_SPECIAL_HPET)
1016 list = &hpet_map;
1017 else
1018 return -EINVAL;
1019
1020 list_for_each_entry(entry, list, list) {
1021 if (!(entry->id == id && entry->cmd_line))
1022 continue;
1023
1024 pr_info("Command-line override present for %s id %d - ignoring\n",
1025 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1026
1027 *devid = entry->devid;
1028
1029 return 0;
1030 }
1031
1032 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1033 if (!entry)
1034 return -ENOMEM;
1035
1036 entry->id = id;
1037 entry->devid = *devid;
1038 entry->cmd_line = cmd_line;
1039
1040 list_add_tail(&entry->list, list);
1041
1042 return 0;
1043 }
1044
1045 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1046 bool cmd_line)
1047 {
1048 struct acpihid_map_entry *entry;
1049 struct list_head *list = &acpihid_map;
1050
1051 list_for_each_entry(entry, list, list) {
1052 if (strcmp(entry->hid, hid) ||
1053 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1054 !entry->cmd_line)
1055 continue;
1056
1057 pr_info("Command-line override for hid:%s uid:%s\n",
1058 hid, uid);
1059 *devid = entry->devid;
1060 return 0;
1061 }
1062
1063 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1064 if (!entry)
1065 return -ENOMEM;
1066
1067 memcpy(entry->uid, uid, strlen(uid));
1068 memcpy(entry->hid, hid, strlen(hid));
1069 entry->devid = *devid;
1070 entry->cmd_line = cmd_line;
1071 entry->root_devid = (entry->devid & (~0x7));
1072
1073 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n",
1074 entry->cmd_line ? "cmd" : "ivrs",
1075 entry->hid, entry->uid, entry->root_devid);
1076
1077 list_add_tail(&entry->list, list);
1078 return 0;
1079 }
1080
1081 static int __init add_early_maps(void)
1082 {
1083 int i, ret;
1084
1085 for (i = 0; i < early_ioapic_map_size; ++i) {
1086 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1087 early_ioapic_map[i].id,
1088 &early_ioapic_map[i].devid,
1089 early_ioapic_map[i].cmd_line);
1090 if (ret)
1091 return ret;
1092 }
1093
1094 for (i = 0; i < early_hpet_map_size; ++i) {
1095 ret = add_special_device(IVHD_SPECIAL_HPET,
1096 early_hpet_map[i].id,
1097 &early_hpet_map[i].devid,
1098 early_hpet_map[i].cmd_line);
1099 if (ret)
1100 return ret;
1101 }
1102
1103 for (i = 0; i < early_acpihid_map_size; ++i) {
1104 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1105 early_acpihid_map[i].uid,
1106 &early_acpihid_map[i].devid,
1107 early_acpihid_map[i].cmd_line);
1108 if (ret)
1109 return ret;
1110 }
1111
1112 return 0;
1113 }
1114
1115 /*
1116 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1117 * it
1118 */
1119 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
1120 {
1121 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
1122 return;
1123
1124 /*
1125 * Treat per-device exclusion ranges as r/w unity-mapped regions
1126 * since some buggy BIOSes might lead to the overwritten exclusion
1127 * range (exclusion_start and exclusion_length members). This
1128 * happens when there are multiple exclusion ranges (IVMD entries)
1129 * defined in ACPI table.
1130 */
1131 m->flags = (IVMD_FLAG_IW | IVMD_FLAG_IR | IVMD_FLAG_UNITY_MAP);
1132 }
1133
1134 /*
1135 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1136 * initializes the hardware and our data structures with it.
1137 */
1138 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1139 struct ivhd_header *h)
1140 {
1141 u8 *p = (u8 *)h;
1142 u8 *end = p, flags = 0;
1143 u16 devid = 0, devid_start = 0, devid_to = 0;
1144 u32 dev_i, ext_flags = 0;
1145 bool alias = false;
1146 struct ivhd_entry *e;
1147 u32 ivhd_size;
1148 int ret;
1149
1150
1151 ret = add_early_maps();
1152 if (ret)
1153 return ret;
1154
1155 amd_iommu_apply_ivrs_quirks();
1156
1157 /*
1158 * First save the recommended feature enable bits from ACPI
1159 */
1160 iommu->acpi_flags = h->flags;
1161
1162 /*
1163 * Done. Now parse the device entries
1164 */
1165 ivhd_size = get_ivhd_header_size(h);
1166 if (!ivhd_size) {
1167 pr_err("Unsupported IVHD type %#x\n", h->type);
1168 return -EINVAL;
1169 }
1170
1171 p += ivhd_size;
1172
1173 end += h->length;
1174
1175
1176 while (p < end) {
1177 e = (struct ivhd_entry *)p;
1178 switch (e->type) {
1179 case IVHD_DEV_ALL:
1180
1181 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1182
1183 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1184 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1185 break;
1186 case IVHD_DEV_SELECT:
1187
1188 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1189 "flags: %02x\n",
1190 PCI_BUS_NUM(e->devid),
1191 PCI_SLOT(e->devid),
1192 PCI_FUNC(e->devid),
1193 e->flags);
1194
1195 devid = e->devid;
1196 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1197 break;
1198 case IVHD_DEV_SELECT_RANGE_START:
1199
1200 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1201 "devid: %02x:%02x.%x flags: %02x\n",
1202 PCI_BUS_NUM(e->devid),
1203 PCI_SLOT(e->devid),
1204 PCI_FUNC(e->devid),
1205 e->flags);
1206
1207 devid_start = e->devid;
1208 flags = e->flags;
1209 ext_flags = 0;
1210 alias = false;
1211 break;
1212 case IVHD_DEV_ALIAS:
1213
1214 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1215 "flags: %02x devid_to: %02x:%02x.%x\n",
1216 PCI_BUS_NUM(e->devid),
1217 PCI_SLOT(e->devid),
1218 PCI_FUNC(e->devid),
1219 e->flags,
1220 PCI_BUS_NUM(e->ext >> 8),
1221 PCI_SLOT(e->ext >> 8),
1222 PCI_FUNC(e->ext >> 8));
1223
1224 devid = e->devid;
1225 devid_to = e->ext >> 8;
1226 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1227 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1228 amd_iommu_alias_table[devid] = devid_to;
1229 break;
1230 case IVHD_DEV_ALIAS_RANGE:
1231
1232 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1233 "devid: %02x:%02x.%x flags: %02x "
1234 "devid_to: %02x:%02x.%x\n",
1235 PCI_BUS_NUM(e->devid),
1236 PCI_SLOT(e->devid),
1237 PCI_FUNC(e->devid),
1238 e->flags,
1239 PCI_BUS_NUM(e->ext >> 8),
1240 PCI_SLOT(e->ext >> 8),
1241 PCI_FUNC(e->ext >> 8));
1242
1243 devid_start = e->devid;
1244 flags = e->flags;
1245 devid_to = e->ext >> 8;
1246 ext_flags = 0;
1247 alias = true;
1248 break;
1249 case IVHD_DEV_EXT_SELECT:
1250
1251 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1252 "flags: %02x ext: %08x\n",
1253 PCI_BUS_NUM(e->devid),
1254 PCI_SLOT(e->devid),
1255 PCI_FUNC(e->devid),
1256 e->flags, e->ext);
1257
1258 devid = e->devid;
1259 set_dev_entry_from_acpi(iommu, devid, e->flags,
1260 e->ext);
1261 break;
1262 case IVHD_DEV_EXT_SELECT_RANGE:
1263
1264 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1265 "%02x:%02x.%x flags: %02x ext: %08x\n",
1266 PCI_BUS_NUM(e->devid),
1267 PCI_SLOT(e->devid),
1268 PCI_FUNC(e->devid),
1269 e->flags, e->ext);
1270
1271 devid_start = e->devid;
1272 flags = e->flags;
1273 ext_flags = e->ext;
1274 alias = false;
1275 break;
1276 case IVHD_DEV_RANGE_END:
1277
1278 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1279 PCI_BUS_NUM(e->devid),
1280 PCI_SLOT(e->devid),
1281 PCI_FUNC(e->devid));
1282
1283 devid = e->devid;
1284 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1285 if (alias) {
1286 amd_iommu_alias_table[dev_i] = devid_to;
1287 set_dev_entry_from_acpi(iommu,
1288 devid_to, flags, ext_flags);
1289 }
1290 set_dev_entry_from_acpi(iommu, dev_i,
1291 flags, ext_flags);
1292 }
1293 break;
1294 case IVHD_DEV_SPECIAL: {
1295 u8 handle, type;
1296 const char *var;
1297 u16 devid;
1298 int ret;
1299
1300 handle = e->ext & 0xff;
1301 devid = (e->ext >> 8) & 0xffff;
1302 type = (e->ext >> 24) & 0xff;
1303
1304 if (type == IVHD_SPECIAL_IOAPIC)
1305 var = "IOAPIC";
1306 else if (type == IVHD_SPECIAL_HPET)
1307 var = "HPET";
1308 else
1309 var = "UNKNOWN";
1310
1311 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1312 var, (int)handle,
1313 PCI_BUS_NUM(devid),
1314 PCI_SLOT(devid),
1315 PCI_FUNC(devid));
1316
1317 ret = add_special_device(type, handle, &devid, false);
1318 if (ret)
1319 return ret;
1320
1321 /*
1322 * add_special_device might update the devid in case a
1323 * command-line override is present. So call
1324 * set_dev_entry_from_acpi after add_special_device.
1325 */
1326 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1327
1328 break;
1329 }
1330 case IVHD_DEV_ACPI_HID: {
1331 u16 devid;
1332 u8 hid[ACPIHID_HID_LEN] = {0};
1333 u8 uid[ACPIHID_UID_LEN] = {0};
1334 int ret;
1335
1336 if (h->type != 0x40) {
1337 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1338 e->type);
1339 break;
1340 }
1341
1342 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1343 hid[ACPIHID_HID_LEN - 1] = '\0';
1344
1345 if (!(*hid)) {
1346 pr_err(FW_BUG "Invalid HID.\n");
1347 break;
1348 }
1349
1350 switch (e->uidf) {
1351 case UID_NOT_PRESENT:
1352
1353 if (e->uidl != 0)
1354 pr_warn(FW_BUG "Invalid UID length.\n");
1355
1356 break;
1357 case UID_IS_INTEGER:
1358
1359 sprintf(uid, "%d", e->uid);
1360
1361 break;
1362 case UID_IS_CHARACTER:
1363
1364 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1365 uid[ACPIHID_UID_LEN - 1] = '\0';
1366
1367 break;
1368 default:
1369 break;
1370 }
1371
1372 devid = e->devid;
1373 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1374 hid, uid,
1375 PCI_BUS_NUM(devid),
1376 PCI_SLOT(devid),
1377 PCI_FUNC(devid));
1378
1379 flags = e->flags;
1380
1381 ret = add_acpi_hid_device(hid, uid, &devid, false);
1382 if (ret)
1383 return ret;
1384
1385 /*
1386 * add_special_device might update the devid in case a
1387 * command-line override is present. So call
1388 * set_dev_entry_from_acpi after add_special_device.
1389 */
1390 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1391
1392 break;
1393 }
1394 default:
1395 break;
1396 }
1397
1398 p += ivhd_entry_length(p);
1399 }
1400
1401 return 0;
1402 }
1403
1404 static void __init free_iommu_one(struct amd_iommu *iommu)
1405 {
1406 free_command_buffer(iommu);
1407 free_event_buffer(iommu);
1408 free_ppr_log(iommu);
1409 free_ga_log(iommu);
1410 iommu_unmap_mmio_space(iommu);
1411 }
1412
1413 static void __init free_iommu_all(void)
1414 {
1415 struct amd_iommu *iommu, *next;
1416
1417 for_each_iommu_safe(iommu, next) {
1418 list_del(&iommu->list);
1419 free_iommu_one(iommu);
1420 kfree(iommu);
1421 }
1422 }
1423
1424 /*
1425 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1426 * Workaround:
1427 * BIOS should disable L2B micellaneous clock gating by setting
1428 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1429 */
1430 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1431 {
1432 u32 value;
1433
1434 if ((boot_cpu_data.x86 != 0x15) ||
1435 (boot_cpu_data.x86_model < 0x10) ||
1436 (boot_cpu_data.x86_model > 0x1f))
1437 return;
1438
1439 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1440 pci_read_config_dword(iommu->dev, 0xf4, &value);
1441
1442 if (value & BIT(2))
1443 return;
1444
1445 /* Select NB indirect register 0x90 and enable writing */
1446 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1447
1448 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1449 pci_info(iommu->dev, "Applying erratum 746 workaround\n");
1450
1451 /* Clear the enable writing bit */
1452 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1453 }
1454
1455 /*
1456 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1457 * Workaround:
1458 * BIOS should enable ATS write permission check by setting
1459 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1460 */
1461 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1462 {
1463 u32 value;
1464
1465 if ((boot_cpu_data.x86 != 0x15) ||
1466 (boot_cpu_data.x86_model < 0x30) ||
1467 (boot_cpu_data.x86_model > 0x3f))
1468 return;
1469
1470 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1471 value = iommu_read_l2(iommu, 0x47);
1472
1473 if (value & BIT(0))
1474 return;
1475
1476 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1477 iommu_write_l2(iommu, 0x47, value | BIT(0));
1478
1479 pci_info(iommu->dev, "Applying ATS write check workaround\n");
1480 }
1481
1482 /*
1483 * This function clues the initialization function for one IOMMU
1484 * together and also allocates the command buffer and programs the
1485 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1486 */
1487 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1488 {
1489 int ret;
1490
1491 raw_spin_lock_init(&iommu->lock);
1492
1493 /* Add IOMMU to internal data structures */
1494 list_add_tail(&iommu->list, &amd_iommu_list);
1495 iommu->index = amd_iommus_present++;
1496
1497 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1498 WARN(1, "System has more IOMMUs than supported by this driver\n");
1499 return -ENOSYS;
1500 }
1501
1502 /* Index is fine - add IOMMU to the array */
1503 amd_iommus[iommu->index] = iommu;
1504
1505 /*
1506 * Copy data from ACPI table entry to the iommu struct
1507 */
1508 iommu->devid = h->devid;
1509 iommu->cap_ptr = h->cap_ptr;
1510 iommu->pci_seg = h->pci_seg;
1511 iommu->mmio_phys = h->mmio_phys;
1512
1513 switch (h->type) {
1514 case 0x10:
1515 /* Check if IVHD EFR contains proper max banks/counters */
1516 if ((h->efr_attr != 0) &&
1517 ((h->efr_attr & (0xF << 13)) != 0) &&
1518 ((h->efr_attr & (0x3F << 17)) != 0))
1519 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1520 else
1521 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1522 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1523 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1524 break;
1525 case 0x11:
1526 case 0x40:
1527 if (h->efr_reg & (1 << 9))
1528 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1529 else
1530 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1531 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1532 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1533 /*
1534 * Note: Since iommu_update_intcapxt() leverages
1535 * the IOMMU MMIO access to MSI capability block registers
1536 * for MSI address lo/hi/data, we need to check both
1537 * EFR[XtSup] and EFR[MsiCapMmioSup] for x2APIC support.
1538 */
1539 if ((h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) &&
1540 (h->efr_reg & BIT(IOMMU_EFR_MSICAPMMIOSUP_SHIFT)))
1541 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
1542 break;
1543 default:
1544 return -EINVAL;
1545 }
1546
1547 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1548 iommu->mmio_phys_end);
1549 if (!iommu->mmio_base)
1550 return -ENOMEM;
1551
1552 if (alloc_command_buffer(iommu))
1553 return -ENOMEM;
1554
1555 if (alloc_event_buffer(iommu))
1556 return -ENOMEM;
1557
1558 iommu->int_enabled = false;
1559
1560 init_translation_status(iommu);
1561 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1562 iommu_disable(iommu);
1563 clear_translation_pre_enabled(iommu);
1564 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1565 iommu->index);
1566 }
1567 if (amd_iommu_pre_enabled)
1568 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1569
1570 ret = init_iommu_from_acpi(iommu, h);
1571 if (ret)
1572 return ret;
1573
1574 ret = amd_iommu_create_irq_domain(iommu);
1575 if (ret)
1576 return ret;
1577
1578 /*
1579 * Make sure IOMMU is not considered to translate itself. The IVRS
1580 * table tells us so, but this is a lie!
1581 */
1582 amd_iommu_rlookup_table[iommu->devid] = NULL;
1583
1584 return 0;
1585 }
1586
1587 /**
1588 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1589 * @ivrs Pointer to the IVRS header
1590 *
1591 * This function search through all IVDB of the maximum supported IVHD
1592 */
1593 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1594 {
1595 u8 *base = (u8 *)ivrs;
1596 struct ivhd_header *ivhd = (struct ivhd_header *)
1597 (base + IVRS_HEADER_LENGTH);
1598 u8 last_type = ivhd->type;
1599 u16 devid = ivhd->devid;
1600
1601 while (((u8 *)ivhd - base < ivrs->length) &&
1602 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1603 u8 *p = (u8 *) ivhd;
1604
1605 if (ivhd->devid == devid)
1606 last_type = ivhd->type;
1607 ivhd = (struct ivhd_header *)(p + ivhd->length);
1608 }
1609
1610 return last_type;
1611 }
1612
1613 /*
1614 * Iterates over all IOMMU entries in the ACPI table, allocates the
1615 * IOMMU structure and initializes it with init_iommu_one()
1616 */
1617 static int __init init_iommu_all(struct acpi_table_header *table)
1618 {
1619 u8 *p = (u8 *)table, *end = (u8 *)table;
1620 struct ivhd_header *h;
1621 struct amd_iommu *iommu;
1622 int ret;
1623
1624 end += table->length;
1625 p += IVRS_HEADER_LENGTH;
1626
1627 while (p < end) {
1628 h = (struct ivhd_header *)p;
1629 if (*p == amd_iommu_target_ivhd_type) {
1630
1631 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1632 "seg: %d flags: %01x info %04x\n",
1633 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1634 PCI_FUNC(h->devid), h->cap_ptr,
1635 h->pci_seg, h->flags, h->info);
1636 DUMP_printk(" mmio-addr: %016llx\n",
1637 h->mmio_phys);
1638
1639 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1640 if (iommu == NULL)
1641 return -ENOMEM;
1642
1643 ret = init_iommu_one(iommu, h);
1644 if (ret)
1645 return ret;
1646 }
1647 p += h->length;
1648
1649 }
1650 WARN_ON(p != end);
1651
1652 return 0;
1653 }
1654
1655 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1656 u8 fxn, u64 *value, bool is_write);
1657
1658 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1659 {
1660 struct pci_dev *pdev = iommu->dev;
1661 u64 val = 0xabcd, val2 = 0, save_reg = 0;
1662
1663 if (!iommu_feature(iommu, FEATURE_PC))
1664 return;
1665
1666 amd_iommu_pc_present = true;
1667
1668 /* save the value to restore, if writable */
1669 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false))
1670 goto pc_false;
1671
1672 /* Check if the performance counters can be written to */
1673 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1674 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1675 (val != val2))
1676 goto pc_false;
1677
1678 /* restore */
1679 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true))
1680 goto pc_false;
1681
1682 pci_info(pdev, "IOMMU performance counters supported\n");
1683
1684 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1685 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1686 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1687
1688 return;
1689
1690 pc_false:
1691 pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n");
1692 amd_iommu_pc_present = false;
1693 return;
1694 }
1695
1696 static ssize_t amd_iommu_show_cap(struct device *dev,
1697 struct device_attribute *attr,
1698 char *buf)
1699 {
1700 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1701 return sprintf(buf, "%x\n", iommu->cap);
1702 }
1703 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1704
1705 static ssize_t amd_iommu_show_features(struct device *dev,
1706 struct device_attribute *attr,
1707 char *buf)
1708 {
1709 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1710 return sprintf(buf, "%llx\n", iommu->features);
1711 }
1712 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1713
1714 static struct attribute *amd_iommu_attrs[] = {
1715 &dev_attr_cap.attr,
1716 &dev_attr_features.attr,
1717 NULL,
1718 };
1719
1720 static struct attribute_group amd_iommu_group = {
1721 .name = "amd-iommu",
1722 .attrs = amd_iommu_attrs,
1723 };
1724
1725 static const struct attribute_group *amd_iommu_groups[] = {
1726 &amd_iommu_group,
1727 NULL,
1728 };
1729
1730 static int __init iommu_init_pci(struct amd_iommu *iommu)
1731 {
1732 int cap_ptr = iommu->cap_ptr;
1733 int ret;
1734
1735 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
1736 iommu->devid & 0xff);
1737 if (!iommu->dev)
1738 return -ENODEV;
1739
1740 /* Prevent binding other PCI device drivers to IOMMU devices */
1741 iommu->dev->match_driver = false;
1742
1743 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1744 &iommu->cap);
1745
1746 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1747 amd_iommu_iotlb_sup = false;
1748
1749 /* read extended feature bits */
1750 iommu->features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);
1751
1752 if (iommu_feature(iommu, FEATURE_GT)) {
1753 int glxval;
1754 u32 max_pasid;
1755 u64 pasmax;
1756
1757 pasmax = iommu->features & FEATURE_PASID_MASK;
1758 pasmax >>= FEATURE_PASID_SHIFT;
1759 max_pasid = (1 << (pasmax + 1)) - 1;
1760
1761 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1762
1763 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1764
1765 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1766 glxval >>= FEATURE_GLXVAL_SHIFT;
1767
1768 if (amd_iommu_max_glx_val == -1)
1769 amd_iommu_max_glx_val = glxval;
1770 else
1771 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1772 }
1773
1774 if (iommu_feature(iommu, FEATURE_GT) &&
1775 iommu_feature(iommu, FEATURE_PPR)) {
1776 iommu->is_iommu_v2 = true;
1777 amd_iommu_v2_present = true;
1778 }
1779
1780 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1781 return -ENOMEM;
1782
1783 ret = iommu_init_ga(iommu);
1784 if (ret)
1785 return ret;
1786
1787 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1788 amd_iommu_np_cache = true;
1789
1790 init_iommu_perf_ctr(iommu);
1791
1792 if (is_rd890_iommu(iommu->dev)) {
1793 int i, j;
1794
1795 iommu->root_pdev =
1796 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
1797 PCI_DEVFN(0, 0));
1798
1799 /*
1800 * Some rd890 systems may not be fully reconfigured by the
1801 * BIOS, so it's necessary for us to store this information so
1802 * it can be reprogrammed on resume
1803 */
1804 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1805 &iommu->stored_addr_lo);
1806 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1807 &iommu->stored_addr_hi);
1808
1809 /* Low bit locks writes to configuration space */
1810 iommu->stored_addr_lo &= ~1;
1811
1812 for (i = 0; i < 6; i++)
1813 for (j = 0; j < 0x12; j++)
1814 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1815
1816 for (i = 0; i < 0x83; i++)
1817 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1818 }
1819
1820 amd_iommu_erratum_746_workaround(iommu);
1821 amd_iommu_ats_write_check_workaround(iommu);
1822
1823 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1824 amd_iommu_groups, "ivhd%d", iommu->index);
1825 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1826 iommu_device_register(&iommu->iommu);
1827
1828 return pci_enable_device(iommu->dev);
1829 }
1830
1831 static void print_iommu_info(void)
1832 {
1833 static const char * const feat_str[] = {
1834 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1835 "IA", "GA", "HE", "PC"
1836 };
1837 struct amd_iommu *iommu;
1838
1839 for_each_iommu(iommu) {
1840 struct pci_dev *pdev = iommu->dev;
1841 int i;
1842
1843 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr);
1844
1845 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1846 pci_info(pdev, "Extended features (%#llx):\n",
1847 iommu->features);
1848 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1849 if (iommu_feature(iommu, (1ULL << i)))
1850 pr_cont(" %s", feat_str[i]);
1851 }
1852
1853 if (iommu->features & FEATURE_GAM_VAPIC)
1854 pr_cont(" GA_vAPIC");
1855
1856 pr_cont("\n");
1857 }
1858 }
1859 if (irq_remapping_enabled) {
1860 pr_info("Interrupt remapping enabled\n");
1861 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1862 pr_info("Virtual APIC enabled\n");
1863 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
1864 pr_info("X2APIC enabled\n");
1865 }
1866 }
1867
1868 static int __init amd_iommu_init_pci(void)
1869 {
1870 struct amd_iommu *iommu;
1871 int ret = 0;
1872
1873 for_each_iommu(iommu) {
1874 ret = iommu_init_pci(iommu);
1875 if (ret)
1876 break;
1877 }
1878
1879 /*
1880 * Order is important here to make sure any unity map requirements are
1881 * fulfilled. The unity mappings are created and written to the device
1882 * table during the amd_iommu_init_api() call.
1883 *
1884 * After that we call init_device_table_dma() to make sure any
1885 * uninitialized DTE will block DMA, and in the end we flush the caches
1886 * of all IOMMUs to make sure the changes to the device table are
1887 * active.
1888 */
1889 ret = amd_iommu_init_api();
1890
1891 init_device_table_dma();
1892
1893 for_each_iommu(iommu)
1894 iommu_flush_all_caches(iommu);
1895
1896 if (!ret)
1897 print_iommu_info();
1898
1899 return ret;
1900 }
1901
1902 /****************************************************************************
1903 *
1904 * The following functions initialize the MSI interrupts for all IOMMUs
1905 * in the system. It's a bit challenging because there could be multiple
1906 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1907 * pci_dev.
1908 *
1909 ****************************************************************************/
1910
1911 static int iommu_setup_msi(struct amd_iommu *iommu)
1912 {
1913 int r;
1914
1915 r = pci_enable_msi(iommu->dev);
1916 if (r)
1917 return r;
1918
1919 r = request_threaded_irq(iommu->dev->irq,
1920 amd_iommu_int_handler,
1921 amd_iommu_int_thread,
1922 0, "AMD-Vi",
1923 iommu);
1924
1925 if (r) {
1926 pci_disable_msi(iommu->dev);
1927 return r;
1928 }
1929
1930 iommu->int_enabled = true;
1931
1932 return 0;
1933 }
1934
1935 #define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2)
1936 #define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8)
1937 #define XT_INT_VEC(x) (((x) & 0xFFULL) << 32)
1938 #define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56)
1939
1940 /**
1941 * Setup the IntCapXT registers with interrupt routing information
1942 * based on the PCI MSI capability block registers, accessed via
1943 * MMIO MSI address low/hi and MSI data registers.
1944 */
1945 static void iommu_update_intcapxt(struct amd_iommu *iommu)
1946 {
1947 u64 val;
1948 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET);
1949 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET);
1950 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET);
1951 bool dm = (addr_lo >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
1952 u32 dest = ((addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xFF);
1953
1954 if (x2apic_enabled())
1955 dest |= MSI_ADDR_EXT_DEST_ID(addr_hi);
1956
1957 val = XT_INT_VEC(data & 0xFF) |
1958 XT_INT_DEST_MODE(dm) |
1959 XT_INT_DEST_LO(dest) |
1960 XT_INT_DEST_HI(dest);
1961
1962 /**
1963 * Current IOMMU implemtation uses the same IRQ for all
1964 * 3 IOMMU interrupts.
1965 */
1966 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);
1967 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET);
1968 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET);
1969 }
1970
1971 static void _irq_notifier_notify(struct irq_affinity_notify *notify,
1972 const cpumask_t *mask)
1973 {
1974 struct amd_iommu *iommu;
1975
1976 for_each_iommu(iommu) {
1977 if (iommu->dev->irq == notify->irq) {
1978 iommu_update_intcapxt(iommu);
1979 break;
1980 }
1981 }
1982 }
1983
1984 static void _irq_notifier_release(struct kref *ref)
1985 {
1986 }
1987
1988 static int iommu_init_intcapxt(struct amd_iommu *iommu)
1989 {
1990 int ret;
1991 struct irq_affinity_notify *notify = &iommu->intcapxt_notify;
1992
1993 /**
1994 * IntCapXT requires XTSup=1 and MsiCapMmioSup=1,
1995 * which can be inferred from amd_iommu_xt_mode.
1996 */
1997 if (amd_iommu_xt_mode != IRQ_REMAP_X2APIC_MODE)
1998 return 0;
1999
2000 /**
2001 * Also, we need to setup notifier to update the IntCapXT registers
2002 * whenever the irq affinity is changed from user-space.
2003 */
2004 notify->irq = iommu->dev->irq;
2005 notify->notify = _irq_notifier_notify,
2006 notify->release = _irq_notifier_release,
2007 ret = irq_set_affinity_notifier(iommu->dev->irq, notify);
2008 if (ret) {
2009 pr_err("Failed to register irq affinity notifier (devid=%#x, irq %d)\n",
2010 iommu->devid, iommu->dev->irq);
2011 return ret;
2012 }
2013
2014 iommu_update_intcapxt(iommu);
2015 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN);
2016 return ret;
2017 }
2018
2019 static int iommu_init_msi(struct amd_iommu *iommu)
2020 {
2021 int ret;
2022
2023 if (iommu->int_enabled)
2024 goto enable_faults;
2025
2026 if (iommu->dev->msi_cap)
2027 ret = iommu_setup_msi(iommu);
2028 else
2029 ret = -ENODEV;
2030
2031 if (ret)
2032 return ret;
2033
2034 enable_faults:
2035 ret = iommu_init_intcapxt(iommu);
2036 if (ret)
2037 return ret;
2038
2039 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
2040
2041 if (iommu->ppr_log != NULL)
2042 iommu_feature_enable(iommu, CONTROL_PPRINT_EN);
2043
2044 iommu_ga_log_enable(iommu);
2045
2046 return 0;
2047 }
2048
2049 /****************************************************************************
2050 *
2051 * The next functions belong to the third pass of parsing the ACPI
2052 * table. In this last pass the memory mapping requirements are
2053 * gathered (like exclusion and unity mapping ranges).
2054 *
2055 ****************************************************************************/
2056
2057 static void __init free_unity_maps(void)
2058 {
2059 struct unity_map_entry *entry, *next;
2060
2061 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
2062 list_del(&entry->list);
2063 kfree(entry);
2064 }
2065 }
2066
2067 /* called when we find an exclusion range definition in ACPI */
2068 static int __init init_exclusion_range(struct ivmd_header *m)
2069 {
2070 int i;
2071
2072 switch (m->type) {
2073 case ACPI_IVMD_TYPE:
2074 set_device_exclusion_range(m->devid, m);
2075 break;
2076 case ACPI_IVMD_TYPE_ALL:
2077 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2078 set_device_exclusion_range(i, m);
2079 break;
2080 case ACPI_IVMD_TYPE_RANGE:
2081 for (i = m->devid; i <= m->aux; ++i)
2082 set_device_exclusion_range(i, m);
2083 break;
2084 default:
2085 break;
2086 }
2087
2088 return 0;
2089 }
2090
2091 /* called for unity map ACPI definition */
2092 static int __init init_unity_map_range(struct ivmd_header *m)
2093 {
2094 struct unity_map_entry *e = NULL;
2095 char *s;
2096
2097 e = kzalloc(sizeof(*e), GFP_KERNEL);
2098 if (e == NULL)
2099 return -ENOMEM;
2100
2101 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2102 init_exclusion_range(m);
2103
2104 switch (m->type) {
2105 default:
2106 kfree(e);
2107 return 0;
2108 case ACPI_IVMD_TYPE:
2109 s = "IVMD_TYPEi\t\t\t";
2110 e->devid_start = e->devid_end = m->devid;
2111 break;
2112 case ACPI_IVMD_TYPE_ALL:
2113 s = "IVMD_TYPE_ALL\t\t";
2114 e->devid_start = 0;
2115 e->devid_end = amd_iommu_last_bdf;
2116 break;
2117 case ACPI_IVMD_TYPE_RANGE:
2118 s = "IVMD_TYPE_RANGE\t\t";
2119 e->devid_start = m->devid;
2120 e->devid_end = m->aux;
2121 break;
2122 }
2123 e->address_start = PAGE_ALIGN(m->range_start);
2124 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2125 e->prot = m->flags >> 1;
2126
2127 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2128 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2129 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2130 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2131 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2132 e->address_start, e->address_end, m->flags);
2133
2134 list_add_tail(&e->list, &amd_iommu_unity_map);
2135
2136 return 0;
2137 }
2138
2139 /* iterates over all memory definitions we find in the ACPI table */
2140 static int __init init_memory_definitions(struct acpi_table_header *table)
2141 {
2142 u8 *p = (u8 *)table, *end = (u8 *)table;
2143 struct ivmd_header *m;
2144
2145 end += table->length;
2146 p += IVRS_HEADER_LENGTH;
2147
2148 while (p < end) {
2149 m = (struct ivmd_header *)p;
2150 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE))
2151 init_unity_map_range(m);
2152
2153 p += m->length;
2154 }
2155
2156 return 0;
2157 }
2158
2159 /*
2160 * Init the device table to not allow DMA access for devices
2161 */
2162 static void init_device_table_dma(void)
2163 {
2164 u32 devid;
2165
2166 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2167 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2168 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2169 }
2170 }
2171
2172 static void __init uninit_device_table_dma(void)
2173 {
2174 u32 devid;
2175
2176 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2177 amd_iommu_dev_table[devid].data[0] = 0ULL;
2178 amd_iommu_dev_table[devid].data[1] = 0ULL;
2179 }
2180 }
2181
2182 static void init_device_table(void)
2183 {
2184 u32 devid;
2185
2186 if (!amd_iommu_irq_remap)
2187 return;
2188
2189 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2190 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2191 }
2192
2193 static void iommu_init_flags(struct amd_iommu *iommu)
2194 {
2195 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2196 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2197 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2198
2199 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2200 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2201 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2202
2203 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2204 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2205 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2206
2207 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2208 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2209 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2210
2211 /*
2212 * make IOMMU memory accesses cache coherent
2213 */
2214 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2215
2216 /* Set IOTLB invalidation timeout to 1s */
2217 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2218 }
2219
2220 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2221 {
2222 int i, j;
2223 u32 ioc_feature_control;
2224 struct pci_dev *pdev = iommu->root_pdev;
2225
2226 /* RD890 BIOSes may not have completely reconfigured the iommu */
2227 if (!is_rd890_iommu(iommu->dev) || !pdev)
2228 return;
2229
2230 /*
2231 * First, we need to ensure that the iommu is enabled. This is
2232 * controlled by a register in the northbridge
2233 */
2234
2235 /* Select Northbridge indirect register 0x75 and enable writing */
2236 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2237 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2238
2239 /* Enable the iommu */
2240 if (!(ioc_feature_control & 0x1))
2241 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2242
2243 /* Restore the iommu BAR */
2244 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2245 iommu->stored_addr_lo);
2246 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2247 iommu->stored_addr_hi);
2248
2249 /* Restore the l1 indirect regs for each of the 6 l1s */
2250 for (i = 0; i < 6; i++)
2251 for (j = 0; j < 0x12; j++)
2252 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2253
2254 /* Restore the l2 indirect regs */
2255 for (i = 0; i < 0x83; i++)
2256 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2257
2258 /* Lock PCI setup registers */
2259 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2260 iommu->stored_addr_lo | 1);
2261 }
2262
2263 static void iommu_enable_ga(struct amd_iommu *iommu)
2264 {
2265 #ifdef CONFIG_IRQ_REMAP
2266 switch (amd_iommu_guest_ir) {
2267 case AMD_IOMMU_GUEST_IR_VAPIC:
2268 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2269 /* Fall through */
2270 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2271 iommu_feature_enable(iommu, CONTROL_GA_EN);
2272 iommu->irte_ops = &irte_128_ops;
2273 break;
2274 default:
2275 iommu->irte_ops = &irte_32_ops;
2276 break;
2277 }
2278 #endif
2279 }
2280
2281 static void early_enable_iommu(struct amd_iommu *iommu)
2282 {
2283 iommu_disable(iommu);
2284 iommu_init_flags(iommu);
2285 iommu_set_device_table(iommu);
2286 iommu_enable_command_buffer(iommu);
2287 iommu_enable_event_buffer(iommu);
2288 iommu_set_exclusion_range(iommu);
2289 iommu_enable_ga(iommu);
2290 iommu_enable_xt(iommu);
2291 iommu_enable(iommu);
2292 iommu_flush_all_caches(iommu);
2293 }
2294
2295 /*
2296 * This function finally enables all IOMMUs found in the system after
2297 * they have been initialized.
2298 *
2299 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2300 * the old content of device table entries. Not this case or copy failed,
2301 * just continue as normal kernel does.
2302 */
2303 static void early_enable_iommus(void)
2304 {
2305 struct amd_iommu *iommu;
2306
2307
2308 if (!copy_device_table()) {
2309 /*
2310 * If come here because of failure in copying device table from old
2311 * kernel with all IOMMUs enabled, print error message and try to
2312 * free allocated old_dev_tbl_cpy.
2313 */
2314 if (amd_iommu_pre_enabled)
2315 pr_err("Failed to copy DEV table from previous kernel.\n");
2316 if (old_dev_tbl_cpy != NULL)
2317 free_pages((unsigned long)old_dev_tbl_cpy,
2318 get_order(dev_table_size));
2319
2320 for_each_iommu(iommu) {
2321 clear_translation_pre_enabled(iommu);
2322 early_enable_iommu(iommu);
2323 }
2324 } else {
2325 pr_info("Copied DEV table from previous kernel.\n");
2326 free_pages((unsigned long)amd_iommu_dev_table,
2327 get_order(dev_table_size));
2328 amd_iommu_dev_table = old_dev_tbl_cpy;
2329 for_each_iommu(iommu) {
2330 iommu_disable_command_buffer(iommu);
2331 iommu_disable_event_buffer(iommu);
2332 iommu_enable_command_buffer(iommu);
2333 iommu_enable_event_buffer(iommu);
2334 iommu_enable_ga(iommu);
2335 iommu_enable_xt(iommu);
2336 iommu_set_device_table(iommu);
2337 iommu_flush_all_caches(iommu);
2338 }
2339 }
2340
2341 #ifdef CONFIG_IRQ_REMAP
2342 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2343 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2344 #endif
2345 }
2346
2347 static void enable_iommus_v2(void)
2348 {
2349 struct amd_iommu *iommu;
2350
2351 for_each_iommu(iommu) {
2352 iommu_enable_ppr_log(iommu);
2353 iommu_enable_gt(iommu);
2354 }
2355 }
2356
2357 static void enable_iommus(void)
2358 {
2359 early_enable_iommus();
2360
2361 enable_iommus_v2();
2362 }
2363
2364 static void disable_iommus(void)
2365 {
2366 struct amd_iommu *iommu;
2367
2368 for_each_iommu(iommu)
2369 iommu_disable(iommu);
2370
2371 #ifdef CONFIG_IRQ_REMAP
2372 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2373 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2374 #endif
2375 }
2376
2377 /*
2378 * Suspend/Resume support
2379 * disable suspend until real resume implemented
2380 */
2381
2382 static void amd_iommu_resume(void)
2383 {
2384 struct amd_iommu *iommu;
2385
2386 for_each_iommu(iommu)
2387 iommu_apply_resume_quirks(iommu);
2388
2389 /* re-load the hardware */
2390 enable_iommus();
2391
2392 amd_iommu_enable_interrupts();
2393 }
2394
2395 static int amd_iommu_suspend(void)
2396 {
2397 /* disable IOMMUs to go out of the way for BIOS */
2398 disable_iommus();
2399
2400 return 0;
2401 }
2402
2403 static struct syscore_ops amd_iommu_syscore_ops = {
2404 .suspend = amd_iommu_suspend,
2405 .resume = amd_iommu_resume,
2406 };
2407
2408 static void __init free_iommu_resources(void)
2409 {
2410 kmemleak_free(irq_lookup_table);
2411 free_pages((unsigned long)irq_lookup_table,
2412 get_order(rlookup_table_size));
2413 irq_lookup_table = NULL;
2414
2415 kmem_cache_destroy(amd_iommu_irq_cache);
2416 amd_iommu_irq_cache = NULL;
2417
2418 free_pages((unsigned long)amd_iommu_rlookup_table,
2419 get_order(rlookup_table_size));
2420 amd_iommu_rlookup_table = NULL;
2421
2422 free_pages((unsigned long)amd_iommu_alias_table,
2423 get_order(alias_table_size));
2424 amd_iommu_alias_table = NULL;
2425
2426 free_pages((unsigned long)amd_iommu_dev_table,
2427 get_order(dev_table_size));
2428 amd_iommu_dev_table = NULL;
2429
2430 free_iommu_all();
2431 }
2432
2433 /* SB IOAPIC is always on this device in AMD systems */
2434 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2435
2436 static bool __init check_ioapic_information(void)
2437 {
2438 const char *fw_bug = FW_BUG;
2439 bool ret, has_sb_ioapic;
2440 int idx;
2441
2442 has_sb_ioapic = false;
2443 ret = false;
2444
2445 /*
2446 * If we have map overrides on the kernel command line the
2447 * messages in this function might not describe firmware bugs
2448 * anymore - so be careful
2449 */
2450 if (cmdline_maps)
2451 fw_bug = "";
2452
2453 for (idx = 0; idx < nr_ioapics; idx++) {
2454 int devid, id = mpc_ioapic_id(idx);
2455
2456 devid = get_ioapic_devid(id);
2457 if (devid < 0) {
2458 pr_err("%s: IOAPIC[%d] not in IVRS table\n",
2459 fw_bug, id);
2460 ret = false;
2461 } else if (devid == IOAPIC_SB_DEVID) {
2462 has_sb_ioapic = true;
2463 ret = true;
2464 }
2465 }
2466
2467 if (!has_sb_ioapic) {
2468 /*
2469 * We expect the SB IOAPIC to be listed in the IVRS
2470 * table. The system timer is connected to the SB IOAPIC
2471 * and if we don't have it in the list the system will
2472 * panic at boot time. This situation usually happens
2473 * when the BIOS is buggy and provides us the wrong
2474 * device id for the IOAPIC in the system.
2475 */
2476 pr_err("%s: No southbridge IOAPIC found\n", fw_bug);
2477 }
2478
2479 if (!ret)
2480 pr_err("Disabling interrupt remapping\n");
2481
2482 return ret;
2483 }
2484
2485 static void __init free_dma_resources(void)
2486 {
2487 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2488 get_order(MAX_DOMAIN_ID/8));
2489 amd_iommu_pd_alloc_bitmap = NULL;
2490
2491 free_unity_maps();
2492 }
2493
2494 /*
2495 * This is the hardware init function for AMD IOMMU in the system.
2496 * This function is called either from amd_iommu_init or from the interrupt
2497 * remapping setup code.
2498 *
2499 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2500 * four times:
2501 *
2502 * 1 pass) Discover the most comprehensive IVHD type to use.
2503 *
2504 * 2 pass) Find the highest PCI device id the driver has to handle.
2505 * Upon this information the size of the data structures is
2506 * determined that needs to be allocated.
2507 *
2508 * 3 pass) Initialize the data structures just allocated with the
2509 * information in the ACPI table about available AMD IOMMUs
2510 * in the system. It also maps the PCI devices in the
2511 * system to specific IOMMUs
2512 *
2513 * 4 pass) After the basic data structures are allocated and
2514 * initialized we update them with information about memory
2515 * remapping requirements parsed out of the ACPI table in
2516 * this last pass.
2517 *
2518 * After everything is set up the IOMMUs are enabled and the necessary
2519 * hotplug and suspend notifiers are registered.
2520 */
2521 static int __init early_amd_iommu_init(void)
2522 {
2523 struct acpi_table_header *ivrs_base;
2524 acpi_status status;
2525 int i, remap_cache_sz, ret = 0;
2526 u32 pci_id;
2527
2528 if (!amd_iommu_detected)
2529 return -ENODEV;
2530
2531 status = acpi_get_table("IVRS", 0, &ivrs_base);
2532 if (status == AE_NOT_FOUND)
2533 return -ENODEV;
2534 else if (ACPI_FAILURE(status)) {
2535 const char *err = acpi_format_exception(status);
2536 pr_err("IVRS table error: %s\n", err);
2537 return -EINVAL;
2538 }
2539
2540 /*
2541 * Validate checksum here so we don't need to do it when
2542 * we actually parse the table
2543 */
2544 ret = check_ivrs_checksum(ivrs_base);
2545 if (ret)
2546 goto out;
2547
2548 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2549 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2550
2551 /*
2552 * First parse ACPI tables to find the largest Bus/Dev/Func
2553 * we need to handle. Upon this information the shared data
2554 * structures for the IOMMUs in the system will be allocated
2555 */
2556 ret = find_last_devid_acpi(ivrs_base);
2557 if (ret)
2558 goto out;
2559
2560 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2561 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2562 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2563
2564 /* Device table - directly used by all IOMMUs */
2565 ret = -ENOMEM;
2566 amd_iommu_dev_table = (void *)__get_free_pages(
2567 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2568 get_order(dev_table_size));
2569 if (amd_iommu_dev_table == NULL)
2570 goto out;
2571
2572 /*
2573 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2574 * IOMMU see for that device
2575 */
2576 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2577 get_order(alias_table_size));
2578 if (amd_iommu_alias_table == NULL)
2579 goto out;
2580
2581 /* IOMMU rlookup table - find the IOMMU for a specific device */
2582 amd_iommu_rlookup_table = (void *)__get_free_pages(
2583 GFP_KERNEL | __GFP_ZERO,
2584 get_order(rlookup_table_size));
2585 if (amd_iommu_rlookup_table == NULL)
2586 goto out;
2587
2588 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2589 GFP_KERNEL | __GFP_ZERO,
2590 get_order(MAX_DOMAIN_ID/8));
2591 if (amd_iommu_pd_alloc_bitmap == NULL)
2592 goto out;
2593
2594 /*
2595 * let all alias entries point to itself
2596 */
2597 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2598 amd_iommu_alias_table[i] = i;
2599
2600 /*
2601 * never allocate domain 0 because its used as the non-allocated and
2602 * error value placeholder
2603 */
2604 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2605
2606 /*
2607 * now the data structures are allocated and basically initialized
2608 * start the real acpi table scan
2609 */
2610 ret = init_iommu_all(ivrs_base);
2611 if (ret)
2612 goto out;
2613
2614 /* Disable IOMMU if there's Stoney Ridge graphics */
2615 for (i = 0; i < 32; i++) {
2616 pci_id = read_pci_config(0, i, 0, 0);
2617 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2618 pr_info("Disable IOMMU on Stoney Ridge\n");
2619 amd_iommu_disabled = true;
2620 break;
2621 }
2622 }
2623
2624 /* Disable any previously enabled IOMMUs */
2625 if (!is_kdump_kernel() || amd_iommu_disabled)
2626 disable_iommus();
2627
2628 if (amd_iommu_irq_remap)
2629 amd_iommu_irq_remap = check_ioapic_information();
2630
2631 if (amd_iommu_irq_remap) {
2632 /*
2633 * Interrupt remapping enabled, create kmem_cache for the
2634 * remapping tables.
2635 */
2636 ret = -ENOMEM;
2637 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2638 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2639 else
2640 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2641 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2642 remap_cache_sz,
2643 IRQ_TABLE_ALIGNMENT,
2644 0, NULL);
2645 if (!amd_iommu_irq_cache)
2646 goto out;
2647
2648 irq_lookup_table = (void *)__get_free_pages(
2649 GFP_KERNEL | __GFP_ZERO,
2650 get_order(rlookup_table_size));
2651 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2652 1, GFP_KERNEL);
2653 if (!irq_lookup_table)
2654 goto out;
2655 }
2656
2657 ret = init_memory_definitions(ivrs_base);
2658 if (ret)
2659 goto out;
2660
2661 /* init the device table */
2662 init_device_table();
2663
2664 out:
2665 /* Don't leak any ACPI memory */
2666 acpi_put_table(ivrs_base);
2667 ivrs_base = NULL;
2668
2669 return ret;
2670 }
2671
2672 static int amd_iommu_enable_interrupts(void)
2673 {
2674 struct amd_iommu *iommu;
2675 int ret = 0;
2676
2677 for_each_iommu(iommu) {
2678 ret = iommu_init_msi(iommu);
2679 if (ret)
2680 goto out;
2681 }
2682
2683 out:
2684 return ret;
2685 }
2686
2687 static bool detect_ivrs(void)
2688 {
2689 struct acpi_table_header *ivrs_base;
2690 acpi_status status;
2691
2692 status = acpi_get_table("IVRS", 0, &ivrs_base);
2693 if (status == AE_NOT_FOUND)
2694 return false;
2695 else if (ACPI_FAILURE(status)) {
2696 const char *err = acpi_format_exception(status);
2697 pr_err("IVRS table error: %s\n", err);
2698 return false;
2699 }
2700
2701 acpi_put_table(ivrs_base);
2702
2703 /* Make sure ACS will be enabled during PCI probe */
2704 pci_request_acs();
2705
2706 return true;
2707 }
2708
2709 /****************************************************************************
2710 *
2711 * AMD IOMMU Initialization State Machine
2712 *
2713 ****************************************************************************/
2714
2715 static int __init state_next(void)
2716 {
2717 int ret = 0;
2718
2719 switch (init_state) {
2720 case IOMMU_START_STATE:
2721 if (!detect_ivrs()) {
2722 init_state = IOMMU_NOT_FOUND;
2723 ret = -ENODEV;
2724 } else {
2725 init_state = IOMMU_IVRS_DETECTED;
2726 }
2727 break;
2728 case IOMMU_IVRS_DETECTED:
2729 ret = early_amd_iommu_init();
2730 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2731 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2732 pr_info("AMD IOMMU disabled\n");
2733 init_state = IOMMU_CMDLINE_DISABLED;
2734 ret = -EINVAL;
2735 }
2736 break;
2737 case IOMMU_ACPI_FINISHED:
2738 early_enable_iommus();
2739 x86_platform.iommu_shutdown = disable_iommus;
2740 init_state = IOMMU_ENABLED;
2741 break;
2742 case IOMMU_ENABLED:
2743 register_syscore_ops(&amd_iommu_syscore_ops);
2744 ret = amd_iommu_init_pci();
2745 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2746 enable_iommus_v2();
2747 break;
2748 case IOMMU_PCI_INIT:
2749 ret = amd_iommu_enable_interrupts();
2750 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2751 break;
2752 case IOMMU_INTERRUPTS_EN:
2753 ret = amd_iommu_init_dma_ops();
2754 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2755 break;
2756 case IOMMU_DMA_OPS:
2757 init_state = IOMMU_INITIALIZED;
2758 break;
2759 case IOMMU_INITIALIZED:
2760 /* Nothing to do */
2761 break;
2762 case IOMMU_NOT_FOUND:
2763 case IOMMU_INIT_ERROR:
2764 case IOMMU_CMDLINE_DISABLED:
2765 /* Error states => do nothing */
2766 ret = -EINVAL;
2767 break;
2768 default:
2769 /* Unknown state */
2770 BUG();
2771 }
2772
2773 if (ret) {
2774 free_dma_resources();
2775 if (!irq_remapping_enabled) {
2776 disable_iommus();
2777 free_iommu_resources();
2778 } else {
2779 struct amd_iommu *iommu;
2780
2781 uninit_device_table_dma();
2782 for_each_iommu(iommu)
2783 iommu_flush_all_caches(iommu);
2784 }
2785 }
2786 return ret;
2787 }
2788
2789 static int __init iommu_go_to_state(enum iommu_init_state state)
2790 {
2791 int ret = -EINVAL;
2792
2793 while (init_state != state) {
2794 if (init_state == IOMMU_NOT_FOUND ||
2795 init_state == IOMMU_INIT_ERROR ||
2796 init_state == IOMMU_CMDLINE_DISABLED)
2797 break;
2798 ret = state_next();
2799 }
2800
2801 return ret;
2802 }
2803
2804 #ifdef CONFIG_IRQ_REMAP
2805 int __init amd_iommu_prepare(void)
2806 {
2807 int ret;
2808
2809 amd_iommu_irq_remap = true;
2810
2811 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2812 if (ret)
2813 return ret;
2814 return amd_iommu_irq_remap ? 0 : -ENODEV;
2815 }
2816
2817 int __init amd_iommu_enable(void)
2818 {
2819 int ret;
2820
2821 ret = iommu_go_to_state(IOMMU_ENABLED);
2822 if (ret)
2823 return ret;
2824
2825 irq_remapping_enabled = 1;
2826 return amd_iommu_xt_mode;
2827 }
2828
2829 void amd_iommu_disable(void)
2830 {
2831 amd_iommu_suspend();
2832 }
2833
2834 int amd_iommu_reenable(int mode)
2835 {
2836 amd_iommu_resume();
2837
2838 return 0;
2839 }
2840
2841 int __init amd_iommu_enable_faulting(void)
2842 {
2843 /* We enable MSI later when PCI is initialized */
2844 return 0;
2845 }
2846 #endif
2847
2848 /*
2849 * This is the core init function for AMD IOMMU hardware in the system.
2850 * This function is called from the generic x86 DMA layer initialization
2851 * code.
2852 */
2853 static int __init amd_iommu_init(void)
2854 {
2855 struct amd_iommu *iommu;
2856 int ret;
2857
2858 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2859 #ifdef CONFIG_GART_IOMMU
2860 if (ret && list_empty(&amd_iommu_list)) {
2861 /*
2862 * We failed to initialize the AMD IOMMU - try fallback
2863 * to GART if possible.
2864 */
2865 gart_iommu_init();
2866 }
2867 #endif
2868
2869 for_each_iommu(iommu)
2870 amd_iommu_debugfs_setup(iommu);
2871
2872 return ret;
2873 }
2874
2875 static bool amd_iommu_sme_check(void)
2876 {
2877 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2878 return true;
2879
2880 /* For Fam17h, a specific level of support is required */
2881 if (boot_cpu_data.microcode >= 0x08001205)
2882 return true;
2883
2884 if ((boot_cpu_data.microcode >= 0x08001126) &&
2885 (boot_cpu_data.microcode <= 0x080011ff))
2886 return true;
2887
2888 pr_notice("IOMMU not currently supported when SME is active\n");
2889
2890 return false;
2891 }
2892
2893 /****************************************************************************
2894 *
2895 * Early detect code. This code runs at IOMMU detection time in the DMA
2896 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2897 * IOMMUs
2898 *
2899 ****************************************************************************/
2900 int __init amd_iommu_detect(void)
2901 {
2902 int ret;
2903
2904 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2905 return -ENODEV;
2906
2907 if (!amd_iommu_sme_check())
2908 return -ENODEV;
2909
2910 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2911 if (ret)
2912 return ret;
2913
2914 amd_iommu_detected = true;
2915 iommu_detected = 1;
2916 x86_init.iommu.iommu_init = amd_iommu_init;
2917
2918 return 1;
2919 }
2920
2921 /****************************************************************************
2922 *
2923 * Parsing functions for the AMD IOMMU specific kernel command line
2924 * options.
2925 *
2926 ****************************************************************************/
2927
2928 static int __init parse_amd_iommu_dump(char *str)
2929 {
2930 amd_iommu_dump = true;
2931
2932 return 1;
2933 }
2934
2935 static int __init parse_amd_iommu_intr(char *str)
2936 {
2937 for (; *str; ++str) {
2938 if (strncmp(str, "legacy", 6) == 0) {
2939 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
2940 break;
2941 }
2942 if (strncmp(str, "vapic", 5) == 0) {
2943 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2944 break;
2945 }
2946 }
2947 return 1;
2948 }
2949
2950 static int __init parse_amd_iommu_options(char *str)
2951 {
2952 for (; *str; ++str) {
2953 if (strncmp(str, "fullflush", 9) == 0)
2954 amd_iommu_unmap_flush = true;
2955 if (strncmp(str, "off", 3) == 0)
2956 amd_iommu_disabled = true;
2957 if (strncmp(str, "force_isolation", 15) == 0)
2958 amd_iommu_force_isolation = true;
2959 }
2960
2961 return 1;
2962 }
2963
2964 static int __init parse_ivrs_ioapic(char *str)
2965 {
2966 unsigned int bus, dev, fn;
2967 int ret, id, i;
2968 u16 devid;
2969
2970 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2971
2972 if (ret != 4) {
2973 pr_err("Invalid command line: ivrs_ioapic%s\n", str);
2974 return 1;
2975 }
2976
2977 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2978 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2979 str);
2980 return 1;
2981 }
2982
2983 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2984
2985 cmdline_maps = true;
2986 i = early_ioapic_map_size++;
2987 early_ioapic_map[i].id = id;
2988 early_ioapic_map[i].devid = devid;
2989 early_ioapic_map[i].cmd_line = true;
2990
2991 return 1;
2992 }
2993
2994 static int __init parse_ivrs_hpet(char *str)
2995 {
2996 unsigned int bus, dev, fn;
2997 int ret, id, i;
2998 u16 devid;
2999
3000 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
3001
3002 if (ret != 4) {
3003 pr_err("Invalid command line: ivrs_hpet%s\n", str);
3004 return 1;
3005 }
3006
3007 if (early_hpet_map_size == EARLY_MAP_SIZE) {
3008 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n",
3009 str);
3010 return 1;
3011 }
3012
3013 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3014
3015 cmdline_maps = true;
3016 i = early_hpet_map_size++;
3017 early_hpet_map[i].id = id;
3018 early_hpet_map[i].devid = devid;
3019 early_hpet_map[i].cmd_line = true;
3020
3021 return 1;
3022 }
3023
3024 static int __init parse_ivrs_acpihid(char *str)
3025 {
3026 u32 bus, dev, fn;
3027 char *hid, *uid, *p;
3028 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
3029 int ret, i;
3030
3031 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
3032 if (ret != 4) {
3033 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str);
3034 return 1;
3035 }
3036
3037 p = acpiid;
3038 hid = strsep(&p, ":");
3039 uid = p;
3040
3041 if (!hid || !(*hid) || !uid) {
3042 pr_err("Invalid command line: hid or uid\n");
3043 return 1;
3044 }
3045
3046 i = early_acpihid_map_size++;
3047 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
3048 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
3049 early_acpihid_map[i].devid =
3050 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3051 early_acpihid_map[i].cmd_line = true;
3052
3053 return 1;
3054 }
3055
3056 __setup("amd_iommu_dump", parse_amd_iommu_dump);
3057 __setup("amd_iommu=", parse_amd_iommu_options);
3058 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
3059 __setup("ivrs_ioapic", parse_ivrs_ioapic);
3060 __setup("ivrs_hpet", parse_ivrs_hpet);
3061 __setup("ivrs_acpihid", parse_ivrs_acpihid);
3062
3063 IOMMU_INIT_FINISH(amd_iommu_detect,
3064 gart_iommu_hole_init,
3065 NULL,
3066 NULL);
3067
3068 bool amd_iommu_v2_supported(void)
3069 {
3070 return amd_iommu_v2_present;
3071 }
3072 EXPORT_SYMBOL(amd_iommu_v2_supported);
3073
3074 struct amd_iommu *get_amd_iommu(unsigned int idx)
3075 {
3076 unsigned int i = 0;
3077 struct amd_iommu *iommu;
3078
3079 for_each_iommu(iommu)
3080 if (i++ == idx)
3081 return iommu;
3082 return NULL;
3083 }
3084 EXPORT_SYMBOL(get_amd_iommu);
3085
3086 /****************************************************************************
3087 *
3088 * IOMMU EFR Performance Counter support functionality. This code allows
3089 * access to the IOMMU PC functionality.
3090 *
3091 ****************************************************************************/
3092
3093 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
3094 {
3095 struct amd_iommu *iommu = get_amd_iommu(idx);
3096
3097 if (iommu)
3098 return iommu->max_banks;
3099
3100 return 0;
3101 }
3102 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
3103
3104 bool amd_iommu_pc_supported(void)
3105 {
3106 return amd_iommu_pc_present;
3107 }
3108 EXPORT_SYMBOL(amd_iommu_pc_supported);
3109
3110 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
3111 {
3112 struct amd_iommu *iommu = get_amd_iommu(idx);
3113
3114 if (iommu)
3115 return iommu->max_counters;
3116
3117 return 0;
3118 }
3119 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
3120
3121 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
3122 u8 fxn, u64 *value, bool is_write)
3123 {
3124 u32 offset;
3125 u32 max_offset_lim;
3126
3127 /* Make sure the IOMMU PC resource is available */
3128 if (!amd_iommu_pc_present)
3129 return -ENODEV;
3130
3131 /* Check for valid iommu and pc register indexing */
3132 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3133 return -ENODEV;
3134
3135 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3136
3137 /* Limit the offset to the hw defined mmio region aperture */
3138 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3139 (iommu->max_counters << 8) | 0x28);
3140 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3141 (offset > max_offset_lim))
3142 return -EINVAL;
3143
3144 if (is_write) {
3145 u64 val = *value & GENMASK_ULL(47, 0);
3146
3147 writel((u32)val, iommu->mmio_base + offset);
3148 writel((val >> 32), iommu->mmio_base + offset + 4);
3149 } else {
3150 *value = readl(iommu->mmio_base + offset + 4);
3151 *value <<= 32;
3152 *value |= readl(iommu->mmio_base + offset);
3153 *value &= GENMASK_ULL(47, 0);
3154 }
3155
3156 return 0;
3157 }
3158
3159 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3160 {
3161 if (!iommu)
3162 return -EINVAL;
3163
3164 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3165 }
3166 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3167
3168 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3169 {
3170 if (!iommu)
3171 return -EINVAL;
3172
3173 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3174 }
3175 EXPORT_SYMBOL(amd_iommu_pc_set_reg);
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