drivers/iommu/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <jroedel@suse.de>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/mutex.h>
  25 #include <linux/msi.h>
  26 #include <linux/list.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29 #include <linux/irqreturn.h>
  30
  31 /*
  32  * Maximum number of IOMMUs supported
  33  */
  34 #define MAX_IOMMUS      32
  35
  36 /*
  37  * some size calculation constants
  38  */
  39 #define DEV_TABLE_ENTRY_SIZE            32
  40 #define ALIAS_TABLE_ENTRY_SIZE          2
  41 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  42
  43 /* Capability offsets used by the driver */
  44 #define MMIO_CAP_HDR_OFFSET     0x00
  45 #define MMIO_RANGE_OFFSET       0x0c
  46 #define MMIO_MISC_OFFSET        0x10
  47
  48 /* Masks, shifts and macros to parse the device range capability */
  49 #define MMIO_RANGE_LD_MASK      0xff000000
  50 #define MMIO_RANGE_FD_MASK      0x00ff0000
  51 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  52 #define MMIO_RANGE_LD_SHIFT     24
  53 #define MMIO_RANGE_FD_SHIFT     16
  54 #define MMIO_RANGE_BUS_SHIFT    8
  55 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  56 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  59
  60 /* Flag masks for the AMD IOMMU exclusion range */
  61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  62 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  63
  64 /* Used offsets into the MMIO space */
  65 #define MMIO_DEV_TABLE_OFFSET   0x0000
  66 #define MMIO_CMD_BUF_OFFSET     0x0008
  67 #define MMIO_EVT_BUF_OFFSET     0x0010
  68 #define MMIO_CONTROL_OFFSET     0x0018
  69 #define MMIO_EXCL_BASE_OFFSET   0x0020
  70 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  71 #define MMIO_EXT_FEATURES       0x0030
  72 #define MMIO_PPR_LOG_OFFSET     0x0038
  73 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
  74 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
  75 #define MMIO_CMD_HEAD_OFFSET    0x2000
  76 #define MMIO_CMD_TAIL_OFFSET    0x2008
  77 #define MMIO_EVT_HEAD_OFFSET    0x2010
  78 #define MMIO_EVT_TAIL_OFFSET    0x2018
  79 #define MMIO_STATUS_OFFSET      0x2020
  80 #define MMIO_PPR_HEAD_OFFSET    0x2030
  81 #define MMIO_PPR_TAIL_OFFSET    0x2038
  82 #define MMIO_GA_HEAD_OFFSET     0x2040
  83 #define MMIO_GA_TAIL_OFFSET     0x2048
  84 #define MMIO_CNTR_CONF_OFFSET   0x4000
  85 #define MMIO_CNTR_REG_OFFSET    0x40000
  86 #define MMIO_REG_END_OFFSET     0x80000
  87
  88
  89
  90 /* Extended Feature Bits */
  91 #define FEATURE_PREFETCH        (1ULL<<0)
  92 #define FEATURE_PPR             (1ULL<<1)
  93 #define FEATURE_X2APIC          (1ULL<<2)
  94 #define FEATURE_NX              (1ULL<<3)
  95 #define FEATURE_GT              (1ULL<<4)
  96 #define FEATURE_IA              (1ULL<<6)
  97 #define FEATURE_GA              (1ULL<<7)
  98 #define FEATURE_HE              (1ULL<<8)
  99 #define FEATURE_PC              (1ULL<<9)
 100 #define FEATURE_GAM_VAPIC       (1ULL<<21)
 101 #define FEATURE_EPHSUP          (1ULL<<50)
 102
 103 #define FEATURE_PASID_SHIFT     32
 104 #define FEATURE_PASID_MASK      (0x1fULL << FEATURE_PASID_SHIFT)
 105
 106 #define FEATURE_GLXVAL_SHIFT    14
 107 #define FEATURE_GLXVAL_MASK     (0x03ULL << FEATURE_GLXVAL_SHIFT)
 108
 109 /* Note:
 110  * The current driver only support 16-bit PASID.
 111  * Currently, hardware only implement upto 16-bit PASID
 112  * even though the spec says it could have upto 20 bits.
 113  */
 114 #define PASID_MASK              0x0000ffff
 115
 116 /* MMIO status bits */
 117 #define MMIO_STATUS_EVT_INT_MASK        (1 << 1)
 118 #define MMIO_STATUS_COM_WAIT_INT_MASK   (1 << 2)
 119 #define MMIO_STATUS_PPR_INT_MASK        (1 << 6)
 120 #define MMIO_STATUS_GALOG_RUN_MASK      (1 << 8)
 121 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
 122 #define MMIO_STATUS_GALOG_INT_MASK      (1 << 10)
 123
 124 /* event logging constants */
 125 #define EVENT_ENTRY_SIZE        0x10
 126 #define EVENT_TYPE_SHIFT        28
 127 #define EVENT_TYPE_MASK         0xf
 128 #define EVENT_TYPE_ILL_DEV      0x1
 129 #define EVENT_TYPE_IO_FAULT     0x2
 130 #define EVENT_TYPE_DEV_TAB_ERR  0x3
 131 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
 132 #define EVENT_TYPE_ILL_CMD      0x5
 133 #define EVENT_TYPE_CMD_HARD_ERR 0x6
 134 #define EVENT_TYPE_IOTLB_INV_TO 0x7
 135 #define EVENT_TYPE_INV_DEV_REQ  0x8
 136 #define EVENT_TYPE_INV_PPR_REQ  0x9
 137 #define EVENT_DEVID_MASK        0xffff
 138 #define EVENT_DEVID_SHIFT       0
 139 #define EVENT_DOMID_MASK        0xffff
 140 #define EVENT_DOMID_SHIFT       0
 141 #define EVENT_FLAGS_MASK        0xfff
 142 #define EVENT_FLAGS_SHIFT       0x10
 143
 144 /* feature control bits */
 145 #define CONTROL_IOMMU_EN        0x00ULL
 146 #define CONTROL_HT_TUN_EN       0x01ULL
 147 #define CONTROL_EVT_LOG_EN      0x02ULL
 148 #define CONTROL_EVT_INT_EN      0x03ULL
 149 #define CONTROL_COMWAIT_EN      0x04ULL
 150 #define CONTROL_INV_TIMEOUT     0x05ULL
 151 #define CONTROL_PASSPW_EN       0x08ULL
 152 #define CONTROL_RESPASSPW_EN    0x09ULL
 153 #define CONTROL_COHERENT_EN     0x0aULL
 154 #define CONTROL_ISOC_EN         0x0bULL
 155 #define CONTROL_CMDBUF_EN       0x0cULL
 156 #define CONTROL_PPFLOG_EN       0x0dULL
 157 #define CONTROL_PPFINT_EN       0x0eULL
 158 #define CONTROL_PPR_EN          0x0fULL
 159 #define CONTROL_GT_EN           0x10ULL
 160 #define CONTROL_GA_EN           0x11ULL
 161 #define CONTROL_GAM_EN          0x19ULL
 162 #define CONTROL_GALOG_EN        0x1CULL
 163 #define CONTROL_GAINT_EN        0x1DULL
 164 #define CONTROL_XT_EN           0x32ULL
 165
 166 #define CTRL_INV_TO_MASK        (7 << CONTROL_INV_TIMEOUT)
 167 #define CTRL_INV_TO_NONE        0
 168 #define CTRL_INV_TO_1MS         1
 169 #define CTRL_INV_TO_10MS        2
 170 #define CTRL_INV_TO_100MS       3
 171 #define CTRL_INV_TO_1S          4
 172 #define CTRL_INV_TO_10S         5
 173 #define CTRL_INV_TO_100S        6
 174
 175 /* command specific defines */
 176 #define CMD_COMPL_WAIT          0x01
 177 #define CMD_INV_DEV_ENTRY       0x02
 178 #define CMD_INV_IOMMU_PAGES     0x03
 179 #define CMD_INV_IOTLB_PAGES     0x04
 180 #define CMD_INV_IRT             0x05
 181 #define CMD_COMPLETE_PPR        0x07
 182 #define CMD_INV_ALL             0x08
 183
 184 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 185 #define CMD_COMPL_WAIT_INT_MASK         0x02
 186 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 187 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 188 #define CMD_INV_IOMMU_PAGES_GN_MASK     0x04
 189
 190 #define PPR_STATUS_MASK                 0xf
 191 #define PPR_STATUS_SHIFT                12
 192
 193 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 194
 195 /* macros and definitions for device table entries */
 196 #define DEV_ENTRY_VALID         0x00
 197 #define DEV_ENTRY_TRANSLATION   0x01
 198 #define DEV_ENTRY_PPR           0x34
 199 #define DEV_ENTRY_IR            0x3d
 200 #define DEV_ENTRY_IW            0x3e
 201 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 202 #define DEV_ENTRY_EX            0x67
 203 #define DEV_ENTRY_SYSMGT1       0x68
 204 #define DEV_ENTRY_SYSMGT2       0x69
 205 #define DEV_ENTRY_IRQ_TBL_EN    0x80
 206 #define DEV_ENTRY_INIT_PASS     0xb8
 207 #define DEV_ENTRY_EINT_PASS     0xb9
 208 #define DEV_ENTRY_NMI_PASS      0xba
 209 #define DEV_ENTRY_LINT0_PASS    0xbe
 210 #define DEV_ENTRY_LINT1_PASS    0xbf
 211 #define DEV_ENTRY_MODE_MASK     0x07
 212 #define DEV_ENTRY_MODE_SHIFT    0x09
 213
 214 #define MAX_DEV_TABLE_ENTRIES   0xffff
 215
 216 /* constants to configure the command buffer */
 217 #define CMD_BUFFER_SIZE    8192
 218 #define CMD_BUFFER_UNINITIALIZED 1
 219 #define CMD_BUFFER_ENTRIES 512
 220 #define MMIO_CMD_SIZE_SHIFT 56
 221 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 222
 223 /* constants for event buffer handling */
 224 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 225 #define EVT_LEN_MASK            (0x9ULL << 56)
 226
 227 /* Constants for PPR Log handling */
 228 #define PPR_LOG_ENTRIES         512
 229 #define PPR_LOG_SIZE_SHIFT      56
 230 #define PPR_LOG_SIZE_512        (0x9ULL << PPR_LOG_SIZE_SHIFT)
 231 #define PPR_ENTRY_SIZE          16
 232 #define PPR_LOG_SIZE            (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
 233
 234 #define PPR_REQ_TYPE(x)         (((x) >> 60) & 0xfULL)
 235 #define PPR_FLAGS(x)            (((x) >> 48) & 0xfffULL)
 236 #define PPR_DEVID(x)            ((x) & 0xffffULL)
 237 #define PPR_TAG(x)              (((x) >> 32) & 0x3ffULL)
 238 #define PPR_PASID1(x)           (((x) >> 16) & 0xffffULL)
 239 #define PPR_PASID2(x)           (((x) >> 42) & 0xfULL)
 240 #define PPR_PASID(x)            ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
 241
 242 #define PPR_REQ_FAULT           0x01
 243
 244 /* Constants for GA Log handling */
 245 #define GA_LOG_ENTRIES          512
 246 #define GA_LOG_SIZE_SHIFT       56
 247 #define GA_LOG_SIZE_512         (0x8ULL << GA_LOG_SIZE_SHIFT)
 248 #define GA_ENTRY_SIZE           8
 249 #define GA_LOG_SIZE             (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
 250
 251 #define GA_TAG(x)               (u32)(x & 0xffffffffULL)
 252 #define GA_DEVID(x)             (u16)(((x) >> 32) & 0xffffULL)
 253 #define GA_REQ_TYPE(x)          (((x) >> 60) & 0xfULL)
 254
 255 #define GA_GUEST_NR             0x1
 256
 257 /* Bit value definition for dte irq remapping fields*/
 258 #define DTE_IRQ_PHYS_ADDR_MASK  (((1ULL << 45)-1) << 6)
 259 #define DTE_IRQ_REMAP_INTCTL_MASK       (0x3ULL << 60)
 260 #define DTE_IRQ_TABLE_LEN_MASK  (0xfULL << 1)
 261 #define DTE_IRQ_REMAP_INTCTL    (2ULL << 60)
 262 #define DTE_IRQ_TABLE_LEN       (8ULL << 1)
 263 #define DTE_IRQ_REMAP_ENABLE    1ULL
 264
 265 #define PAGE_MODE_NONE    0x00
 266 #define PAGE_MODE_1_LEVEL 0x01
 267 #define PAGE_MODE_2_LEVEL 0x02
 268 #define PAGE_MODE_3_LEVEL 0x03
 269 #define PAGE_MODE_4_LEVEL 0x04
 270 #define PAGE_MODE_5_LEVEL 0x05
 271 #define PAGE_MODE_6_LEVEL 0x06
 272 #define PAGE_MODE_7_LEVEL 0x07
 273
 274 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 275 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 276                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 277                                    (0xffffffffffffffffULL))
 278 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 279 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 280 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 281                                  IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW)
 282 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 283
 284 #define PM_MAP_4k               0
 285 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 286 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 287                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 288 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 289
 290 /*
 291  * Returns the page table level to use for a given page size
 292  * Pagesize is expected to be a power-of-two
 293  */
 294 #define PAGE_SIZE_LEVEL(pagesize) \
 295                 ((__ffs(pagesize) - 12) / 9)
 296 /*
 297  * Returns the number of ptes to use for a given page size
 298  * Pagesize is expected to be a power-of-two
 299  */
 300 #define PAGE_SIZE_PTE_COUNT(pagesize) \
 301                 (1ULL << ((__ffs(pagesize) - 12) % 9))
 302
 303 /*
 304  * Aligns a given io-virtual address to a given page size
 305  * Pagesize is expected to be a power-of-two
 306  */
 307 #define PAGE_SIZE_ALIGN(address, pagesize) \
 308                 ((address) & ~((pagesize) - 1))
 309 /*
 310  * Creates an IOMMU PTE for an address and a given pagesize
 311  * The PTE has no permission bits set
 312  * Pagesize is expected to be a power-of-two larger than 4096
 313  */
 314 #define PAGE_SIZE_PTE(address, pagesize)                \
 315                 (((address) | ((pagesize) - 1)) &       \
 316                  (~(pagesize >> 1)) & PM_ADDR_MASK)
 317
 318 /*
 319  * Takes a PTE value with mode=0x07 and returns the page size it maps
 320  */
 321 #define PTE_PAGE_SIZE(pte) \
 322         (1ULL << (1 + ffz(((pte) | 0xfffULL))))
 323
 324 /*
 325  * Takes a page-table level and returns the default page-size for this level
 326  */
 327 #define PTE_LEVEL_PAGE_SIZE(level)                      \
 328         (1ULL << (12 + (9 * (level))))
 329
 330 /*
 331  * Bit value definition for I/O PTE fields
 332  */
 333 #define IOMMU_PTE_PR (1ULL << 0)
 334 #define IOMMU_PTE_U  (1ULL << 59)
 335 #define IOMMU_PTE_FC (1ULL << 60)
 336 #define IOMMU_PTE_IR (1ULL << 61)
 337 #define IOMMU_PTE_IW (1ULL << 62)
 338
 339 /*
 340  * Bit value definition for DTE fields
 341  */
 342 #define DTE_FLAG_V  (1ULL << 0)
 343 #define DTE_FLAG_TV (1ULL << 1)
 344 #define DTE_FLAG_IR (1ULL << 61)
 345 #define DTE_FLAG_IW (1ULL << 62)
 346
 347 #define DTE_FLAG_IOTLB  (1ULL << 32)
 348 #define DTE_FLAG_GV     (1ULL << 55)
 349 #define DTE_FLAG_MASK   (0x3ffULL << 32)
 350 #define DTE_GLX_SHIFT   (56)
 351 #define DTE_GLX_MASK    (3)
 352 #define DEV_DOMID_MASK  0xffffULL
 353
 354 #define DTE_GCR3_VAL_A(x)       (((x) >> 12) & 0x00007ULL)
 355 #define DTE_GCR3_VAL_B(x)       (((x) >> 15) & 0x0ffffULL)
 356 #define DTE_GCR3_VAL_C(x)       (((x) >> 31) & 0xfffffULL)
 357
 358 #define DTE_GCR3_INDEX_A        0
 359 #define DTE_GCR3_INDEX_B        1
 360 #define DTE_GCR3_INDEX_C        1
 361
 362 #define DTE_GCR3_SHIFT_A        58
 363 #define DTE_GCR3_SHIFT_B        16
 364 #define DTE_GCR3_SHIFT_C        43
 365
 366 #define GCR3_VALID              0x01ULL
 367
 368 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 369 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR)
 370 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK))
 371 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 372
 373 #define IOMMU_PROT_MASK 0x03
 374 #define IOMMU_PROT_IR 0x01
 375 #define IOMMU_PROT_IW 0x02
 376
 377 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2)
 378
 379 /* IOMMU capabilities */
 380 #define IOMMU_CAP_IOTLB   24
 381 #define IOMMU_CAP_NPCACHE 26
 382 #define IOMMU_CAP_EFR     27
 383
 384 /* IOMMU Feature Reporting Field (for IVHD type 10h */
 385 #define IOMMU_FEAT_XTSUP_SHIFT  0
 386 #define IOMMU_FEAT_GASUP_SHIFT  6
 387
 388 /* IOMMU Extended Feature Register (EFR) */
 389 #define IOMMU_EFR_XTSUP_SHIFT   2
 390 #define IOMMU_EFR_GASUP_SHIFT   7
 391
 392 #define MAX_DOMAIN_ID 65536
 393
 394 /* Protection domain flags */
 395 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 396 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 397                                               domain for an IOMMU */
 398 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 399                                               translation */
 400 #define PD_IOMMUV2_MASK         (1UL << 3) /* domain has gcr3 table */
 401
 402 extern bool amd_iommu_dump;
 403 #define DUMP_printk(format, arg...)                                     \
 404         do {                                                            \
 405                 if (amd_iommu_dump)                                             \
 406                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 407         } while(0);
 408
 409 /* global flag if IOMMUs cache non-present entries */
 410 extern bool amd_iommu_np_cache;
 411 /* Only true if all IOMMUs support device IOTLBs */
 412 extern bool amd_iommu_iotlb_sup;
 413
 414 #define MAX_IRQS_PER_TABLE      256
 415 #define IRQ_TABLE_ALIGNMENT     128
 416
 417 struct irq_remap_table {
 418         raw_spinlock_t lock;
 419         unsigned min_index;
 420         u32 *table;
 421 };
 422
 423 extern struct irq_remap_table **irq_lookup_table;
 424
 425 /* Interrupt remapping feature used? */
 426 extern bool amd_iommu_irq_remap;
 427
 428 /* kmem_cache to get tables with 128 byte alignement */
 429 extern struct kmem_cache *amd_iommu_irq_cache;
 430
 431 /*
 432  * Make iterating over all IOMMUs easier
 433  */
 434 #define for_each_iommu(iommu) \
 435         list_for_each_entry((iommu), &amd_iommu_list, list)
 436 #define for_each_iommu_safe(iommu, next) \
 437         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 438
 439 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 440 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 441 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 442 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 443 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 444 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 445
 446 /*
 447  * This struct is used to pass information about
 448  * incoming PPR faults around.
 449  */
 450 struct amd_iommu_fault {
 451         u64 address;    /* IO virtual address of the fault*/
 452         u32 pasid;      /* Address space identifier */
 453         u16 device_id;  /* Originating PCI device id */
 454         u16 tag;        /* PPR tag */
 455         u16 flags;      /* Fault flags */
 456
 457 };
 458
 459
 460 struct iommu_domain;
 461 struct irq_domain;
 462 struct amd_irte_ops;
 463
 464 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED      (1 << 0)
 465
 466 /*
 467  * This structure contains generic data for  IOMMU protection domains
 468  * independent of their use.
 469  */
 470 struct protection_domain {
 471         struct list_head list;  /* for list of all protection domains */
 472         struct list_head dev_list; /* List of all devices in this domain */
 473         struct iommu_domain domain; /* generic domain handle used by
 474                                        iommu core code */
 475         spinlock_t lock;        /* mostly used to lock the page table*/
 476         struct mutex api_lock;  /* protect page tables in the iommu-api path */
 477         u16 id;                 /* the domain id written to the device table */
 478         int mode;               /* paging mode (0-6 levels) */
 479         u64 *pt_root;           /* page table root pointer */
 480         int glx;                /* Number of levels for GCR3 table */
 481         u64 *gcr3_tbl;          /* Guest CR3 table */
 482         unsigned long flags;    /* flags to find out type of domain */
 483         bool updated;           /* complete domain flush required */
 484         unsigned dev_cnt;       /* devices assigned to this domain */
 485         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 486 };
 487
 488 /*
 489  * Structure where we save information about one hardware AMD IOMMU in the
 490  * system.
 491  */
 492 struct amd_iommu {
 493         struct list_head list;
 494
 495         /* Index within the IOMMU array */
 496         int index;
 497
 498         /* locks the accesses to the hardware */
 499         raw_spinlock_t lock;
 500
 501         /* Pointer to PCI device of this IOMMU */
 502         struct pci_dev *dev;
 503
 504         /* Cache pdev to root device for resume quirks */
 505         struct pci_dev *root_pdev;
 506
 507         /* physical address of MMIO space */
 508         u64 mmio_phys;
 509
 510         /* physical end address of MMIO space */
 511         u64 mmio_phys_end;
 512
 513         /* virtual address of MMIO space */
 514         u8 __iomem *mmio_base;
 515
 516         /* capabilities of that IOMMU read from ACPI */
 517         u32 cap;
 518
 519         /* flags read from acpi table */
 520         u8 acpi_flags;
 521
 522         /* Extended features */
 523         u64 features;
 524
 525         /* IOMMUv2 */
 526         bool is_iommu_v2;
 527
 528         /* PCI device id of the IOMMU device */
 529         u16 devid;
 530
 531         /*
 532          * Capability pointer. There could be more than one IOMMU per PCI
 533          * device function if there are more than one AMD IOMMU capability
 534          * pointers.
 535          */
 536         u16 cap_ptr;
 537
 538         /* pci domain of this IOMMU */
 539         u16 pci_seg;
 540
 541         /* start of exclusion range of that IOMMU */
 542         u64 exclusion_start;
 543         /* length of exclusion range of that IOMMU */
 544         u64 exclusion_length;
 545
 546         /* command buffer virtual address */
 547         u8 *cmd_buf;
 548         u32 cmd_buf_head;
 549         u32 cmd_buf_tail;
 550
 551         /* event buffer virtual address */
 552         u8 *evt_buf;
 553
 554         /* Base of the PPR log, if present */
 555         u8 *ppr_log;
 556
 557         /* Base of the GA log, if present */
 558         u8 *ga_log;
 559
 560         /* Tail of the GA log, if present */
 561         u8 *ga_log_tail;
 562
 563         /* true if interrupts for this IOMMU are already enabled */
 564         bool int_enabled;
 565
 566         /* if one, we need to send a completion wait command */
 567         bool need_sync;
 568
 569         /* Handle for IOMMU core code */
 570         struct iommu_device iommu;
 571
 572         /*
 573          * We can't rely on the BIOS to restore all values on reinit, so we
 574          * need to stash them
 575          */
 576
 577         /* The iommu BAR */
 578         u32 stored_addr_lo;
 579         u32 stored_addr_hi;
 580
 581         /*
 582          * Each iommu has 6 l1s, each of which is documented as having 0x12
 583          * registers
 584          */
 585         u32 stored_l1[6][0x12];
 586
 587         /* The l2 indirect registers */
 588         u32 stored_l2[0x83];
 589
 590         /* The maximum PC banks and counters/bank (PCSup=1) */
 591         u8 max_banks;
 592         u8 max_counters;
 593 #ifdef CONFIG_IRQ_REMAP
 594         struct irq_domain *ir_domain;
 595         struct irq_domain *msi_domain;
 596
 597         struct amd_irte_ops *irte_ops;
 598 #endif
 599
 600         u32 flags;
 601         volatile u64 __aligned(8) cmd_sem;
 602
 603 #ifdef CONFIG_AMD_IOMMU_DEBUGFS
 604         /* DebugFS Info */
 605         struct dentry *debugfs;
 606 #endif
 607 };
 608
 609 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
 610 {
 611         struct iommu_device *iommu = dev_to_iommu_device(dev);
 612
 613         return container_of(iommu, struct amd_iommu, iommu);
 614 }
 615
 616 #define ACPIHID_UID_LEN 256
 617 #define ACPIHID_HID_LEN 9
 618
 619 struct acpihid_map_entry {
 620         struct list_head list;
 621         u8 uid[ACPIHID_UID_LEN];
 622         u8 hid[ACPIHID_HID_LEN];
 623         u16 devid;
 624         u16 root_devid;
 625         bool cmd_line;
 626         struct iommu_group *group;
 627 };
 628
 629 struct devid_map {
 630         struct list_head list;
 631         u8 id;
 632         u16 devid;
 633         bool cmd_line;
 634 };
 635
 636 /*
 637  * This struct contains device specific data for the IOMMU
 638  */
 639 struct iommu_dev_data {
 640         struct list_head list;            /* For domain->dev_list */
 641         struct llist_node dev_data_list;  /* For global dev_data_list */
 642         struct protection_domain *domain; /* Domain the device is bound to */
 643         u16 devid;                        /* PCI Device ID */
 644         u16 alias;                        /* Alias Device ID */
 645         bool iommu_v2;                    /* Device can make use of IOMMUv2 */
 646         bool passthrough;                 /* Device is identity mapped */
 647         struct {
 648                 bool enabled;
 649                 int qdep;
 650         } ats;                            /* ATS state */
 651         bool pri_tlp;                     /* PASID TLB required for
 652                                              PPR completions */
 653         u32 errata;                       /* Bitmap for errata to apply */
 654         bool use_vapic;                   /* Enable device to use vapic mode */
 655         bool defer_attach;
 656
 657         struct ratelimit_state rs;        /* Ratelimit IOPF messages */
 658 };
 659
 660 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
 661 extern struct list_head ioapic_map;
 662 extern struct list_head hpet_map;
 663 extern struct list_head acpihid_map;
 664
 665 /*
 666  * List with all IOMMUs in the system. This list is not locked because it is
 667  * only written and read at driver initialization or suspend time
 668  */
 669 extern struct list_head amd_iommu_list;
 670
 671 /*
 672  * Array with pointers to each IOMMU struct
 673  * The indices are referenced in the protection domains
 674  */
 675 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 676
 677 /*
 678  * Structure defining one entry in the device table
 679  */
 680 struct dev_table_entry {
 681         u64 data[4];
 682 };
 683
 684 /*
 685  * One entry for unity mappings parsed out of the ACPI table.
 686  */
 687 struct unity_map_entry {
 688         struct list_head list;
 689
 690         /* starting device id this entry is used for (including) */
 691         u16 devid_start;
 692         /* end device id this entry is used for (including) */
 693         u16 devid_end;
 694
 695         /* start address to unity map (including) */
 696         u64 address_start;
 697         /* end address to unity map (including) */
 698         u64 address_end;
 699
 700         /* required protection */
 701         int prot;
 702 };
 703
 704 /*
 705  * List of all unity mappings. It is not locked because as runtime it is only
 706  * read. It is created at ACPI table parsing time.
 707  */
 708 extern struct list_head amd_iommu_unity_map;
 709
 710 /*
 711  * Data structures for device handling
 712  */
 713
 714 /*
 715  * Device table used by hardware. Read and write accesses by software are
 716  * locked with the amd_iommu_pd_table lock.
 717  */
 718 extern struct dev_table_entry *amd_iommu_dev_table;
 719
 720 /*
 721  * Alias table to find requestor ids to device ids. Not locked because only
 722  * read on runtime.
 723  */
 724 extern u16 *amd_iommu_alias_table;
 725
 726 /*
 727  * Reverse lookup table to find the IOMMU which translates a specific device.
 728  */
 729 extern struct amd_iommu **amd_iommu_rlookup_table;
 730
 731 /* size of the dma_ops aperture as power of 2 */
 732 extern unsigned amd_iommu_aperture_order;
 733
 734 /* largest PCI device id we expect translation requests for */
 735 extern u16 amd_iommu_last_bdf;
 736
 737 /* allocation bitmap for domain ids */
 738 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 739
 740 /*
 741  * If true, the addresses will be flushed on unmap time, not when
 742  * they are reused
 743  */
 744 extern bool amd_iommu_unmap_flush;
 745
 746 /* Smallest max PASID supported by any IOMMU in the system */
 747 extern u32 amd_iommu_max_pasid;
 748
 749 extern bool amd_iommu_v2_present;
 750
 751 extern bool amd_iommu_force_isolation;
 752
 753 /* Max levels of glxval supported */
 754 extern int amd_iommu_max_glx_val;
 755
 756 /*
 757  * This function flushes all internal caches of
 758  * the IOMMU used by this driver.
 759  */
 760 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
 761
 762 static inline int get_ioapic_devid(int id)
 763 {
 764         struct devid_map *entry;
 765
 766         list_for_each_entry(entry, &ioapic_map, list) {
 767                 if (entry->id == id)
 768                         return entry->devid;
 769         }
 770
 771         return -EINVAL;
 772 }
 773
 774 static inline int get_hpet_devid(int id)
 775 {
 776         struct devid_map *entry;
 777
 778         list_for_each_entry(entry, &hpet_map, list) {
 779                 if (entry->id == id)
 780                         return entry->devid;
 781         }
 782
 783         return -EINVAL;
 784 }
 785
 786 enum amd_iommu_intr_mode_type {
 787         AMD_IOMMU_GUEST_IR_LEGACY,
 788
 789         /* This mode is not visible to users. It is used when
 790          * we cannot fully enable vAPIC and fallback to only support
 791          * legacy interrupt remapping via 128-bit IRTE.
 792          */
 793         AMD_IOMMU_GUEST_IR_LEGACY_GA,
 794         AMD_IOMMU_GUEST_IR_VAPIC,
 795 };
 796
 797 #define AMD_IOMMU_GUEST_IR_GA(x)        (x == AMD_IOMMU_GUEST_IR_VAPIC || \
 798                                          x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
 799
 800 #define AMD_IOMMU_GUEST_IR_VAPIC(x)     (x == AMD_IOMMU_GUEST_IR_VAPIC)
 801
 802 union irte {
 803         u32 val;
 804         struct {
 805                 u32 valid       : 1,
 806                     no_fault    : 1,
 807                     int_type    : 3,
 808                     rq_eoi      : 1,
 809                     dm          : 1,
 810                     rsvd_1      : 1,
 811                     destination : 8,
 812                     vector      : 8,
 813                     rsvd_2      : 8;
 814         } fields;
 815 };
 816
 817 #define APICID_TO_IRTE_DEST_LO(x)    (x & 0xffffff)
 818 #define APICID_TO_IRTE_DEST_HI(x)    ((x >> 24) & 0xff)
 819
 820 union irte_ga_lo {
 821         u64 val;
 822
 823         /* For int remapping */
 824         struct {
 825                 u64 valid       : 1,
 826                     no_fault    : 1,
 827                     /* ------ */
 828                     int_type    : 3,
 829                     rq_eoi      : 1,
 830                     dm          : 1,
 831                     /* ------ */
 832                     guest_mode  : 1,
 833                     destination : 24,
 834                     ga_tag      : 32;
 835         } fields_remap;
 836
 837         /* For guest vAPIC */
 838         struct {
 839                 u64 valid       : 1,
 840                     no_fault    : 1,
 841                     /* ------ */
 842                     ga_log_intr : 1,
 843                     rsvd1       : 3,
 844                     is_run      : 1,
 845                     /* ------ */
 846                     guest_mode  : 1,
 847                     destination : 24,
 848                     ga_tag      : 32;
 849         } fields_vapic;
 850 };
 851
 852 union irte_ga_hi {
 853         u64 val;
 854         struct {
 855                 u64 vector      : 8,
 856                     rsvd_1      : 4,
 857                     ga_root_ptr : 40,
 858                     rsvd_2      : 4,
 859                     destination : 8;
 860         } fields;
 861 };
 862
 863 struct irte_ga {
 864         union irte_ga_lo lo;
 865         union irte_ga_hi hi;
 866 };
 867
 868 struct irq_2_irte {
 869         u16 devid; /* Device ID for IRTE table */
 870         u16 index; /* Index into IRTE table*/
 871 };
 872
 873 struct amd_ir_data {
 874         u32 cached_ga_tag;
 875         struct irq_2_irte irq_2_irte;
 876         struct msi_msg msi_entry;
 877         void *entry;    /* Pointer to union irte or struct irte_ga */
 878         void *ref;      /* Pointer to the actual irte */
 879 };
 880
 881 struct amd_irte_ops {
 882         void (*prepare)(void *, u32, u32, u8, u32, int);
 883         void (*activate)(void *, u16, u16);
 884         void (*deactivate)(void *, u16, u16);
 885         void (*set_affinity)(void *, u16, u16, u8, u32);
 886         void *(*get)(struct irq_remap_table *, int);
 887         void (*set_allocated)(struct irq_remap_table *, int);
 888         bool (*is_allocated)(struct irq_remap_table *, int);
 889         void (*clear_allocated)(struct irq_remap_table *, int);
 890 };
 891
 892 #ifdef CONFIG_IRQ_REMAP
 893 extern struct amd_irte_ops irte_32_ops;
 894 extern struct amd_irte_ops irte_128_ops;
 895 #endif
 896
 897 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */