2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 #define pr_fmt(fmt) "GICv3: " fmt
20 #include <linux/acpi.h>
21 #include <linux/cpu.h>
22 #include <linux/cpu_pm.h>
23 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/percpu.h>
30 #include <linux/refcount.h>
31 #include <linux/slab.h>
33 #include <linux/irqchip.h>
34 #include <linux/irqchip/arm-gic-common.h>
35 #include <linux/irqchip/arm-gic-v3.h>
36 #include <linux/irqchip/irq-partition-percpu.h>
38 #include <asm/cputype.h>
39 #include <asm/exception.h>
40 #include <asm/smp_plat.h>
43 #include "irq-gic-common.h"
45 #define GICD_INT_NMI_PRI (GICD_INT_DEF_PRI & ~0x80)
47 #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0)
49 struct redist_region
{
50 void __iomem
*redist_base
;
51 phys_addr_t phys_base
;
55 struct gic_chip_data
{
56 struct fwnode_handle
*fwnode
;
57 void __iomem
*dist_base
;
58 struct redist_region
*redist_regions
;
60 struct irq_domain
*domain
;
62 u32 nr_redist_regions
;
66 struct partition_desc
*ppi_descs
[16];
69 static struct gic_chip_data gic_data __read_mostly
;
70 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key
);
73 * The behaviours of RPR and PMR registers differ depending on the value of
74 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
75 * distributor and redistributors depends on whether security is enabled in the
78 * When security is enabled, non-secure priority values from the (re)distributor
79 * are presented to the GIC CPUIF as follow:
80 * (GIC_(R)DIST_PRI[irq] >> 1) | 0x80;
82 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
83 * EL1 are subject to a similar operation thus matching the priorities presented
84 * from the (re)distributor when security is enabled.
86 * see GICv3/GICv4 Architecture Specification (IHI0069D):
87 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
89 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
92 * For now, we only support pseudo-NMIs if we have non-secure view of
95 static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis
);
97 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
98 static refcount_t ppi_nmi_refs
[16];
100 static struct gic_kvm_info gic_v3_kvm_info
;
101 static DEFINE_PER_CPU(bool, has_rss
);
103 #define MPIDR_RS(mpidr) (((mpidr) & 0xF0UL) >> 4)
104 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist))
105 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
106 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K)
108 /* Our default, arbitrary priority value. Linux only uses one anyway. */
109 #define DEFAULT_PMR_VALUE 0xf0
111 static inline unsigned int gic_irq(struct irq_data
*d
)
116 static inline int gic_irq_in_rdist(struct irq_data
*d
)
118 return gic_irq(d
) < 32;
121 static inline void __iomem
*gic_dist_base(struct irq_data
*d
)
123 if (gic_irq_in_rdist(d
)) /* SGI+PPI -> SGI_base for this CPU */
124 return gic_data_rdist_sgi_base();
126 if (d
->hwirq
<= 1023) /* SPI -> dist_base */
127 return gic_data
.dist_base
;
132 static void gic_do_wait_for_rwp(void __iomem
*base
)
134 u32 count
= 1000000; /* 1s! */
136 while (readl_relaxed(base
+ GICD_CTLR
) & GICD_CTLR_RWP
) {
139 pr_err_ratelimited("RWP timeout, gone fishing\n");
147 /* Wait for completion of a distributor change */
148 static void gic_dist_wait_for_rwp(void)
150 gic_do_wait_for_rwp(gic_data
.dist_base
);
153 /* Wait for completion of a redistributor change */
154 static void gic_redist_wait_for_rwp(void)
156 gic_do_wait_for_rwp(gic_data_rdist_rd_base());
161 static u64 __maybe_unused
gic_read_iar(void)
163 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154
))
164 return gic_read_iar_cavium_thunderx();
166 return gic_read_iar_common();
170 static void gic_enable_redist(bool enable
)
173 u32 count
= 1000000; /* 1s! */
176 if (gic_data
.flags
& FLAGS_WORKAROUND_GICR_WAKER_MSM8996
)
179 rbase
= gic_data_rdist_rd_base();
181 val
= readl_relaxed(rbase
+ GICR_WAKER
);
183 /* Wake up this CPU redistributor */
184 val
&= ~GICR_WAKER_ProcessorSleep
;
186 val
|= GICR_WAKER_ProcessorSleep
;
187 writel_relaxed(val
, rbase
+ GICR_WAKER
);
189 if (!enable
) { /* Check that GICR_WAKER is writeable */
190 val
= readl_relaxed(rbase
+ GICR_WAKER
);
191 if (!(val
& GICR_WAKER_ProcessorSleep
))
192 return; /* No PM support in this redistributor */
196 val
= readl_relaxed(rbase
+ GICR_WAKER
);
197 if (enable
^ (bool)(val
& GICR_WAKER_ChildrenAsleep
))
203 pr_err_ratelimited("redistributor failed to %s...\n",
204 enable
? "wakeup" : "sleep");
208 * Routines to disable, enable, EOI and route interrupts
210 static int gic_peek_irq(struct irq_data
*d
, u32 offset
)
212 u32 mask
= 1 << (gic_irq(d
) % 32);
215 if (gic_irq_in_rdist(d
))
216 base
= gic_data_rdist_sgi_base();
218 base
= gic_data
.dist_base
;
220 return !!(readl_relaxed(base
+ offset
+ (gic_irq(d
) / 32) * 4) & mask
);
223 static void gic_poke_irq(struct irq_data
*d
, u32 offset
)
225 u32 mask
= 1 << (gic_irq(d
) % 32);
226 void (*rwp_wait
)(void);
229 if (gic_irq_in_rdist(d
)) {
230 base
= gic_data_rdist_sgi_base();
231 rwp_wait
= gic_redist_wait_for_rwp
;
233 base
= gic_data
.dist_base
;
234 rwp_wait
= gic_dist_wait_for_rwp
;
237 writel_relaxed(mask
, base
+ offset
+ (gic_irq(d
) / 32) * 4);
241 static void gic_mask_irq(struct irq_data
*d
)
243 gic_poke_irq(d
, GICD_ICENABLER
);
246 static void gic_eoimode1_mask_irq(struct irq_data
*d
)
250 * When masking a forwarded interrupt, make sure it is
251 * deactivated as well.
253 * This ensures that an interrupt that is getting
254 * disabled/masked will not get "stuck", because there is
255 * noone to deactivate it (guest is being terminated).
257 if (irqd_is_forwarded_to_vcpu(d
))
258 gic_poke_irq(d
, GICD_ICACTIVER
);
261 static void gic_unmask_irq(struct irq_data
*d
)
263 gic_poke_irq(d
, GICD_ISENABLER
);
266 static inline bool gic_supports_nmi(void)
268 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI
) &&
269 static_branch_likely(&supports_pseudo_nmis
);
272 static int gic_irq_set_irqchip_state(struct irq_data
*d
,
273 enum irqchip_irq_state which
, bool val
)
277 if (d
->hwirq
>= gic_data
.irq_nr
) /* PPI/SPI only */
281 case IRQCHIP_STATE_PENDING
:
282 reg
= val
? GICD_ISPENDR
: GICD_ICPENDR
;
285 case IRQCHIP_STATE_ACTIVE
:
286 reg
= val
? GICD_ISACTIVER
: GICD_ICACTIVER
;
289 case IRQCHIP_STATE_MASKED
:
290 reg
= val
? GICD_ICENABLER
: GICD_ISENABLER
;
297 gic_poke_irq(d
, reg
);
301 static int gic_irq_get_irqchip_state(struct irq_data
*d
,
302 enum irqchip_irq_state which
, bool *val
)
304 if (d
->hwirq
>= gic_data
.irq_nr
) /* PPI/SPI only */
308 case IRQCHIP_STATE_PENDING
:
309 *val
= gic_peek_irq(d
, GICD_ISPENDR
);
312 case IRQCHIP_STATE_ACTIVE
:
313 *val
= gic_peek_irq(d
, GICD_ISACTIVER
);
316 case IRQCHIP_STATE_MASKED
:
317 *val
= !gic_peek_irq(d
, GICD_ISENABLER
);
327 static void gic_irq_set_prio(struct irq_data
*d
, u8 prio
)
329 void __iomem
*base
= gic_dist_base(d
);
331 writeb_relaxed(prio
, base
+ GICD_IPRIORITYR
+ gic_irq(d
));
334 static int gic_irq_nmi_setup(struct irq_data
*d
)
336 struct irq_desc
*desc
= irq_to_desc(d
->irq
);
338 if (!gic_supports_nmi())
341 if (gic_peek_irq(d
, GICD_ISENABLER
)) {
342 pr_err("Cannot set NMI property of enabled IRQ %u\n", d
->irq
);
347 * A secondary irq_chip should be in charge of LPI request,
348 * it should not be possible to get there
350 if (WARN_ON(gic_irq(d
) >= 8192))
353 /* desc lock should already be held */
354 if (gic_irq(d
) < 32) {
355 /* Setting up PPI as NMI, only switch handler for first NMI */
356 if (!refcount_inc_not_zero(&ppi_nmi_refs
[gic_irq(d
) - 16])) {
357 refcount_set(&ppi_nmi_refs
[gic_irq(d
) - 16], 1);
358 desc
->handle_irq
= handle_percpu_devid_fasteoi_nmi
;
361 desc
->handle_irq
= handle_fasteoi_nmi
;
364 gic_irq_set_prio(d
, GICD_INT_NMI_PRI
);
369 static void gic_irq_nmi_teardown(struct irq_data
*d
)
371 struct irq_desc
*desc
= irq_to_desc(d
->irq
);
373 if (WARN_ON(!gic_supports_nmi()))
376 if (gic_peek_irq(d
, GICD_ISENABLER
)) {
377 pr_err("Cannot set NMI property of enabled IRQ %u\n", d
->irq
);
382 * A secondary irq_chip should be in charge of LPI request,
383 * it should not be possible to get there
385 if (WARN_ON(gic_irq(d
) >= 8192))
388 /* desc lock should already be held */
389 if (gic_irq(d
) < 32) {
390 /* Tearing down NMI, only switch handler for last NMI */
391 if (refcount_dec_and_test(&ppi_nmi_refs
[gic_irq(d
) - 16]))
392 desc
->handle_irq
= handle_percpu_devid_irq
;
394 desc
->handle_irq
= handle_fasteoi_irq
;
397 gic_irq_set_prio(d
, GICD_INT_DEF_PRI
);
400 static void gic_eoi_irq(struct irq_data
*d
)
402 gic_write_eoir(gic_irq(d
));
405 static void gic_eoimode1_eoi_irq(struct irq_data
*d
)
408 * No need to deactivate an LPI, or an interrupt that
409 * is is getting forwarded to a vcpu.
411 if (gic_irq(d
) >= 8192 || irqd_is_forwarded_to_vcpu(d
))
413 gic_write_dir(gic_irq(d
));
416 static int gic_set_type(struct irq_data
*d
, unsigned int type
)
418 unsigned int irq
= gic_irq(d
);
419 void (*rwp_wait
)(void);
422 /* Interrupt configuration for SGIs can't be changed */
426 /* SPIs have restrictions on the supported types */
427 if (irq
>= 32 && type
!= IRQ_TYPE_LEVEL_HIGH
&&
428 type
!= IRQ_TYPE_EDGE_RISING
)
431 if (gic_irq_in_rdist(d
)) {
432 base
= gic_data_rdist_sgi_base();
433 rwp_wait
= gic_redist_wait_for_rwp
;
435 base
= gic_data
.dist_base
;
436 rwp_wait
= gic_dist_wait_for_rwp
;
439 return gic_configure_irq(irq
, type
, base
, rwp_wait
);
442 static int gic_irq_set_vcpu_affinity(struct irq_data
*d
, void *vcpu
)
445 irqd_set_forwarded_to_vcpu(d
);
447 irqd_clr_forwarded_to_vcpu(d
);
451 static u64
gic_mpidr_to_affinity(unsigned long mpidr
)
455 aff
= ((u64
)MPIDR_AFFINITY_LEVEL(mpidr
, 3) << 32 |
456 MPIDR_AFFINITY_LEVEL(mpidr
, 2) << 16 |
457 MPIDR_AFFINITY_LEVEL(mpidr
, 1) << 8 |
458 MPIDR_AFFINITY_LEVEL(mpidr
, 0));
463 static void gic_deactivate_unhandled(u32 irqnr
)
465 if (static_branch_likely(&supports_deactivate_key
)) {
467 gic_write_dir(irqnr
);
469 gic_write_eoir(irqnr
);
473 static inline void gic_handle_nmi(u32 irqnr
, struct pt_regs
*regs
)
475 bool irqs_enabled
= interrupts_enabled(regs
);
481 if (static_branch_likely(&supports_deactivate_key
))
482 gic_write_eoir(irqnr
);
484 * Leave the PSR.I bit set to prevent other NMIs to be
485 * received while handling this one.
486 * PSR.I will be restored when we ERET to the
487 * interrupted context.
489 err
= handle_domain_nmi(gic_data
.domain
, irqnr
, regs
);
491 gic_deactivate_unhandled(irqnr
);
497 static asmlinkage
void __exception_irq_entry
gic_handle_irq(struct pt_regs
*regs
)
501 irqnr
= gic_read_iar();
503 if (gic_supports_nmi() &&
504 unlikely(gic_read_rpr() == GICD_INT_NMI_PRI
)) {
505 gic_handle_nmi(irqnr
, regs
);
509 if (gic_prio_masking_enabled()) {
511 gic_arch_enable_irqs();
514 if (likely(irqnr
> 15 && irqnr
< 1020) || irqnr
>= 8192) {
517 if (static_branch_likely(&supports_deactivate_key
))
518 gic_write_eoir(irqnr
);
522 err
= handle_domain_irq(gic_data
.domain
, irqnr
, regs
);
524 WARN_ONCE(true, "Unexpected interrupt received!\n");
525 gic_deactivate_unhandled(irqnr
);
530 gic_write_eoir(irqnr
);
531 if (static_branch_likely(&supports_deactivate_key
))
532 gic_write_dir(irqnr
);
535 * Unlike GICv2, we don't need an smp_rmb() here.
536 * The control dependency from gic_read_iar to
537 * the ISB in gic_write_eoir is enough to ensure
538 * that any shared data read by handle_IPI will
539 * be read after the ACK.
541 handle_IPI(irqnr
, regs
);
543 WARN_ONCE(true, "Unexpected SGI received!\n");
548 static u32
gic_get_pribits(void)
552 pribits
= gic_read_ctlr();
553 pribits
&= ICC_CTLR_EL1_PRI_BITS_MASK
;
554 pribits
>>= ICC_CTLR_EL1_PRI_BITS_SHIFT
;
560 static bool gic_has_group0(void)
565 old_pmr
= gic_read_pmr();
568 * Let's find out if Group0 is under control of EL3 or not by
569 * setting the highest possible, non-zero priority in PMR.
571 * If SCR_EL3.FIQ is set, the priority gets shifted down in
572 * order for the CPU interface to set bit 7, and keep the
573 * actual priority in the non-secure range. In the process, it
574 * looses the least significant bit and the actual priority
575 * becomes 0x80. Reading it back returns 0, indicating that
576 * we're don't have access to Group0.
578 gic_write_pmr(BIT(8 - gic_get_pribits()));
579 val
= gic_read_pmr();
581 gic_write_pmr(old_pmr
);
586 static void __init
gic_dist_init(void)
590 void __iomem
*base
= gic_data
.dist_base
;
592 /* Disable the distributor */
593 writel_relaxed(0, base
+ GICD_CTLR
);
594 gic_dist_wait_for_rwp();
597 * Configure SPIs as non-secure Group-1. This will only matter
598 * if the GIC only has a single security state. This will not
599 * do the right thing if the kernel is running in secure mode,
600 * but that's not the intended use case anyway.
602 for (i
= 32; i
< gic_data
.irq_nr
; i
+= 32)
603 writel_relaxed(~0, base
+ GICD_IGROUPR
+ i
/ 8);
605 gic_dist_config(base
, gic_data
.irq_nr
, gic_dist_wait_for_rwp
);
607 /* Enable distributor with ARE, Group1 */
608 writel_relaxed(GICD_CTLR_ARE_NS
| GICD_CTLR_ENABLE_G1A
| GICD_CTLR_ENABLE_G1
,
612 * Set all global interrupts to the boot CPU only. ARE must be
615 affinity
= gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id()));
616 for (i
= 32; i
< gic_data
.irq_nr
; i
++)
617 gic_write_irouter(affinity
, base
+ GICD_IROUTER
+ i
* 8);
620 static int gic_iterate_rdists(int (*fn
)(struct redist_region
*, void __iomem
*))
625 for (i
= 0; i
< gic_data
.nr_redist_regions
; i
++) {
626 void __iomem
*ptr
= gic_data
.redist_regions
[i
].redist_base
;
630 reg
= readl_relaxed(ptr
+ GICR_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
631 if (reg
!= GIC_PIDR2_ARCH_GICv3
&&
632 reg
!= GIC_PIDR2_ARCH_GICv4
) { /* We're in trouble... */
633 pr_warn("No redistributor present @%p\n", ptr
);
638 typer
= gic_read_typer(ptr
+ GICR_TYPER
);
639 ret
= fn(gic_data
.redist_regions
+ i
, ptr
);
643 if (gic_data
.redist_regions
[i
].single_redist
)
646 if (gic_data
.redist_stride
) {
647 ptr
+= gic_data
.redist_stride
;
649 ptr
+= SZ_64K
* 2; /* Skip RD_base + SGI_base */
650 if (typer
& GICR_TYPER_VLPIS
)
651 ptr
+= SZ_64K
* 2; /* Skip VLPI_base + reserved page */
653 } while (!(typer
& GICR_TYPER_LAST
));
656 return ret
? -ENODEV
: 0;
659 static int __gic_populate_rdist(struct redist_region
*region
, void __iomem
*ptr
)
661 unsigned long mpidr
= cpu_logical_map(smp_processor_id());
666 * Convert affinity to a 32bit value that can be matched to
667 * GICR_TYPER bits [63:32].
669 aff
= (MPIDR_AFFINITY_LEVEL(mpidr
, 3) << 24 |
670 MPIDR_AFFINITY_LEVEL(mpidr
, 2) << 16 |
671 MPIDR_AFFINITY_LEVEL(mpidr
, 1) << 8 |
672 MPIDR_AFFINITY_LEVEL(mpidr
, 0));
674 typer
= gic_read_typer(ptr
+ GICR_TYPER
);
675 if ((typer
>> 32) == aff
) {
676 u64 offset
= ptr
- region
->redist_base
;
677 gic_data_rdist_rd_base() = ptr
;
678 gic_data_rdist()->phys_base
= region
->phys_base
+ offset
;
680 pr_info("CPU%d: found redistributor %lx region %d:%pa\n",
681 smp_processor_id(), mpidr
,
682 (int)(region
- gic_data
.redist_regions
),
683 &gic_data_rdist()->phys_base
);
691 static int gic_populate_rdist(void)
693 if (gic_iterate_rdists(__gic_populate_rdist
) == 0)
696 /* We couldn't even deal with ourselves... */
697 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n",
699 (unsigned long)cpu_logical_map(smp_processor_id()));
703 static int __gic_update_vlpi_properties(struct redist_region
*region
,
706 u64 typer
= gic_read_typer(ptr
+ GICR_TYPER
);
707 gic_data
.rdists
.has_vlpis
&= !!(typer
& GICR_TYPER_VLPIS
);
708 gic_data
.rdists
.has_direct_lpi
&= !!(typer
& GICR_TYPER_DirectLPIS
);
713 static void gic_update_vlpi_properties(void)
715 gic_iterate_rdists(__gic_update_vlpi_properties
);
716 pr_info("%sVLPI support, %sdirect LPI support\n",
717 !gic_data
.rdists
.has_vlpis
? "no " : "",
718 !gic_data
.rdists
.has_direct_lpi
? "no " : "");
721 /* Check whether it's single security state view */
722 static inline bool gic_dist_security_disabled(void)
724 return readl_relaxed(gic_data
.dist_base
+ GICD_CTLR
) & GICD_CTLR_DS
;
727 static void gic_cpu_sys_reg_init(void)
729 int i
, cpu
= smp_processor_id();
730 u64 mpidr
= cpu_logical_map(cpu
);
731 u64 need_rss
= MPIDR_RS(mpidr
);
736 * Need to check that the SRE bit has actually been set. If
737 * not, it means that SRE is disabled at EL2. We're going to
738 * die painfully, and there is nothing we can do about it.
740 * Kindly inform the luser.
742 if (!gic_enable_sre())
743 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
745 pribits
= gic_get_pribits();
747 group0
= gic_has_group0();
749 /* Set priority mask register */
750 if (!gic_prio_masking_enabled()) {
751 write_gicreg(DEFAULT_PMR_VALUE
, ICC_PMR_EL1
);
754 * Mismatch configuration with boot CPU, the system is likely
755 * to die as interrupt masking will not work properly on all
758 WARN_ON(gic_supports_nmi() && group0
&&
759 !gic_dist_security_disabled());
763 * Some firmwares hand over to the kernel with the BPR changed from
764 * its reset value (and with a value large enough to prevent
765 * any pre-emptive interrupts from working at all). Writing a zero
766 * to BPR restores is reset value.
770 if (static_branch_likely(&supports_deactivate_key
)) {
771 /* EOI drops priority only (mode 1) */
772 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop
);
774 /* EOI deactivates interrupt too (mode 0) */
775 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir
);
778 /* Always whack Group0 before Group1 */
783 write_gicreg(0, ICC_AP0R3_EL1
);
784 write_gicreg(0, ICC_AP0R2_EL1
);
786 write_gicreg(0, ICC_AP0R1_EL1
);
789 write_gicreg(0, ICC_AP0R0_EL1
);
798 write_gicreg(0, ICC_AP1R3_EL1
);
799 write_gicreg(0, ICC_AP1R2_EL1
);
801 write_gicreg(0, ICC_AP1R1_EL1
);
804 write_gicreg(0, ICC_AP1R0_EL1
);
809 /* ... and let's hit the road... */
812 /* Keep the RSS capability status in per_cpu variable */
813 per_cpu(has_rss
, cpu
) = !!(gic_read_ctlr() & ICC_CTLR_EL1_RSS
);
815 /* Check all the CPUs have capable of sending SGIs to other CPUs */
816 for_each_online_cpu(i
) {
817 bool have_rss
= per_cpu(has_rss
, i
) && per_cpu(has_rss
, cpu
);
819 need_rss
|= MPIDR_RS(cpu_logical_map(i
));
820 if (need_rss
&& (!have_rss
))
821 pr_crit("CPU%d (%lx) can't SGI CPU%d (%lx), no RSS\n",
822 cpu
, (unsigned long)mpidr
,
823 i
, (unsigned long)cpu_logical_map(i
));
827 * GIC spec says, when ICC_CTLR_EL1.RSS==1 and GICD_TYPER.RSS==0,
828 * writing ICC_ASGI1R_EL1 register with RS != 0 is a CONSTRAINED
829 * UNPREDICTABLE choice of :
830 * - The write is ignored.
831 * - The RS field is treated as 0.
833 if (need_rss
&& (!gic_data
.has_rss
))
834 pr_crit_once("RSS is required but GICD doesn't support it\n");
837 static bool gicv3_nolpi
;
839 static int __init
gicv3_nolpi_cfg(char *buf
)
841 return strtobool(buf
, &gicv3_nolpi
);
843 early_param("irqchip.gicv3_nolpi", gicv3_nolpi_cfg
);
845 static int gic_dist_supports_lpis(void)
847 return (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS
) &&
848 !!(readl_relaxed(gic_data
.dist_base
+ GICD_TYPER
) & GICD_TYPER_LPIS
) &&
852 static void gic_cpu_init(void)
856 /* Register ourselves with the rest of the world */
857 if (gic_populate_rdist())
860 gic_enable_redist(true);
862 rbase
= gic_data_rdist_sgi_base();
864 /* Configure SGIs/PPIs as non-secure Group-1 */
865 writel_relaxed(~0, rbase
+ GICR_IGROUPR0
);
867 gic_cpu_config(rbase
, gic_redist_wait_for_rwp
);
869 /* initialise system registers */
870 gic_cpu_sys_reg_init();
875 #define MPIDR_TO_SGI_RS(mpidr) (MPIDR_RS(mpidr) << ICC_SGI1R_RS_SHIFT)
876 #define MPIDR_TO_SGI_CLUSTER_ID(mpidr) ((mpidr) & ~0xFUL)
878 static int gic_starting_cpu(unsigned int cpu
)
882 if (gic_dist_supports_lpis())
888 static u16
gic_compute_target_list(int *base_cpu
, const struct cpumask
*mask
,
889 unsigned long cluster_id
)
891 int next_cpu
, cpu
= *base_cpu
;
892 unsigned long mpidr
= cpu_logical_map(cpu
);
895 while (cpu
< nr_cpu_ids
) {
896 tlist
|= 1 << (mpidr
& 0xf);
898 next_cpu
= cpumask_next(cpu
, mask
);
899 if (next_cpu
>= nr_cpu_ids
)
903 mpidr
= cpu_logical_map(cpu
);
905 if (cluster_id
!= MPIDR_TO_SGI_CLUSTER_ID(mpidr
)) {
915 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \
916 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \
917 << ICC_SGI1R_AFFINITY_## level ##_SHIFT)
919 static void gic_send_sgi(u64 cluster_id
, u16 tlist
, unsigned int irq
)
923 val
= (MPIDR_TO_SGI_AFFINITY(cluster_id
, 3) |
924 MPIDR_TO_SGI_AFFINITY(cluster_id
, 2) |
925 irq
<< ICC_SGI1R_SGI_ID_SHIFT
|
926 MPIDR_TO_SGI_AFFINITY(cluster_id
, 1) |
927 MPIDR_TO_SGI_RS(cluster_id
) |
928 tlist
<< ICC_SGI1R_TARGET_LIST_SHIFT
);
930 pr_devel("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val
);
931 gic_write_sgi1r(val
);
934 static void gic_raise_softirq(const struct cpumask
*mask
, unsigned int irq
)
938 if (WARN_ON(irq
>= 16))
942 * Ensure that stores to Normal memory are visible to the
943 * other CPUs before issuing the IPI.
947 for_each_cpu(cpu
, mask
) {
948 u64 cluster_id
= MPIDR_TO_SGI_CLUSTER_ID(cpu_logical_map(cpu
));
951 tlist
= gic_compute_target_list(&cpu
, mask
, cluster_id
);
952 gic_send_sgi(cluster_id
, tlist
, irq
);
955 /* Force the above writes to ICC_SGI1R_EL1 to be executed */
959 static void gic_smp_init(void)
961 set_smp_cross_call(gic_raise_softirq
);
962 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING
,
963 "irqchip/arm/gicv3:starting",
964 gic_starting_cpu
, NULL
);
967 static int gic_set_affinity(struct irq_data
*d
, const struct cpumask
*mask_val
,
976 cpu
= cpumask_first(mask_val
);
978 cpu
= cpumask_any_and(mask_val
, cpu_online_mask
);
980 if (cpu
>= nr_cpu_ids
)
983 if (gic_irq_in_rdist(d
))
986 /* If interrupt was enabled, disable it first */
987 enabled
= gic_peek_irq(d
, GICD_ISENABLER
);
991 reg
= gic_dist_base(d
) + GICD_IROUTER
+ (gic_irq(d
) * 8);
992 val
= gic_mpidr_to_affinity(cpu_logical_map(cpu
));
994 gic_write_irouter(val
, reg
);
997 * If the interrupt was enabled, enabled it again. Otherwise,
998 * just wait for the distributor to have digested our changes.
1003 gic_dist_wait_for_rwp();
1005 irq_data_update_effective_affinity(d
, cpumask_of(cpu
));
1007 return IRQ_SET_MASK_OK_DONE
;
1010 #define gic_set_affinity NULL
1011 #define gic_smp_init() do { } while(0)
1014 #ifdef CONFIG_CPU_PM
1015 static int gic_cpu_pm_notifier(struct notifier_block
*self
,
1016 unsigned long cmd
, void *v
)
1018 if (cmd
== CPU_PM_EXIT
) {
1019 if (gic_dist_security_disabled())
1020 gic_enable_redist(true);
1021 gic_cpu_sys_reg_init();
1022 } else if (cmd
== CPU_PM_ENTER
&& gic_dist_security_disabled()) {
1023 gic_write_grpen1(0);
1024 gic_enable_redist(false);
1029 static struct notifier_block gic_cpu_pm_notifier_block
= {
1030 .notifier_call
= gic_cpu_pm_notifier
,
1033 static void gic_cpu_pm_init(void)
1035 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block
);
1039 static inline void gic_cpu_pm_init(void) { }
1040 #endif /* CONFIG_CPU_PM */
1042 static struct irq_chip gic_chip
= {
1044 .irq_mask
= gic_mask_irq
,
1045 .irq_unmask
= gic_unmask_irq
,
1046 .irq_eoi
= gic_eoi_irq
,
1047 .irq_set_type
= gic_set_type
,
1048 .irq_set_affinity
= gic_set_affinity
,
1049 .irq_get_irqchip_state
= gic_irq_get_irqchip_state
,
1050 .irq_set_irqchip_state
= gic_irq_set_irqchip_state
,
1051 .irq_nmi_setup
= gic_irq_nmi_setup
,
1052 .irq_nmi_teardown
= gic_irq_nmi_teardown
,
1053 .flags
= IRQCHIP_SET_TYPE_MASKED
|
1054 IRQCHIP_SKIP_SET_WAKE
|
1055 IRQCHIP_MASK_ON_SUSPEND
,
1058 static struct irq_chip gic_eoimode1_chip
= {
1060 .irq_mask
= gic_eoimode1_mask_irq
,
1061 .irq_unmask
= gic_unmask_irq
,
1062 .irq_eoi
= gic_eoimode1_eoi_irq
,
1063 .irq_set_type
= gic_set_type
,
1064 .irq_set_affinity
= gic_set_affinity
,
1065 .irq_get_irqchip_state
= gic_irq_get_irqchip_state
,
1066 .irq_set_irqchip_state
= gic_irq_set_irqchip_state
,
1067 .irq_set_vcpu_affinity
= gic_irq_set_vcpu_affinity
,
1068 .irq_nmi_setup
= gic_irq_nmi_setup
,
1069 .irq_nmi_teardown
= gic_irq_nmi_teardown
,
1070 .flags
= IRQCHIP_SET_TYPE_MASKED
|
1071 IRQCHIP_SKIP_SET_WAKE
|
1072 IRQCHIP_MASK_ON_SUSPEND
,
1075 #define GIC_ID_NR (1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
1077 static int gic_irq_domain_map(struct irq_domain
*d
, unsigned int irq
,
1080 struct irq_chip
*chip
= &gic_chip
;
1082 if (static_branch_likely(&supports_deactivate_key
))
1083 chip
= &gic_eoimode1_chip
;
1085 /* SGIs are private to the core kernel */
1089 if (hw
>= gic_data
.irq_nr
&& hw
< 8192)
1092 if (hw
>= GIC_ID_NR
)
1097 irq_set_percpu_devid(irq
);
1098 irq_domain_set_info(d
, irq
, hw
, chip
, d
->host_data
,
1099 handle_percpu_devid_irq
, NULL
, NULL
);
1100 irq_set_status_flags(irq
, IRQ_NOAUTOEN
);
1103 if (hw
>= 32 && hw
< gic_data
.irq_nr
) {
1104 irq_domain_set_info(d
, irq
, hw
, chip
, d
->host_data
,
1105 handle_fasteoi_irq
, NULL
, NULL
);
1107 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq
)));
1110 if (hw
>= 8192 && hw
< GIC_ID_NR
) {
1111 if (!gic_dist_supports_lpis())
1113 irq_domain_set_info(d
, irq
, hw
, chip
, d
->host_data
,
1114 handle_fasteoi_irq
, NULL
, NULL
);
1120 #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1)
1122 static int gic_irq_domain_translate(struct irq_domain
*d
,
1123 struct irq_fwspec
*fwspec
,
1124 unsigned long *hwirq
,
1127 if (is_of_node(fwspec
->fwnode
)) {
1128 if (fwspec
->param_count
< 3)
1131 switch (fwspec
->param
[0]) {
1133 *hwirq
= fwspec
->param
[1] + 32;
1136 case GIC_IRQ_TYPE_PARTITION
:
1137 *hwirq
= fwspec
->param
[1] + 16;
1139 case GIC_IRQ_TYPE_LPI
: /* LPI */
1140 *hwirq
= fwspec
->param
[1];
1146 *type
= fwspec
->param
[2] & IRQ_TYPE_SENSE_MASK
;
1149 * Make it clear that broken DTs are... broken.
1150 * Partitionned PPIs are an unfortunate exception.
1152 WARN_ON(*type
== IRQ_TYPE_NONE
&&
1153 fwspec
->param
[0] != GIC_IRQ_TYPE_PARTITION
);
1157 if (is_fwnode_irqchip(fwspec
->fwnode
)) {
1158 if(fwspec
->param_count
!= 2)
1161 *hwirq
= fwspec
->param
[0];
1162 *type
= fwspec
->param
[1];
1164 WARN_ON(*type
== IRQ_TYPE_NONE
);
1171 static int gic_irq_domain_alloc(struct irq_domain
*domain
, unsigned int virq
,
1172 unsigned int nr_irqs
, void *arg
)
1175 irq_hw_number_t hwirq
;
1176 unsigned int type
= IRQ_TYPE_NONE
;
1177 struct irq_fwspec
*fwspec
= arg
;
1179 ret
= gic_irq_domain_translate(domain
, fwspec
, &hwirq
, &type
);
1183 for (i
= 0; i
< nr_irqs
; i
++) {
1184 ret
= gic_irq_domain_map(domain
, virq
+ i
, hwirq
+ i
);
1192 static void gic_irq_domain_free(struct irq_domain
*domain
, unsigned int virq
,
1193 unsigned int nr_irqs
)
1197 for (i
= 0; i
< nr_irqs
; i
++) {
1198 struct irq_data
*d
= irq_domain_get_irq_data(domain
, virq
+ i
);
1199 irq_set_handler(virq
+ i
, NULL
);
1200 irq_domain_reset_irq_data(d
);
1204 static int gic_irq_domain_select(struct irq_domain
*d
,
1205 struct irq_fwspec
*fwspec
,
1206 enum irq_domain_bus_token bus_token
)
1209 if (fwspec
->fwnode
!= d
->fwnode
)
1212 /* If this is not DT, then we have a single domain */
1213 if (!is_of_node(fwspec
->fwnode
))
1217 * If this is a PPI and we have a 4th (non-null) parameter,
1218 * then we need to match the partition domain.
1220 if (fwspec
->param_count
>= 4 &&
1221 fwspec
->param
[0] == 1 && fwspec
->param
[3] != 0)
1222 return d
== partition_get_domain(gic_data
.ppi_descs
[fwspec
->param
[1]]);
1224 return d
== gic_data
.domain
;
1227 static const struct irq_domain_ops gic_irq_domain_ops
= {
1228 .translate
= gic_irq_domain_translate
,
1229 .alloc
= gic_irq_domain_alloc
,
1230 .free
= gic_irq_domain_free
,
1231 .select
= gic_irq_domain_select
,
1234 static int partition_domain_translate(struct irq_domain
*d
,
1235 struct irq_fwspec
*fwspec
,
1236 unsigned long *hwirq
,
1239 struct device_node
*np
;
1242 np
= of_find_node_by_phandle(fwspec
->param
[3]);
1246 ret
= partition_translate_id(gic_data
.ppi_descs
[fwspec
->param
[1]],
1247 of_node_to_fwnode(np
));
1252 *type
= fwspec
->param
[2] & IRQ_TYPE_SENSE_MASK
;
1257 static const struct irq_domain_ops partition_domain_ops
= {
1258 .translate
= partition_domain_translate
,
1259 .select
= gic_irq_domain_select
,
1262 static bool gic_enable_quirk_msm8996(void *data
)
1264 struct gic_chip_data
*d
= data
;
1266 d
->flags
|= FLAGS_WORKAROUND_GICR_WAKER_MSM8996
;
1271 static void gic_enable_nmi_support(void)
1275 for (i
= 0; i
< 16; i
++)
1276 refcount_set(&ppi_nmi_refs
[i
], 0);
1278 static_branch_enable(&supports_pseudo_nmis
);
1280 if (static_branch_likely(&supports_deactivate_key
))
1281 gic_eoimode1_chip
.flags
|= IRQCHIP_SUPPORTS_NMI
;
1283 gic_chip
.flags
|= IRQCHIP_SUPPORTS_NMI
;
1286 static int __init
gic_init_bases(void __iomem
*dist_base
,
1287 struct redist_region
*rdist_regs
,
1288 u32 nr_redist_regions
,
1290 struct fwnode_handle
*handle
)
1296 if (!is_hyp_mode_available())
1297 static_branch_disable(&supports_deactivate_key
);
1299 if (static_branch_likely(&supports_deactivate_key
))
1300 pr_info("GIC: Using split EOI/Deactivate mode\n");
1302 gic_data
.fwnode
= handle
;
1303 gic_data
.dist_base
= dist_base
;
1304 gic_data
.redist_regions
= rdist_regs
;
1305 gic_data
.nr_redist_regions
= nr_redist_regions
;
1306 gic_data
.redist_stride
= redist_stride
;
1309 * Find out how many interrupts are supported.
1310 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)
1312 typer
= readl_relaxed(gic_data
.dist_base
+ GICD_TYPER
);
1313 gic_data
.rdists
.gicd_typer
= typer
;
1314 gic_irqs
= GICD_TYPER_IRQS(typer
);
1315 if (gic_irqs
> 1020)
1317 gic_data
.irq_nr
= gic_irqs
;
1319 gic_data
.domain
= irq_domain_create_tree(handle
, &gic_irq_domain_ops
,
1321 irq_domain_update_bus_token(gic_data
.domain
, DOMAIN_BUS_WIRED
);
1322 gic_data
.rdists
.rdist
= alloc_percpu(typeof(*gic_data
.rdists
.rdist
));
1323 gic_data
.rdists
.has_vlpis
= true;
1324 gic_data
.rdists
.has_direct_lpi
= true;
1326 if (WARN_ON(!gic_data
.domain
) || WARN_ON(!gic_data
.rdists
.rdist
)) {
1331 gic_data
.has_rss
= !!(typer
& GICD_TYPER_RSS
);
1332 pr_info("Distributor has %sRange Selector support\n",
1333 gic_data
.has_rss
? "" : "no ");
1335 if (typer
& GICD_TYPER_MBIS
) {
1336 err
= mbi_init(handle
, gic_data
.domain
);
1338 pr_err("Failed to initialize MBIs\n");
1341 set_handle_irq(gic_handle_irq
);
1343 gic_update_vlpi_properties();
1350 if (gic_dist_supports_lpis()) {
1351 its_init(handle
, &gic_data
.rdists
, gic_data
.domain
);
1355 if (gic_prio_masking_enabled()) {
1356 if (!gic_has_group0() || gic_dist_security_disabled())
1357 gic_enable_nmi_support();
1359 pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
1365 if (gic_data
.domain
)
1366 irq_domain_remove(gic_data
.domain
);
1367 free_percpu(gic_data
.rdists
.rdist
);
1371 static int __init
gic_validate_dist_version(void __iomem
*dist_base
)
1373 u32 reg
= readl_relaxed(dist_base
+ GICD_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
1375 if (reg
!= GIC_PIDR2_ARCH_GICv3
&& reg
!= GIC_PIDR2_ARCH_GICv4
)
1381 /* Create all possible partitions at boot time */
1382 static void __init
gic_populate_ppi_partitions(struct device_node
*gic_node
)
1384 struct device_node
*parts_node
, *child_part
;
1385 int part_idx
= 0, i
;
1387 struct partition_affinity
*parts
;
1389 parts_node
= of_get_child_by_name(gic_node
, "ppi-partitions");
1393 nr_parts
= of_get_child_count(parts_node
);
1398 parts
= kcalloc(nr_parts
, sizeof(*parts
), GFP_KERNEL
);
1399 if (WARN_ON(!parts
))
1402 for_each_child_of_node(parts_node
, child_part
) {
1403 struct partition_affinity
*part
;
1406 part
= &parts
[part_idx
];
1408 part
->partition_id
= of_node_to_fwnode(child_part
);
1410 pr_info("GIC: PPI partition %pOFn[%d] { ",
1411 child_part
, part_idx
);
1413 n
= of_property_count_elems_of_size(child_part
, "affinity",
1417 for (i
= 0; i
< n
; i
++) {
1420 struct device_node
*cpu_node
;
1422 err
= of_property_read_u32_index(child_part
, "affinity",
1427 cpu_node
= of_find_node_by_phandle(cpu_phandle
);
1428 if (WARN_ON(!cpu_node
))
1431 cpu
= of_cpu_node_to_id(cpu_node
);
1432 if (WARN_ON(cpu
< 0))
1435 pr_cont("%pOF[%d] ", cpu_node
, cpu
);
1437 cpumask_set_cpu(cpu
, &part
->mask
);
1444 for (i
= 0; i
< 16; i
++) {
1446 struct partition_desc
*desc
;
1447 struct irq_fwspec ppi_fwspec
= {
1448 .fwnode
= gic_data
.fwnode
,
1451 [0] = GIC_IRQ_TYPE_PARTITION
,
1453 [2] = IRQ_TYPE_NONE
,
1457 irq
= irq_create_fwspec_mapping(&ppi_fwspec
);
1460 desc
= partition_create_desc(gic_data
.fwnode
, parts
, nr_parts
,
1461 irq
, &partition_domain_ops
);
1465 gic_data
.ppi_descs
[i
] = desc
;
1469 of_node_put(parts_node
);
1472 static void __init
gic_of_setup_kvm_info(struct device_node
*node
)
1478 gic_v3_kvm_info
.type
= GIC_V3
;
1480 gic_v3_kvm_info
.maint_irq
= irq_of_parse_and_map(node
, 0);
1481 if (!gic_v3_kvm_info
.maint_irq
)
1484 if (of_property_read_u32(node
, "#redistributor-regions",
1488 gicv_idx
+= 3; /* Also skip GICD, GICC, GICH */
1489 ret
= of_address_to_resource(node
, gicv_idx
, &r
);
1491 gic_v3_kvm_info
.vcpu
= r
;
1493 gic_v3_kvm_info
.has_v4
= gic_data
.rdists
.has_vlpis
;
1494 gic_set_kvm_info(&gic_v3_kvm_info
);
1497 static const struct gic_quirk gic_quirks
[] = {
1499 .desc
= "GICv3: Qualcomm MSM8996 broken firmware",
1500 .compatible
= "qcom,msm8996-gic-v3",
1501 .init
= gic_enable_quirk_msm8996
,
1507 static int __init
gic_of_init(struct device_node
*node
, struct device_node
*parent
)
1509 void __iomem
*dist_base
;
1510 struct redist_region
*rdist_regs
;
1512 u32 nr_redist_regions
;
1515 dist_base
= of_iomap(node
, 0);
1517 pr_err("%pOF: unable to map gic dist registers\n", node
);
1521 err
= gic_validate_dist_version(dist_base
);
1523 pr_err("%pOF: no distributor detected, giving up\n", node
);
1524 goto out_unmap_dist
;
1527 if (of_property_read_u32(node
, "#redistributor-regions", &nr_redist_regions
))
1528 nr_redist_regions
= 1;
1530 rdist_regs
= kcalloc(nr_redist_regions
, sizeof(*rdist_regs
),
1534 goto out_unmap_dist
;
1537 for (i
= 0; i
< nr_redist_regions
; i
++) {
1538 struct resource res
;
1541 ret
= of_address_to_resource(node
, 1 + i
, &res
);
1542 rdist_regs
[i
].redist_base
= of_iomap(node
, 1 + i
);
1543 if (ret
|| !rdist_regs
[i
].redist_base
) {
1544 pr_err("%pOF: couldn't map region %d\n", node
, i
);
1546 goto out_unmap_rdist
;
1548 rdist_regs
[i
].phys_base
= res
.start
;
1551 if (of_property_read_u64(node
, "redistributor-stride", &redist_stride
))
1554 gic_enable_of_quirks(node
, gic_quirks
, &gic_data
);
1556 err
= gic_init_bases(dist_base
, rdist_regs
, nr_redist_regions
,
1557 redist_stride
, &node
->fwnode
);
1559 goto out_unmap_rdist
;
1561 gic_populate_ppi_partitions(node
);
1563 if (static_branch_likely(&supports_deactivate_key
))
1564 gic_of_setup_kvm_info(node
);
1568 for (i
= 0; i
< nr_redist_regions
; i
++)
1569 if (rdist_regs
[i
].redist_base
)
1570 iounmap(rdist_regs
[i
].redist_base
);
1577 IRQCHIP_DECLARE(gic_v3
, "arm,gic-v3", gic_of_init
);
1582 void __iomem
*dist_base
;
1583 struct redist_region
*redist_regs
;
1584 u32 nr_redist_regions
;
1588 phys_addr_t vcpu_base
;
1589 } acpi_data __initdata
;
1592 gic_acpi_register_redist(phys_addr_t phys_base
, void __iomem
*redist_base
)
1594 static int count
= 0;
1596 acpi_data
.redist_regs
[count
].phys_base
= phys_base
;
1597 acpi_data
.redist_regs
[count
].redist_base
= redist_base
;
1598 acpi_data
.redist_regs
[count
].single_redist
= acpi_data
.single_redist
;
1603 gic_acpi_parse_madt_redist(struct acpi_subtable_header
*header
,
1604 const unsigned long end
)
1606 struct acpi_madt_generic_redistributor
*redist
=
1607 (struct acpi_madt_generic_redistributor
*)header
;
1608 void __iomem
*redist_base
;
1610 redist_base
= ioremap(redist
->base_address
, redist
->length
);
1612 pr_err("Couldn't map GICR region @%llx\n", redist
->base_address
);
1616 gic_acpi_register_redist(redist
->base_address
, redist_base
);
1621 gic_acpi_parse_madt_gicc(struct acpi_subtable_header
*header
,
1622 const unsigned long end
)
1624 struct acpi_madt_generic_interrupt
*gicc
=
1625 (struct acpi_madt_generic_interrupt
*)header
;
1626 u32 reg
= readl_relaxed(acpi_data
.dist_base
+ GICD_PIDR2
) & GIC_PIDR2_ARCH_MASK
;
1627 u32 size
= reg
== GIC_PIDR2_ARCH_GICv4
? SZ_64K
* 4 : SZ_64K
* 2;
1628 void __iomem
*redist_base
;
1630 /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
1631 if (!(gicc
->flags
& ACPI_MADT_ENABLED
))
1634 redist_base
= ioremap(gicc
->gicr_base_address
, size
);
1638 gic_acpi_register_redist(gicc
->gicr_base_address
, redist_base
);
1642 static int __init
gic_acpi_collect_gicr_base(void)
1644 acpi_tbl_entry_handler redist_parser
;
1645 enum acpi_madt_type type
;
1647 if (acpi_data
.single_redist
) {
1648 type
= ACPI_MADT_TYPE_GENERIC_INTERRUPT
;
1649 redist_parser
= gic_acpi_parse_madt_gicc
;
1651 type
= ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR
;
1652 redist_parser
= gic_acpi_parse_madt_redist
;
1655 /* Collect redistributor base addresses in GICR entries */
1656 if (acpi_table_parse_madt(type
, redist_parser
, 0) > 0)
1659 pr_info("No valid GICR entries exist\n");
1663 static int __init
gic_acpi_match_gicr(struct acpi_subtable_header
*header
,
1664 const unsigned long end
)
1666 /* Subtable presence means that redist exists, that's it */
1670 static int __init
gic_acpi_match_gicc(struct acpi_subtable_header
*header
,
1671 const unsigned long end
)
1673 struct acpi_madt_generic_interrupt
*gicc
=
1674 (struct acpi_madt_generic_interrupt
*)header
;
1677 * If GICC is enabled and has valid gicr base address, then it means
1678 * GICR base is presented via GICC
1680 if ((gicc
->flags
& ACPI_MADT_ENABLED
) && gicc
->gicr_base_address
)
1684 * It's perfectly valid firmware can pass disabled GICC entry, driver
1685 * should not treat as errors, skip the entry instead of probe fail.
1687 if (!(gicc
->flags
& ACPI_MADT_ENABLED
))
1693 static int __init
gic_acpi_count_gicr_regions(void)
1698 * Count how many redistributor regions we have. It is not allowed
1699 * to mix redistributor description, GICR and GICC subtables have to be
1700 * mutually exclusive.
1702 count
= acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR
,
1703 gic_acpi_match_gicr
, 0);
1705 acpi_data
.single_redist
= false;
1709 count
= acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT
,
1710 gic_acpi_match_gicc
, 0);
1712 acpi_data
.single_redist
= true;
1717 static bool __init
acpi_validate_gic_table(struct acpi_subtable_header
*header
,
1718 struct acpi_probe_entry
*ape
)
1720 struct acpi_madt_generic_distributor
*dist
;
1723 dist
= (struct acpi_madt_generic_distributor
*)header
;
1724 if (dist
->version
!= ape
->driver_data
)
1727 /* We need to do that exercise anyway, the sooner the better */
1728 count
= gic_acpi_count_gicr_regions();
1732 acpi_data
.nr_redist_regions
= count
;
1736 static int __init
gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header
*header
,
1737 const unsigned long end
)
1739 struct acpi_madt_generic_interrupt
*gicc
=
1740 (struct acpi_madt_generic_interrupt
*)header
;
1742 static int first_madt
= true;
1744 /* Skip unusable CPUs */
1745 if (!(gicc
->flags
& ACPI_MADT_ENABLED
))
1748 maint_irq_mode
= (gicc
->flags
& ACPI_MADT_VGIC_IRQ_MODE
) ?
1749 ACPI_EDGE_SENSITIVE
: ACPI_LEVEL_SENSITIVE
;
1754 acpi_data
.maint_irq
= gicc
->vgic_interrupt
;
1755 acpi_data
.maint_irq_mode
= maint_irq_mode
;
1756 acpi_data
.vcpu_base
= gicc
->gicv_base_address
;
1762 * The maintenance interrupt and GICV should be the same for every CPU
1764 if ((acpi_data
.maint_irq
!= gicc
->vgic_interrupt
) ||
1765 (acpi_data
.maint_irq_mode
!= maint_irq_mode
) ||
1766 (acpi_data
.vcpu_base
!= gicc
->gicv_base_address
))
1772 static bool __init
gic_acpi_collect_virt_info(void)
1776 count
= acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT
,
1777 gic_acpi_parse_virt_madt_gicc
, 0);
1782 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K)
1783 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1784 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1786 static void __init
gic_acpi_setup_kvm_info(void)
1790 if (!gic_acpi_collect_virt_info()) {
1791 pr_warn("Unable to get hardware information used for virtualization\n");
1795 gic_v3_kvm_info
.type
= GIC_V3
;
1797 irq
= acpi_register_gsi(NULL
, acpi_data
.maint_irq
,
1798 acpi_data
.maint_irq_mode
,
1803 gic_v3_kvm_info
.maint_irq
= irq
;
1805 if (acpi_data
.vcpu_base
) {
1806 struct resource
*vcpu
= &gic_v3_kvm_info
.vcpu
;
1808 vcpu
->flags
= IORESOURCE_MEM
;
1809 vcpu
->start
= acpi_data
.vcpu_base
;
1810 vcpu
->end
= vcpu
->start
+ ACPI_GICV2_VCPU_MEM_SIZE
- 1;
1813 gic_v3_kvm_info
.has_v4
= gic_data
.rdists
.has_vlpis
;
1814 gic_set_kvm_info(&gic_v3_kvm_info
);
1818 gic_acpi_init(struct acpi_subtable_header
*header
, const unsigned long end
)
1820 struct acpi_madt_generic_distributor
*dist
;
1821 struct fwnode_handle
*domain_handle
;
1825 /* Get distributor base address */
1826 dist
= (struct acpi_madt_generic_distributor
*)header
;
1827 acpi_data
.dist_base
= ioremap(dist
->base_address
,
1828 ACPI_GICV3_DIST_MEM_SIZE
);
1829 if (!acpi_data
.dist_base
) {
1830 pr_err("Unable to map GICD registers\n");
1834 err
= gic_validate_dist_version(acpi_data
.dist_base
);
1836 pr_err("No distributor detected at @%p, giving up\n",
1837 acpi_data
.dist_base
);
1838 goto out_dist_unmap
;
1841 size
= sizeof(*acpi_data
.redist_regs
) * acpi_data
.nr_redist_regions
;
1842 acpi_data
.redist_regs
= kzalloc(size
, GFP_KERNEL
);
1843 if (!acpi_data
.redist_regs
) {
1845 goto out_dist_unmap
;
1848 err
= gic_acpi_collect_gicr_base();
1850 goto out_redist_unmap
;
1852 domain_handle
= irq_domain_alloc_fwnode(acpi_data
.dist_base
);
1853 if (!domain_handle
) {
1855 goto out_redist_unmap
;
1858 err
= gic_init_bases(acpi_data
.dist_base
, acpi_data
.redist_regs
,
1859 acpi_data
.nr_redist_regions
, 0, domain_handle
);
1861 goto out_fwhandle_free
;
1863 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC
, domain_handle
);
1865 if (static_branch_likely(&supports_deactivate_key
))
1866 gic_acpi_setup_kvm_info();
1871 irq_domain_free_fwnode(domain_handle
);
1873 for (i
= 0; i
< acpi_data
.nr_redist_regions
; i
++)
1874 if (acpi_data
.redist_regs
[i
].redist_base
)
1875 iounmap(acpi_data
.redist_regs
[i
].redist_base
);
1876 kfree(acpi_data
.redist_regs
);
1878 iounmap(acpi_data
.dist_base
);
1881 IRQCHIP_ACPI_DECLARE(gic_v3
, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
,
1882 acpi_validate_gic_table
, ACPI_MADT_GIC_VERSION_V3
,
1884 IRQCHIP_ACPI_DECLARE(gic_v4
, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
,
1885 acpi_validate_gic_table
, ACPI_MADT_GIC_VERSION_V4
,
1887 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4
, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR
,
1888 acpi_validate_gic_table
, ACPI_MADT_GIC_VERSION_NONE
,