drivers/irqchip/irq-renesas-intc-irqpin.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas INTC External IRQ Pin Driver
   4  *
   5  *  Copyright (C) 2013 Magnus Damm
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/of.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/spinlock.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/ioport.h>
  14 #include <linux/io.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/err.h>
  18 #include <linux/slab.h>
  19 #include <linux/module.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22
  23 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
  24
  25 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
  26 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
  27 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
  28 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
  29 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
  30 #define INTC_IRQPIN_REG_NR_MANDATORY 5
  31 #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
  32 #define INTC_IRQPIN_REG_NR 6
  33
  34 /* INTC external IRQ PIN hardware register access:
  35  *
  36  * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
  37  * PRIO is read-write 32-bit with 4-bits per IRQ (**)
  38  * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
  39  * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  40  * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  41  *
  42  * (*) May be accessed by more than one driver instance - lock needed
  43  * (**) Read-modify-write access by one driver instance - lock needed
  44  * (***) Accessed by one driver instance only - no locking needed
  45  */
  46
  47 struct intc_irqpin_iomem {
  48         void __iomem *iomem;
  49         unsigned long (*read)(void __iomem *iomem);
  50         void (*write)(void __iomem *iomem, unsigned long data);
  51         int width;
  52 };
  53
  54 struct intc_irqpin_irq {
  55         int hw_irq;
  56         int requested_irq;
  57         int domain_irq;
  58         struct intc_irqpin_priv *p;
  59 };
  60
  61 struct intc_irqpin_priv {
  62         struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
  63         struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
  64         unsigned int sense_bitfield_width;
  65         struct platform_device *pdev;
  66         struct irq_chip irq_chip;
  67         struct irq_domain *irq_domain;
  68         atomic_t wakeup_path;
  69         unsigned shared_irqs:1;
  70         u8 shared_irq_mask;
  71 };
  72
  73 struct intc_irqpin_config {
  74         int irlm_bit;           /* -1 if non-existent */
  75 };
  76
  77 static unsigned long intc_irqpin_read32(void __iomem *iomem)
  78 {
  79         return ioread32(iomem);
  80 }
  81
  82 static unsigned long intc_irqpin_read8(void __iomem *iomem)
  83 {
  84         return ioread8(iomem);
  85 }
  86
  87 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
  88 {
  89         iowrite32(data, iomem);
  90 }
  91
  92 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
  93 {
  94         iowrite8(data, iomem);
  95 }
  96
  97 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
  98                                              int reg)
  99 {
 100         struct intc_irqpin_iomem *i = &p->iomem[reg];
 101
 102         return i->read(i->iomem);
 103 }
 104
 105 static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
 106                                      int reg, unsigned long data)
 107 {
 108         struct intc_irqpin_iomem *i = &p->iomem[reg];
 109
 110         i->write(i->iomem, data);
 111 }
 112
 113 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
 114                                                    int reg, int hw_irq)
 115 {
 116         return BIT((p->iomem[reg].width - 1) - hw_irq);
 117 }
 118
 119 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
 120                                                int reg, int hw_irq)
 121 {
 122         intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
 123 }
 124
 125 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
 126
 127 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
 128                                           int reg, int shift,
 129                                           int width, int value)
 130 {
 131         unsigned long flags;
 132         unsigned long tmp;
 133
 134         raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
 135
 136         tmp = intc_irqpin_read(p, reg);
 137         tmp &= ~(((1 << width) - 1) << shift);
 138         tmp |= value << shift;
 139         intc_irqpin_write(p, reg, tmp);
 140
 141         raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
 142 }
 143
 144 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
 145                                          int irq, int do_mask)
 146 {
 147         /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
 148         int bitfield_width = 4;
 149         int shift = 32 - (irq + 1) * bitfield_width;
 150
 151         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
 152                                       shift, bitfield_width,
 153                                       do_mask ? 0 : (1 << bitfield_width) - 1);
 154 }
 155
 156 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
 157 {
 158         /* The SENSE register is assumed to be 32-bit. */
 159         int bitfield_width = p->sense_bitfield_width;
 160         int shift = 32 - (irq + 1) * bitfield_width;
 161
 162         dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
 163
 164         if (value >= (1 << bitfield_width))
 165                 return -EINVAL;
 166
 167         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
 168                                       bitfield_width, value);
 169         return 0;
 170 }
 171
 172 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
 173 {
 174         dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
 175                 str, i->requested_irq, i->hw_irq, i->domain_irq);
 176 }
 177
 178 static void intc_irqpin_irq_enable(struct irq_data *d)
 179 {
 180         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 181         int hw_irq = irqd_to_hwirq(d);
 182
 183         intc_irqpin_dbg(&p->irq[hw_irq], "enable");
 184         intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
 185 }
 186
 187 static void intc_irqpin_irq_disable(struct irq_data *d)
 188 {
 189         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 190         int hw_irq = irqd_to_hwirq(d);
 191
 192         intc_irqpin_dbg(&p->irq[hw_irq], "disable");
 193         intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
 194 }
 195
 196 static void intc_irqpin_shared_irq_enable(struct irq_data *d)
 197 {
 198         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 199         int hw_irq = irqd_to_hwirq(d);
 200
 201         intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
 202         intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
 203
 204         p->shared_irq_mask &= ~BIT(hw_irq);
 205 }
 206
 207 static void intc_irqpin_shared_irq_disable(struct irq_data *d)
 208 {
 209         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 210         int hw_irq = irqd_to_hwirq(d);
 211
 212         intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
 213         intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
 214
 215         p->shared_irq_mask |= BIT(hw_irq);
 216 }
 217
 218 static void intc_irqpin_irq_enable_force(struct irq_data *d)
 219 {
 220         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 221         int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
 222
 223         intc_irqpin_irq_enable(d);
 224
 225         /* enable interrupt through parent interrupt controller,
 226          * assumes non-shared interrupt with 1:1 mapping
 227          * needed for busted IRQs on some SoCs like sh73a0
 228          */
 229         irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
 230 }
 231
 232 static void intc_irqpin_irq_disable_force(struct irq_data *d)
 233 {
 234         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 235         int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
 236
 237         /* disable interrupt through parent interrupt controller,
 238          * assumes non-shared interrupt with 1:1 mapping
 239          * needed for busted IRQs on some SoCs like sh73a0
 240          */
 241         irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
 242         intc_irqpin_irq_disable(d);
 243 }
 244
 245 #define INTC_IRQ_SENSE_VALID 0x10
 246 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
 247
 248 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
 249         [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
 250         [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
 251         [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
 252         [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
 253         [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
 254 };
 255
 256 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
 257 {
 258         unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
 259         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 260
 261         if (!(value & INTC_IRQ_SENSE_VALID))
 262                 return -EINVAL;
 263
 264         return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
 265                                      value ^ INTC_IRQ_SENSE_VALID);
 266 }
 267
 268 static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
 269 {
 270         struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 271         int hw_irq = irqd_to_hwirq(d);
 272
 273         irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
 274         if (on)
 275                 atomic_inc(&p->wakeup_path);
 276         else
 277                 atomic_dec(&p->wakeup_path);
 278
 279         return 0;
 280 }
 281
 282 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
 283 {
 284         struct intc_irqpin_irq *i = dev_id;
 285         struct intc_irqpin_priv *p = i->p;
 286         unsigned long bit;
 287
 288         intc_irqpin_dbg(i, "demux1");
 289         bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
 290
 291         if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
 292                 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
 293                 intc_irqpin_dbg(i, "demux2");
 294                 generic_handle_irq(i->domain_irq);
 295                 return IRQ_HANDLED;
 296         }
 297         return IRQ_NONE;
 298 }
 299
 300 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
 301 {
 302         struct intc_irqpin_priv *p = dev_id;
 303         unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
 304         irqreturn_t status = IRQ_NONE;
 305         int k;
 306
 307         for (k = 0; k < 8; k++) {
 308                 if (reg_source & BIT(7 - k)) {
 309                         if (BIT(k) & p->shared_irq_mask)
 310                                 continue;
 311
 312                         status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
 313                 }
 314         }
 315
 316         return status;
 317 }
 318
 319 /*
 320  * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
 321  * different category than their parents, so it won't report false recursion.
 322  */
 323 static struct lock_class_key intc_irqpin_irq_lock_class;
 324
 325 /* And this is for the request mutex */
 326 static struct lock_class_key intc_irqpin_irq_request_class;
 327
 328 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
 329                                       irq_hw_number_t hw)
 330 {
 331         struct intc_irqpin_priv *p = h->host_data;
 332
 333         p->irq[hw].domain_irq = virq;
 334         p->irq[hw].hw_irq = hw;
 335
 336         intc_irqpin_dbg(&p->irq[hw], "map");
 337         irq_set_chip_data(virq, h->host_data);
 338         irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
 339                               &intc_irqpin_irq_request_class);
 340         irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 341         return 0;
 342 }
 343
 344 static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
 345         .map    = intc_irqpin_irq_domain_map,
 346         .xlate  = irq_domain_xlate_twocell,
 347 };
 348
 349 static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
 350         .irlm_bit = 23, /* ICR0.IRLM0 */
 351 };
 352
 353 static const struct intc_irqpin_config intc_irqpin_rmobile = {
 354         .irlm_bit = -1,
 355 };
 356
 357 static const struct of_device_id intc_irqpin_dt_ids[] = {
 358         { .compatible = "renesas,intc-irqpin", },
 359         { .compatible = "renesas,intc-irqpin-r8a7778",
 360           .data = &intc_irqpin_irlm_r8a777x },
 361         { .compatible = "renesas,intc-irqpin-r8a7779",
 362           .data = &intc_irqpin_irlm_r8a777x },
 363         { .compatible = "renesas,intc-irqpin-r8a7740",
 364           .data = &intc_irqpin_rmobile },
 365         { .compatible = "renesas,intc-irqpin-sh73a0",
 366           .data = &intc_irqpin_rmobile },
 367         {},
 368 };
 369 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
 370
 371 static int intc_irqpin_probe(struct platform_device *pdev)
 372 {
 373         const struct intc_irqpin_config *config;
 374         struct device *dev = &pdev->dev;
 375         struct intc_irqpin_priv *p;
 376         struct intc_irqpin_iomem *i;
 377         struct resource *io[INTC_IRQPIN_REG_NR];
 378         struct irq_chip *irq_chip;
 379         void (*enable_fn)(struct irq_data *d);
 380         void (*disable_fn)(struct irq_data *d);
 381         const char *name = dev_name(dev);
 382         bool control_parent;
 383         unsigned int nirqs;
 384         int ref_irq;
 385         int ret;
 386         int k;
 387
 388         p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 389         if (!p)
 390                 return -ENOMEM;
 391
 392         /* deal with driver instance configuration */
 393         of_property_read_u32(dev->of_node, "sense-bitfield-width",
 394                              &p->sense_bitfield_width);
 395         control_parent = of_property_read_bool(dev->of_node, "control-parent");
 396         if (!p->sense_bitfield_width)
 397                 p->sense_bitfield_width = 4; /* default to 4 bits */
 398
 399         p->pdev = pdev;
 400         platform_set_drvdata(pdev, p);
 401
 402         config = of_device_get_match_data(dev);
 403
 404         pm_runtime_enable(dev);
 405         pm_runtime_get_sync(dev);
 406
 407         /* get hold of register banks */
 408         memset(io, 0, sizeof(io));
 409         for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
 410                 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
 411                 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
 412                         dev_err(dev, "not enough IOMEM resources\n");
 413                         ret = -EINVAL;
 414                         goto err0;
 415                 }
 416         }
 417
 418         /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
 419         for (k = 0; k < INTC_IRQPIN_MAX; k++) {
 420                 ret = platform_get_irq_optional(pdev, k);
 421                 if (ret == -ENXIO)
 422                         break;
 423                 if (ret < 0)
 424                         goto err0;
 425
 426                 p->irq[k].p = p;
 427                 p->irq[k].requested_irq = ret;
 428         }
 429
 430         nirqs = k;
 431         if (nirqs < 1) {
 432                 dev_err(dev, "not enough IRQ resources\n");
 433                 ret = -EINVAL;
 434                 goto err0;
 435         }
 436
 437         /* ioremap IOMEM and setup read/write callbacks */
 438         for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
 439                 i = &p->iomem[k];
 440
 441                 /* handle optional registers */
 442                 if (!io[k])
 443                         continue;
 444
 445                 switch (resource_size(io[k])) {
 446                 case 1:
 447                         i->width = 8;
 448                         i->read = intc_irqpin_read8;
 449                         i->write = intc_irqpin_write8;
 450                         break;
 451                 case 4:
 452                         i->width = 32;
 453                         i->read = intc_irqpin_read32;
 454                         i->write = intc_irqpin_write32;
 455                         break;
 456                 default:
 457                         dev_err(dev, "IOMEM size mismatch\n");
 458                         ret = -EINVAL;
 459                         goto err0;
 460                 }
 461
 462                 i->iomem = devm_ioremap(dev, io[k]->start,
 463                                         resource_size(io[k]));
 464                 if (!i->iomem) {
 465                         dev_err(dev, "failed to remap IOMEM\n");
 466                         ret = -ENXIO;
 467                         goto err0;
 468                 }
 469         }
 470
 471         /* configure "individual IRQ mode" where needed */
 472         if (config && config->irlm_bit >= 0) {
 473                 if (io[INTC_IRQPIN_REG_IRLM])
 474                         intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
 475                                                       config->irlm_bit, 1, 1);
 476                 else
 477                         dev_warn(dev, "unable to select IRLM mode\n");
 478         }
 479
 480         /* mask all interrupts using priority */
 481         for (k = 0; k < nirqs; k++)
 482                 intc_irqpin_mask_unmask_prio(p, k, 1);
 483
 484         /* clear all pending interrupts */
 485         intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
 486
 487         /* scan for shared interrupt lines */
 488         ref_irq = p->irq[0].requested_irq;
 489         p->shared_irqs = 1;
 490         for (k = 1; k < nirqs; k++) {
 491                 if (ref_irq != p->irq[k].requested_irq) {
 492                         p->shared_irqs = 0;
 493                         break;
 494                 }
 495         }
 496
 497         /* use more severe masking method if requested */
 498         if (control_parent) {
 499                 enable_fn = intc_irqpin_irq_enable_force;
 500                 disable_fn = intc_irqpin_irq_disable_force;
 501         } else if (!p->shared_irqs) {
 502                 enable_fn = intc_irqpin_irq_enable;
 503                 disable_fn = intc_irqpin_irq_disable;
 504         } else {
 505                 enable_fn = intc_irqpin_shared_irq_enable;
 506                 disable_fn = intc_irqpin_shared_irq_disable;
 507         }
 508
 509         irq_chip = &p->irq_chip;
 510         irq_chip->name = "intc-irqpin";
 511         irq_chip->irq_mask = disable_fn;
 512         irq_chip->irq_unmask = enable_fn;
 513         irq_chip->irq_set_type = intc_irqpin_irq_set_type;
 514         irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
 515         irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
 516
 517         p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
 518                                               &intc_irqpin_irq_domain_ops, p);
 519         if (!p->irq_domain) {
 520                 ret = -ENXIO;
 521                 dev_err(dev, "cannot initialize irq domain\n");
 522                 goto err0;
 523         }
 524
 525         irq_domain_set_pm_device(p->irq_domain, dev);
 526
 527         if (p->shared_irqs) {
 528                 /* request one shared interrupt */
 529                 if (devm_request_irq(dev, p->irq[0].requested_irq,
 530                                 intc_irqpin_shared_irq_handler,
 531                                 IRQF_SHARED, name, p)) {
 532                         dev_err(dev, "failed to request low IRQ\n");
 533                         ret = -ENOENT;
 534                         goto err1;
 535                 }
 536         } else {
 537                 /* request interrupts one by one */
 538                 for (k = 0; k < nirqs; k++) {
 539                         if (devm_request_irq(dev, p->irq[k].requested_irq,
 540                                              intc_irqpin_irq_handler, 0, name,
 541                                              &p->irq[k])) {
 542                                 dev_err(dev, "failed to request low IRQ\n");
 543                                 ret = -ENOENT;
 544                                 goto err1;
 545                         }
 546                 }
 547         }
 548
 549         /* unmask all interrupts on prio level */
 550         for (k = 0; k < nirqs; k++)
 551                 intc_irqpin_mask_unmask_prio(p, k, 0);
 552
 553         dev_info(dev, "driving %d irqs\n", nirqs);
 554
 555         return 0;
 556
 557 err1:
 558         irq_domain_remove(p->irq_domain);
 559 err0:
 560         pm_runtime_put(dev);
 561         pm_runtime_disable(dev);
 562         return ret;
 563 }
 564
 565 static int intc_irqpin_remove(struct platform_device *pdev)
 566 {
 567         struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
 568
 569         irq_domain_remove(p->irq_domain);
 570         pm_runtime_put(&pdev->dev);
 571         pm_runtime_disable(&pdev->dev);
 572         return 0;
 573 }
 574
 575 static int __maybe_unused intc_irqpin_suspend(struct device *dev)
 576 {
 577         struct intc_irqpin_priv *p = dev_get_drvdata(dev);
 578
 579         if (atomic_read(&p->wakeup_path))
 580                 device_set_wakeup_path(dev);
 581
 582         return 0;
 583 }
 584
 585 static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
 586
 587 static struct platform_driver intc_irqpin_device_driver = {
 588         .probe          = intc_irqpin_probe,
 589         .remove         = intc_irqpin_remove,
 590         .driver         = {
 591                 .name   = "renesas_intc_irqpin",
 592                 .of_match_table = intc_irqpin_dt_ids,
 593                 .pm     = &intc_irqpin_pm_ops,
 594         }
 595 };
 596
 597 static int __init intc_irqpin_init(void)
 598 {
 599         return platform_driver_register(&intc_irqpin_device_driver);
 600 }
 601 postcore_initcall(intc_irqpin_init);
 602
 603 static void __exit intc_irqpin_exit(void)
 604 {
 605         platform_driver_unregister(&intc_irqpin_device_driver);
 606 }
 607 module_exit(intc_irqpin_exit);
 608
 609 MODULE_AUTHOR("Magnus Damm");
 610 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
 611 MODULE_LICENSE("GPL v2");