1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics 2017
5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
8 #include <linux/bitops.h>
9 #include <linux/delay.h>
10 #include <linux/hwspinlock.h>
11 #include <linux/interrupt.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/platform_device.h>
22 #include <linux/syscore_ops.h>
24 #include <dt-bindings/interrupt-controller/arm-gic.h>
26 #define IRQS_PER_BANK 32
28 #define HWSPNLCK_TIMEOUT 1000 /* usec */
30 struct stm32_exti_bank
{
43 struct stm32_exti_drv_data
{
44 const struct stm32_exti_bank
**exti_banks
;
49 struct stm32_exti_chip_data
{
50 struct stm32_exti_host_data
*host_data
;
51 const struct stm32_exti_bank
*reg_bank
;
52 struct raw_spinlock rlock
;
59 struct stm32_exti_host_data
{
61 struct stm32_exti_chip_data
*chips_data
;
62 const struct stm32_exti_drv_data
*drv_data
;
63 struct hwspinlock
*hwlock
;
66 static struct stm32_exti_host_data
*stm32_host_data
;
68 static const struct stm32_exti_bank stm32f4xx_exti_b1
= {
75 .fpr_ofst
= UNDEF_REG
,
76 .trg_ofst
= UNDEF_REG
,
79 static const struct stm32_exti_bank
*stm32f4xx_exti_banks
[] = {
83 static const struct stm32_exti_drv_data stm32f4xx_drv_data
= {
84 .exti_banks
= stm32f4xx_exti_banks
,
85 .bank_nr
= ARRAY_SIZE(stm32f4xx_exti_banks
),
88 static const struct stm32_exti_bank stm32h7xx_exti_b1
= {
95 .fpr_ofst
= UNDEF_REG
,
96 .trg_ofst
= UNDEF_REG
,
99 static const struct stm32_exti_bank stm32h7xx_exti_b2
= {
106 .fpr_ofst
= UNDEF_REG
,
107 .trg_ofst
= UNDEF_REG
,
110 static const struct stm32_exti_bank stm32h7xx_exti_b3
= {
117 .fpr_ofst
= UNDEF_REG
,
118 .trg_ofst
= UNDEF_REG
,
121 static const struct stm32_exti_bank
*stm32h7xx_exti_banks
[] = {
127 static const struct stm32_exti_drv_data stm32h7xx_drv_data
= {
128 .exti_banks
= stm32h7xx_exti_banks
,
129 .bank_nr
= ARRAY_SIZE(stm32h7xx_exti_banks
),
132 static const struct stm32_exti_bank stm32mp1_exti_b1
= {
134 .emr_ofst
= UNDEF_REG
,
143 static const struct stm32_exti_bank stm32mp1_exti_b2
= {
145 .emr_ofst
= UNDEF_REG
,
154 static const struct stm32_exti_bank stm32mp1_exti_b3
= {
156 .emr_ofst
= UNDEF_REG
,
165 static const struct stm32_exti_bank
*stm32mp1_exti_banks
[] = {
171 static struct irq_chip stm32_exti_h_chip
;
172 static struct irq_chip stm32_exti_h_chip_direct
;
174 #define EXTI_INVALID_IRQ U8_MAX
175 #define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
178 * Use some intentionally tricky logic here to initialize the whole array to
179 * EXTI_INVALID_IRQ, but then override certain fields, requiring us to indicate
180 * that we "know" that there are overrides in this structure, and we'll need to
181 * disable that warning from W=1 builds.
184 __diag_ignore_all("-Woverride-init",
185 "logic to initialize all and then override some is OK");
187 static const u8 stm32mp1_desc_irq
[] = {
189 [0 ... (STM32MP1_DESC_IRQ_SIZE
- 1)] = EXTI_INVALID_IRQ
,
236 static const u8 stm32mp13_desc_irq
[] = {
238 [0 ... (STM32MP1_DESC_IRQ_SIZE
- 1)] = EXTI_INVALID_IRQ
,
283 static const struct stm32_exti_drv_data stm32mp1_drv_data
= {
284 .exti_banks
= stm32mp1_exti_banks
,
285 .bank_nr
= ARRAY_SIZE(stm32mp1_exti_banks
),
286 .desc_irqs
= stm32mp1_desc_irq
,
289 static const struct stm32_exti_drv_data stm32mp13_drv_data
= {
290 .exti_banks
= stm32mp1_exti_banks
,
291 .bank_nr
= ARRAY_SIZE(stm32mp1_exti_banks
),
292 .desc_irqs
= stm32mp13_desc_irq
,
295 static unsigned long stm32_exti_pending(struct irq_chip_generic
*gc
)
297 struct stm32_exti_chip_data
*chip_data
= gc
->private;
298 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
299 unsigned long pending
;
301 pending
= irq_reg_readl(gc
, stm32_bank
->rpr_ofst
);
302 if (stm32_bank
->fpr_ofst
!= UNDEF_REG
)
303 pending
|= irq_reg_readl(gc
, stm32_bank
->fpr_ofst
);
308 static void stm32_irq_handler(struct irq_desc
*desc
)
310 struct irq_domain
*domain
= irq_desc_get_handler_data(desc
);
311 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
312 unsigned int nbanks
= domain
->gc
->num_chips
;
313 struct irq_chip_generic
*gc
;
314 unsigned long pending
;
315 int n
, i
, irq_base
= 0;
317 chained_irq_enter(chip
, desc
);
319 for (i
= 0; i
< nbanks
; i
++, irq_base
+= IRQS_PER_BANK
) {
320 gc
= irq_get_domain_generic_chip(domain
, irq_base
);
322 while ((pending
= stm32_exti_pending(gc
))) {
323 for_each_set_bit(n
, &pending
, IRQS_PER_BANK
)
324 generic_handle_domain_irq(domain
, irq_base
+ n
);
328 chained_irq_exit(chip
, desc
);
331 static int stm32_exti_set_type(struct irq_data
*d
,
332 unsigned int type
, u32
*rtsr
, u32
*ftsr
)
334 u32 mask
= BIT(d
->hwirq
% IRQS_PER_BANK
);
337 case IRQ_TYPE_EDGE_RISING
:
341 case IRQ_TYPE_EDGE_FALLING
:
345 case IRQ_TYPE_EDGE_BOTH
:
356 static int stm32_irq_set_type(struct irq_data
*d
, unsigned int type
)
358 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
359 struct stm32_exti_chip_data
*chip_data
= gc
->private;
360 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
361 struct hwspinlock
*hwlock
= chip_data
->host_data
->hwlock
;
368 err
= hwspin_lock_timeout_in_atomic(hwlock
, HWSPNLCK_TIMEOUT
);
370 pr_err("%s can't get hwspinlock (%d)\n", __func__
, err
);
375 rtsr
= irq_reg_readl(gc
, stm32_bank
->rtsr_ofst
);
376 ftsr
= irq_reg_readl(gc
, stm32_bank
->ftsr_ofst
);
378 err
= stm32_exti_set_type(d
, type
, &rtsr
, &ftsr
);
382 irq_reg_writel(gc
, rtsr
, stm32_bank
->rtsr_ofst
);
383 irq_reg_writel(gc
, ftsr
, stm32_bank
->ftsr_ofst
);
387 hwspin_unlock_in_atomic(hwlock
);
394 static void stm32_chip_suspend(struct stm32_exti_chip_data
*chip_data
,
397 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
398 void __iomem
*base
= chip_data
->host_data
->base
;
400 /* save rtsr, ftsr registers */
401 chip_data
->rtsr_cache
= readl_relaxed(base
+ stm32_bank
->rtsr_ofst
);
402 chip_data
->ftsr_cache
= readl_relaxed(base
+ stm32_bank
->ftsr_ofst
);
404 writel_relaxed(wake_active
, base
+ stm32_bank
->imr_ofst
);
407 static void stm32_chip_resume(struct stm32_exti_chip_data
*chip_data
,
410 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
411 void __iomem
*base
= chip_data
->host_data
->base
;
413 /* restore rtsr, ftsr, registers */
414 writel_relaxed(chip_data
->rtsr_cache
, base
+ stm32_bank
->rtsr_ofst
);
415 writel_relaxed(chip_data
->ftsr_cache
, base
+ stm32_bank
->ftsr_ofst
);
417 writel_relaxed(mask_cache
, base
+ stm32_bank
->imr_ofst
);
420 static void stm32_irq_suspend(struct irq_chip_generic
*gc
)
422 struct stm32_exti_chip_data
*chip_data
= gc
->private;
425 stm32_chip_suspend(chip_data
, gc
->wake_active
);
429 static void stm32_irq_resume(struct irq_chip_generic
*gc
)
431 struct stm32_exti_chip_data
*chip_data
= gc
->private;
434 stm32_chip_resume(chip_data
, gc
->mask_cache
);
438 static int stm32_exti_alloc(struct irq_domain
*d
, unsigned int virq
,
439 unsigned int nr_irqs
, void *data
)
441 struct irq_fwspec
*fwspec
= data
;
442 irq_hw_number_t hwirq
;
444 hwirq
= fwspec
->param
[0];
446 irq_map_generic_chip(d
, virq
, hwirq
);
451 static void stm32_exti_free(struct irq_domain
*d
, unsigned int virq
,
452 unsigned int nr_irqs
)
454 struct irq_data
*data
= irq_domain_get_irq_data(d
, virq
);
456 irq_domain_reset_irq_data(data
);
459 static const struct irq_domain_ops irq_exti_domain_ops
= {
460 .map
= irq_map_generic_chip
,
461 .alloc
= stm32_exti_alloc
,
462 .free
= stm32_exti_free
,
463 .xlate
= irq_domain_xlate_twocell
,
466 static void stm32_irq_ack(struct irq_data
*d
)
468 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
469 struct stm32_exti_chip_data
*chip_data
= gc
->private;
470 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
474 irq_reg_writel(gc
, d
->mask
, stm32_bank
->rpr_ofst
);
475 if (stm32_bank
->fpr_ofst
!= UNDEF_REG
)
476 irq_reg_writel(gc
, d
->mask
, stm32_bank
->fpr_ofst
);
481 /* directly set the target bit without reading first. */
482 static inline void stm32_exti_write_bit(struct irq_data
*d
, u32 reg
)
484 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
485 void __iomem
*base
= chip_data
->host_data
->base
;
486 u32 val
= BIT(d
->hwirq
% IRQS_PER_BANK
);
488 writel_relaxed(val
, base
+ reg
);
491 static inline u32
stm32_exti_set_bit(struct irq_data
*d
, u32 reg
)
493 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
494 void __iomem
*base
= chip_data
->host_data
->base
;
497 val
= readl_relaxed(base
+ reg
);
498 val
|= BIT(d
->hwirq
% IRQS_PER_BANK
);
499 writel_relaxed(val
, base
+ reg
);
504 static inline u32
stm32_exti_clr_bit(struct irq_data
*d
, u32 reg
)
506 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
507 void __iomem
*base
= chip_data
->host_data
->base
;
510 val
= readl_relaxed(base
+ reg
);
511 val
&= ~BIT(d
->hwirq
% IRQS_PER_BANK
);
512 writel_relaxed(val
, base
+ reg
);
517 static void stm32_exti_h_eoi(struct irq_data
*d
)
519 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
520 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
522 raw_spin_lock(&chip_data
->rlock
);
524 stm32_exti_write_bit(d
, stm32_bank
->rpr_ofst
);
525 if (stm32_bank
->fpr_ofst
!= UNDEF_REG
)
526 stm32_exti_write_bit(d
, stm32_bank
->fpr_ofst
);
528 raw_spin_unlock(&chip_data
->rlock
);
530 if (d
->parent_data
->chip
)
531 irq_chip_eoi_parent(d
);
534 static void stm32_exti_h_mask(struct irq_data
*d
)
536 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
537 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
539 raw_spin_lock(&chip_data
->rlock
);
540 chip_data
->mask_cache
= stm32_exti_clr_bit(d
, stm32_bank
->imr_ofst
);
541 raw_spin_unlock(&chip_data
->rlock
);
543 if (d
->parent_data
->chip
)
544 irq_chip_mask_parent(d
);
547 static void stm32_exti_h_unmask(struct irq_data
*d
)
549 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
550 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
552 raw_spin_lock(&chip_data
->rlock
);
553 chip_data
->mask_cache
= stm32_exti_set_bit(d
, stm32_bank
->imr_ofst
);
554 raw_spin_unlock(&chip_data
->rlock
);
556 if (d
->parent_data
->chip
)
557 irq_chip_unmask_parent(d
);
560 static int stm32_exti_h_set_type(struct irq_data
*d
, unsigned int type
)
562 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
563 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
564 struct hwspinlock
*hwlock
= chip_data
->host_data
->hwlock
;
565 void __iomem
*base
= chip_data
->host_data
->base
;
569 raw_spin_lock(&chip_data
->rlock
);
572 err
= hwspin_lock_timeout_in_atomic(hwlock
, HWSPNLCK_TIMEOUT
);
574 pr_err("%s can't get hwspinlock (%d)\n", __func__
, err
);
579 rtsr
= readl_relaxed(base
+ stm32_bank
->rtsr_ofst
);
580 ftsr
= readl_relaxed(base
+ stm32_bank
->ftsr_ofst
);
582 err
= stm32_exti_set_type(d
, type
, &rtsr
, &ftsr
);
586 writel_relaxed(rtsr
, base
+ stm32_bank
->rtsr_ofst
);
587 writel_relaxed(ftsr
, base
+ stm32_bank
->ftsr_ofst
);
591 hwspin_unlock_in_atomic(hwlock
);
593 raw_spin_unlock(&chip_data
->rlock
);
598 static int stm32_exti_h_set_wake(struct irq_data
*d
, unsigned int on
)
600 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
601 u32 mask
= BIT(d
->hwirq
% IRQS_PER_BANK
);
603 raw_spin_lock(&chip_data
->rlock
);
606 chip_data
->wake_active
|= mask
;
608 chip_data
->wake_active
&= ~mask
;
610 raw_spin_unlock(&chip_data
->rlock
);
615 static int stm32_exti_h_set_affinity(struct irq_data
*d
,
616 const struct cpumask
*dest
, bool force
)
618 if (d
->parent_data
->chip
)
619 return irq_chip_set_affinity_parent(d
, dest
, force
);
621 return IRQ_SET_MASK_OK_DONE
;
624 static int __maybe_unused
stm32_exti_h_suspend(void)
626 struct stm32_exti_chip_data
*chip_data
;
629 for (i
= 0; i
< stm32_host_data
->drv_data
->bank_nr
; i
++) {
630 chip_data
= &stm32_host_data
->chips_data
[i
];
631 raw_spin_lock(&chip_data
->rlock
);
632 stm32_chip_suspend(chip_data
, chip_data
->wake_active
);
633 raw_spin_unlock(&chip_data
->rlock
);
639 static void __maybe_unused
stm32_exti_h_resume(void)
641 struct stm32_exti_chip_data
*chip_data
;
644 for (i
= 0; i
< stm32_host_data
->drv_data
->bank_nr
; i
++) {
645 chip_data
= &stm32_host_data
->chips_data
[i
];
646 raw_spin_lock(&chip_data
->rlock
);
647 stm32_chip_resume(chip_data
, chip_data
->mask_cache
);
648 raw_spin_unlock(&chip_data
->rlock
);
652 static struct syscore_ops stm32_exti_h_syscore_ops
= {
653 #ifdef CONFIG_PM_SLEEP
654 .suspend
= stm32_exti_h_suspend
,
655 .resume
= stm32_exti_h_resume
,
659 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data
*host_data
)
661 stm32_host_data
= host_data
;
662 register_syscore_ops(&stm32_exti_h_syscore_ops
);
665 static void stm32_exti_h_syscore_deinit(void)
667 unregister_syscore_ops(&stm32_exti_h_syscore_ops
);
670 static int stm32_exti_h_retrigger(struct irq_data
*d
)
672 struct stm32_exti_chip_data
*chip_data
= irq_data_get_irq_chip_data(d
);
673 const struct stm32_exti_bank
*stm32_bank
= chip_data
->reg_bank
;
674 void __iomem
*base
= chip_data
->host_data
->base
;
675 u32 mask
= BIT(d
->hwirq
% IRQS_PER_BANK
);
677 writel_relaxed(mask
, base
+ stm32_bank
->swier_ofst
);
682 static struct irq_chip stm32_exti_h_chip
= {
683 .name
= "stm32-exti-h",
684 .irq_eoi
= stm32_exti_h_eoi
,
685 .irq_mask
= stm32_exti_h_mask
,
686 .irq_unmask
= stm32_exti_h_unmask
,
687 .irq_retrigger
= stm32_exti_h_retrigger
,
688 .irq_set_type
= stm32_exti_h_set_type
,
689 .irq_set_wake
= stm32_exti_h_set_wake
,
690 .flags
= IRQCHIP_MASK_ON_SUSPEND
,
691 .irq_set_affinity
= IS_ENABLED(CONFIG_SMP
) ? stm32_exti_h_set_affinity
: NULL
,
694 static struct irq_chip stm32_exti_h_chip_direct
= {
695 .name
= "stm32-exti-h-direct",
696 .irq_eoi
= irq_chip_eoi_parent
,
697 .irq_ack
= irq_chip_ack_parent
,
698 .irq_mask
= stm32_exti_h_mask
,
699 .irq_unmask
= stm32_exti_h_unmask
,
700 .irq_retrigger
= irq_chip_retrigger_hierarchy
,
701 .irq_set_type
= irq_chip_set_type_parent
,
702 .irq_set_wake
= stm32_exti_h_set_wake
,
703 .flags
= IRQCHIP_MASK_ON_SUSPEND
,
704 .irq_set_affinity
= IS_ENABLED(CONFIG_SMP
) ? irq_chip_set_affinity_parent
: NULL
,
707 static int stm32_exti_h_domain_alloc(struct irq_domain
*dm
,
709 unsigned int nr_irqs
, void *data
)
711 struct stm32_exti_host_data
*host_data
= dm
->host_data
;
712 struct stm32_exti_chip_data
*chip_data
;
714 struct irq_fwspec
*fwspec
= data
;
715 struct irq_fwspec p_fwspec
;
716 irq_hw_number_t hwirq
;
719 struct irq_chip
*chip
;
721 hwirq
= fwspec
->param
[0];
722 if (hwirq
>= host_data
->drv_data
->bank_nr
* IRQS_PER_BANK
)
725 bank
= hwirq
/ IRQS_PER_BANK
;
726 chip_data
= &host_data
->chips_data
[bank
];
728 event_trg
= readl_relaxed(host_data
->base
+ chip_data
->reg_bank
->trg_ofst
);
729 chip
= (event_trg
& BIT(hwirq
% IRQS_PER_BANK
)) ?
730 &stm32_exti_h_chip
: &stm32_exti_h_chip_direct
;
732 irq_domain_set_hwirq_and_chip(dm
, virq
, hwirq
, chip
, chip_data
);
734 if (!host_data
->drv_data
->desc_irqs
)
737 desc_irq
= host_data
->drv_data
->desc_irqs
[hwirq
];
738 if (desc_irq
!= EXTI_INVALID_IRQ
) {
739 p_fwspec
.fwnode
= dm
->parent
->fwnode
;
740 p_fwspec
.param_count
= 3;
741 p_fwspec
.param
[0] = GIC_SPI
;
742 p_fwspec
.param
[1] = desc_irq
;
743 p_fwspec
.param
[2] = IRQ_TYPE_LEVEL_HIGH
;
745 return irq_domain_alloc_irqs_parent(dm
, virq
, 1, &p_fwspec
);
752 stm32_exti_host_data
*stm32_exti_host_init(const struct stm32_exti_drv_data
*dd
,
753 struct device_node
*node
)
755 struct stm32_exti_host_data
*host_data
;
757 host_data
= kzalloc(sizeof(*host_data
), GFP_KERNEL
);
761 host_data
->drv_data
= dd
;
762 host_data
->chips_data
= kcalloc(dd
->bank_nr
,
763 sizeof(struct stm32_exti_chip_data
),
765 if (!host_data
->chips_data
)
768 host_data
->base
= of_iomap(node
, 0);
769 if (!host_data
->base
) {
770 pr_err("%pOF: Unable to map registers\n", node
);
771 goto free_chips_data
;
774 stm32_host_data
= host_data
;
779 kfree(host_data
->chips_data
);
787 stm32_exti_chip_data
*stm32_exti_chip_init(struct stm32_exti_host_data
*h_data
,
789 struct device_node
*node
)
791 const struct stm32_exti_bank
*stm32_bank
;
792 struct stm32_exti_chip_data
*chip_data
;
793 void __iomem
*base
= h_data
->base
;
795 stm32_bank
= h_data
->drv_data
->exti_banks
[bank_idx
];
796 chip_data
= &h_data
->chips_data
[bank_idx
];
797 chip_data
->host_data
= h_data
;
798 chip_data
->reg_bank
= stm32_bank
;
800 raw_spin_lock_init(&chip_data
->rlock
);
803 * This IP has no reset, so after hot reboot we should
804 * clear registers to avoid residue
806 writel_relaxed(0, base
+ stm32_bank
->imr_ofst
);
807 if (stm32_bank
->emr_ofst
!= UNDEF_REG
)
808 writel_relaxed(0, base
+ stm32_bank
->emr_ofst
);
810 pr_info("%pOF: bank%d\n", node
, bank_idx
);
815 static int __init
stm32_exti_init(const struct stm32_exti_drv_data
*drv_data
,
816 struct device_node
*node
)
818 struct stm32_exti_host_data
*host_data
;
819 unsigned int clr
= IRQ_NOREQUEST
| IRQ_NOPROBE
| IRQ_NOAUTOEN
;
821 struct irq_chip_generic
*gc
;
822 struct irq_domain
*domain
;
824 host_data
= stm32_exti_host_init(drv_data
, node
);
828 domain
= irq_domain_add_linear(node
, drv_data
->bank_nr
* IRQS_PER_BANK
,
829 &irq_exti_domain_ops
, NULL
);
831 pr_err("%pOFn: Could not register interrupt domain.\n",
837 ret
= irq_alloc_domain_generic_chips(domain
, IRQS_PER_BANK
, 1, "exti",
838 handle_edge_irq
, clr
, 0, 0);
840 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
842 goto out_free_domain
;
845 for (i
= 0; i
< drv_data
->bank_nr
; i
++) {
846 const struct stm32_exti_bank
*stm32_bank
;
847 struct stm32_exti_chip_data
*chip_data
;
849 stm32_bank
= drv_data
->exti_banks
[i
];
850 chip_data
= stm32_exti_chip_init(host_data
, i
, node
);
852 gc
= irq_get_domain_generic_chip(domain
, i
* IRQS_PER_BANK
);
854 gc
->reg_base
= host_data
->base
;
855 gc
->chip_types
->type
= IRQ_TYPE_EDGE_BOTH
;
856 gc
->chip_types
->chip
.irq_ack
= stm32_irq_ack
;
857 gc
->chip_types
->chip
.irq_mask
= irq_gc_mask_clr_bit
;
858 gc
->chip_types
->chip
.irq_unmask
= irq_gc_mask_set_bit
;
859 gc
->chip_types
->chip
.irq_set_type
= stm32_irq_set_type
;
860 gc
->chip_types
->chip
.irq_set_wake
= irq_gc_set_wake
;
861 gc
->suspend
= stm32_irq_suspend
;
862 gc
->resume
= stm32_irq_resume
;
863 gc
->wake_enabled
= IRQ_MSK(IRQS_PER_BANK
);
865 gc
->chip_types
->regs
.mask
= stm32_bank
->imr_ofst
;
866 gc
->private = (void *)chip_data
;
869 nr_irqs
= of_irq_count(node
);
870 for (i
= 0; i
< nr_irqs
; i
++) {
871 unsigned int irq
= irq_of_parse_and_map(node
, i
);
873 irq_set_handler_data(irq
, domain
);
874 irq_set_chained_handler(irq
, stm32_irq_handler
);
880 irq_domain_remove(domain
);
882 iounmap(host_data
->base
);
883 kfree(host_data
->chips_data
);
888 static const struct irq_domain_ops stm32_exti_h_domain_ops
= {
889 .alloc
= stm32_exti_h_domain_alloc
,
890 .free
= irq_domain_free_irqs_common
,
891 .xlate
= irq_domain_xlate_twocell
,
894 static void stm32_exti_remove_irq(void *data
)
896 struct irq_domain
*domain
= data
;
898 irq_domain_remove(domain
);
901 static int stm32_exti_remove(struct platform_device
*pdev
)
903 stm32_exti_h_syscore_deinit();
907 static int stm32_exti_probe(struct platform_device
*pdev
)
910 struct device
*dev
= &pdev
->dev
;
911 struct device_node
*np
= dev
->of_node
;
912 struct irq_domain
*parent_domain
, *domain
;
913 struct stm32_exti_host_data
*host_data
;
914 const struct stm32_exti_drv_data
*drv_data
;
916 host_data
= devm_kzalloc(dev
, sizeof(*host_data
), GFP_KERNEL
);
920 /* check for optional hwspinlock which may be not available yet */
921 ret
= of_hwspin_lock_get_id(np
, 0);
922 if (ret
== -EPROBE_DEFER
)
923 /* hwspinlock framework not yet ready */
927 host_data
->hwlock
= devm_hwspin_lock_request_specific(dev
, ret
);
928 if (!host_data
->hwlock
) {
929 dev_err(dev
, "Failed to request hwspinlock\n");
932 } else if (ret
!= -ENOENT
) {
933 /* note: ENOENT is a valid case (means 'no hwspinlock') */
934 dev_err(dev
, "Failed to get hwspinlock\n");
938 /* initialize host_data */
939 drv_data
= of_device_get_match_data(dev
);
941 dev_err(dev
, "no of match data\n");
944 host_data
->drv_data
= drv_data
;
946 host_data
->chips_data
= devm_kcalloc(dev
, drv_data
->bank_nr
,
947 sizeof(*host_data
->chips_data
),
949 if (!host_data
->chips_data
)
952 host_data
->base
= devm_platform_ioremap_resource(pdev
, 0);
953 if (IS_ERR(host_data
->base
))
954 return PTR_ERR(host_data
->base
);
956 for (i
= 0; i
< drv_data
->bank_nr
; i
++)
957 stm32_exti_chip_init(host_data
, i
, np
);
959 parent_domain
= irq_find_host(of_irq_find_parent(np
));
960 if (!parent_domain
) {
961 dev_err(dev
, "GIC interrupt-parent not found\n");
965 domain
= irq_domain_add_hierarchy(parent_domain
, 0,
966 drv_data
->bank_nr
* IRQS_PER_BANK
,
967 np
, &stm32_exti_h_domain_ops
,
971 dev_err(dev
, "Could not register exti domain\n");
975 ret
= devm_add_action_or_reset(dev
, stm32_exti_remove_irq
, domain
);
979 stm32_exti_h_syscore_init(host_data
);
984 /* platform driver only for MP1 */
985 static const struct of_device_id stm32_exti_ids
[] = {
986 { .compatible
= "st,stm32mp1-exti", .data
= &stm32mp1_drv_data
},
987 { .compatible
= "st,stm32mp13-exti", .data
= &stm32mp13_drv_data
},
990 MODULE_DEVICE_TABLE(of
, stm32_exti_ids
);
992 static struct platform_driver stm32_exti_driver
= {
993 .probe
= stm32_exti_probe
,
994 .remove
= stm32_exti_remove
,
996 .name
= "stm32_exti",
997 .of_match_table
= stm32_exti_ids
,
1001 static int __init
stm32_exti_arch_init(void)
1003 return platform_driver_register(&stm32_exti_driver
);
1006 static void __exit
stm32_exti_arch_exit(void)
1008 return platform_driver_unregister(&stm32_exti_driver
);
1011 arch_initcall(stm32_exti_arch_init
);
1012 module_exit(stm32_exti_arch_exit
);
1014 /* no platform driver for F4 and H7 */
1015 static int __init
stm32f4_exti_of_init(struct device_node
*np
,
1016 struct device_node
*parent
)
1018 return stm32_exti_init(&stm32f4xx_drv_data
, np
);
1021 IRQCHIP_DECLARE(stm32f4_exti
, "st,stm32-exti", stm32f4_exti_of_init
);
1023 static int __init
stm32h7_exti_of_init(struct device_node
*np
,
1024 struct device_node
*parent
)
1026 return stm32_exti_init(&stm32h7xx_drv_data
, np
);
1029 IRQCHIP_DECLARE(stm32h7_exti
, "st,stm32h7-exti", stm32h7_exti_of_init
);